JP4204671B2 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
JP4204671B2
JP4204671B2 JP25794998A JP25794998A JP4204671B2 JP 4204671 B2 JP4204671 B2 JP 4204671B2 JP 25794998 A JP25794998 A JP 25794998A JP 25794998 A JP25794998 A JP 25794998A JP 4204671 B2 JP4204671 B2 JP 4204671B2
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JP
Japan
Prior art keywords
silicon
effect transistor
field effect
semiconductor
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP25794998A
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English (en)
Japanese (ja)
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JP2000091570A5 (enExample
JP2000091570A (ja
Inventor
泰助 古川
匠 中畑
茂光 丸野
浩平 杉原
康隆 西岡
聡 山川
安紀 徳田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
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Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP25794998A priority Critical patent/JP4204671B2/ja
Priority to US09/243,480 priority patent/US6228728B1/en
Publication of JP2000091570A publication Critical patent/JP2000091570A/ja
Publication of JP2000091570A5 publication Critical patent/JP2000091570A5/ja
Application granted granted Critical
Publication of JP4204671B2 publication Critical patent/JP4204671B2/ja
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Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Recrystallisation Techniques (AREA)
JP25794998A 1998-09-11 1998-09-11 半導体装置の製造方法 Expired - Fee Related JP4204671B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP25794998A JP4204671B2 (ja) 1998-09-11 1998-09-11 半導体装置の製造方法
US09/243,480 US6228728B1 (en) 1998-09-11 1999-02-03 Method of fabricating semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP25794998A JP4204671B2 (ja) 1998-09-11 1998-09-11 半導体装置の製造方法

Publications (3)

Publication Number Publication Date
JP2000091570A JP2000091570A (ja) 2000-03-31
JP2000091570A5 JP2000091570A5 (enExample) 2005-09-29
JP4204671B2 true JP4204671B2 (ja) 2009-01-07

Family

ID=17313464

Family Applications (1)

Application Number Title Priority Date Filing Date
JP25794998A Expired - Fee Related JP4204671B2 (ja) 1998-09-11 1998-09-11 半導体装置の製造方法

Country Status (2)

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US (1) US6228728B1 (enExample)
JP (1) JP4204671B2 (enExample)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6368963B1 (en) * 2000-09-12 2002-04-09 Advanced Micro Devices, Inc. Passivation of semiconductor device surfaces using an iodine/ethanol solution
US6555880B2 (en) * 2001-06-07 2003-04-29 International Business Machines Corporation Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby
TWI229917B (en) * 2003-09-09 2005-03-21 Nanya Technology Corp Interconnect process and method for removing silicide
US7166528B2 (en) 2003-10-10 2007-01-23 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US7056796B2 (en) * 2003-12-03 2006-06-06 United Microelectronics Corp. Method for fabricating silicide by heating an epitaxial layer and a metal layer formed thereon
US7682940B2 (en) * 2004-12-01 2010-03-23 Applied Materials, Inc. Use of Cl2 and/or HCl during silicon epitaxial film formation
US7560352B2 (en) * 2004-12-01 2009-07-14 Applied Materials, Inc. Selective deposition
US7312128B2 (en) * 2004-12-01 2007-12-25 Applied Materials, Inc. Selective epitaxy process with alternating gas supply
KR100640354B1 (ko) 2004-12-23 2006-10-31 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
KR100638988B1 (ko) * 2004-12-23 2006-10-26 동부일렉트로닉스 주식회사 에피택셜 공정을 이용한 반도체 소자 및 그 평탄화 형성방법
JP4274566B2 (ja) * 2005-04-25 2009-06-10 エルピーダメモリ株式会社 半導体装置の製造方法
US7674337B2 (en) * 2006-04-07 2010-03-09 Applied Materials, Inc. Gas manifolds for use during epitaxial film formation
CN101496153A (zh) * 2006-07-31 2009-07-29 应用材料股份有限公司 形成含碳外延硅层的方法
KR101369355B1 (ko) * 2006-07-31 2014-03-04 어플라이드 머티어리얼스, 인코포레이티드 에피택셜 층 형성 동안에 형태를 제어하는 방법
JP2019075513A (ja) 2017-10-19 2019-05-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2513287B2 (ja) 1988-11-24 1996-07-03 日本電気株式会社 積層型メモリセルの製造方法
JP3042444B2 (ja) * 1996-12-27 2000-05-15 日本電気株式会社 半導体装置の製造方法
US5970352A (en) * 1998-04-23 1999-10-19 Kabushiki Kaisha Toshiba Field effect transistor having elevated source and drain regions and methods for manufacturing the same

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Publication number Publication date
US6228728B1 (en) 2001-05-08
JP2000091570A (ja) 2000-03-31

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