JP4187673B2 - 温度補償rram回路 - Google Patents
温度補償rram回路 Download PDFInfo
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- E03—WATER SUPPLY; SEWERAGE
- E03B—INSTALLATIONS OR METHODS FOR OBTAINING, COLLECTING, OR DISTRIBUTING WATER
- E03B9/00—Methods or installations for drawing-off water
- E03B9/02—Hydrants; Arrangements of valves therein; Keys for hydrants
- E03B9/08—Underground hydrants
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-
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- G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
- G01F15/00—Details of, or accessories for, apparatus of groups G01F1/00 - G01F13/00 insofar as such details or appliances are not adapted to particular types of such apparatus
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- G11C11/5685—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using storage elements comprising metal oxide memory material, e.g. perovskites
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Description
a)温度依存性素子を含む温度補償制御回路を提供する工程と、
b)温度補償制御回路によって、温度依存性センシング信号を発生させる工程と、
c)温度依存性センシング信号をメモリ抵抗器に印加して、メモリ抵抗器の抵抗の温度変化を補償する工程と、
d)メモリ抵抗器の補償状態をセンシングする工程と
を包含する。
a)温度依存性素子を含む温度補償基準信号回路を提供する工程と、
b)センシング信号をメモリ抵抗器に印加することによって、センス信号を発生させる工程と、
c)温度補償基準信号回路によって、少なくとも1つの温度依存性基準信号を発生させる工程と、
d)センス信号を少なくとも1つの基準信号と比較する工程と、
e)比較する工程に応答して出力信号を提供する工程と
を包含する。
a)第1の温度依存性素子を含む温度補償制御回路を提供する工程と、
b)第2の温度依存性素子を含む温度補償基準信号回路を提供する工程と、
c)温度補償制御回路によって、温度依存性センシング信号を発生させる工程と、
d)温度依存性センシング信号をメモリ抵抗器に印加して、センス信号を発生させる工程と、
e)温度補償基準信号回路によって少なくとも1つの温度依存性基準信号を発生させる工程と、
f)工程dのセンス信号を少なくとも1つの基準信号と比較する工程と、
g)比較する工程に応答して出力信号を提供する工程と
を包含する。
ただし、VDSATは飽和電圧であり、VTHはトランジスタ138の閾値電圧であり、両方とも、温度にあまり依存しない関数である。
温度変化に対するRRAM読み出し可能性を向上させる温度補償RRAMセンシング回路が開示される。回路は、温度補償回路の応答を制御して、メモリ抵抗器の抵抗状態の温度変化を補償する温度依存性信号を生成する温度依存性素子を含む。温度依存性素子は、メモリ抵抗器に供給されるセンシング信号を制御して、メモリ抵抗器の抵抗状態が温度変化に対して補償されるようにし得る。温度依存性素子は、比較回路に供給される基準信号を制御して、比較回路によって提供された出力信号が温度変化に対して補償されるようにし得る。温度依存性素子は、好ましくは、メモリ抵抗器と同じ材料およびプロセスから製造され得る。
102 抵抗セグメント
103 低電圧セグメント
104 低電圧セグメント
105 温度依存性電圧セグメント
106 温度依存性電圧セグメント
120 温度センサブロック
121 制御回路ブロック
122 メモリ抵抗器アレイ
123 センスアンプブロック
130 温度センサブロック
131 制御回路ブロック
132 メモリアレイブロック
133 センスアンプブロック
135 温度依存性素子
136 メモリ抵抗器
137 ダイオード
138 バイアスnMOSトランジスタ
139 電流負荷nMOSトランジスタ
Claims (27)
- 温度の変化に対して読み出し可能性を向上させる温度補償RRAMセンシング回路であって、該回路は、
a)温度依存性メモリ抵抗器アレイと、
b)温度依存性素子と、
c)該温度依存性素子と通信し、少なくとも1つの温度依存性出力信号に基づいて、該温度依存性メモリ抵抗器を流れる電流を制御して、該メモリ抵抗器の抵抗の温度変化を補償する、温度補償制御回路と
を含み、
該温度依存性素子は、電気的に、該メモリ抵抗器の複数の抵抗状態のいずれかに応じた抵抗状態にプログラム可能となるよう、該メモリ抵抗器と同材料及び同プロセスで製造されたものである、温度補償RRAMセンシング回路。 - 前記温度補償制御回路によって発生させられた前記温度依存性出力信号は、温度依存性電流源であり、該電流源の温度依存性が前記メモリ抵抗器の温度依存性と反対の方向であるので、該メモリ抵抗器にかかる電圧が温度変化に対して補償される、請求項1に記載の回路。
- 前記温度補償制御回路によって発生させられた前記温度依存性出力信号は、温度依存性電圧源であり、該電圧源の温度依存性が前記メモリ抵抗器の温度依存性と同じ方向であり、該メモリ抵抗器にわたる電流は温度変化に対して補償される、請求項1に記載の回路。
- センスアンプをさらに含み、該センスアンプはインバータを含む、請求項1に記載の回路。
- センスアンプをさらに含み、該センスアンプは比較回路を含む、請求項1に記載の回路。
- 前記温度補償制御回路は電流負荷nMOS回路である、請求項1に記載の回路。
- 前記温度補償制御回路は電流源pMOS回路である、請求項1に記載の回路。
- 前記メモリ抵抗器アレイは、1R1Dクロスポイントメモリアレイである、請求項1に記載の回路。
- 前記メモリ抵抗器アレイは、1R1Tランダムアクセスメモリアレイである、請求項1に記載の回路。
- 前記温度依存性素子に接続するダイオードをさらに含む、請求項1に記載の回路。
- 前記メモリ抵抗器アレイは2ビット抵抗状態を格納する、請求項1に記載の回路。
- 前記メモリ抵抗器アレイはマルチビット抵抗状態を格納する、請求項1に記載の回路。
- マルチビットセンシング回路をさらに含む、請求項12に記載の回路。
- 温度変化に対する読み出し可能性を向上させるRRAMデバイスにおける選択されたメモリ抵抗器の抵抗状態をセンスする方法であって、該方法は、
a)温度依存性素子を含む温度補償制御回路を提供する工程と、
b)該温度補償制御回路によって、少なくとも1つの温度依存性センシング信号を発生させる工程と、
c)該少なくとも1つの温度依存性センシング信号に基づいて該メモリ抵抗器を流れる電流を制御して、該メモリ抵抗器の抵抗の温度変化を補償する工程と、
d)該メモリ抵抗器の補償状態をセンシングする工程と
を包含し、
該温度依存性素子は、電気的に、該メモリ抵抗器の複数の抵抗状態のいずれかに応じた抵抗状態にプログラム可能となるよう、該メモリ抵抗器と同材料及び同プロセスで製造されたものである、方法。 - 前記温度依存性センシング信号は電流源であり、前記メモリ抵抗器の前記補償状態は該メモリ抵抗器にかかる電圧である、請求項14に記載の方法。
- 前記温度依存性センシング信号は電圧源であり、前記メモリ抵抗器の前記補償状態は該メモリ抵抗器を流れる電流である、請求項14に記載の方法。
- 温度変化に対する読み出し可能性を向上させる、温度補償RRAMセンシング回路であって、該回路は、
a)温度依存性メモリ抵抗器アレイと、
b)温度依存性素子と、
c)温度依存性素子と通信し、少なくとも1つの温度依存性基準信号を提供する、温度補償基準回路と、
d)該メモリ抵抗器アレイおよび該温度補償基準回路と通信する比較回路であって、少なくとも1つのメモリ抵抗器によって発生させられる少なくとも1つのセンス信号を該温度補償制御回路によって発生させられる少なくとも1つの基準信号と比較して、該比較に応答して少なくとも1つの出力信号を提供するように適応する、比較回路と
を含み、
該温度依存性素子は、電気的に、該メモリ抵抗器の複数の抵抗状態のいずれかに応じた抵抗状態にプログラム可能となるよう、該メモリ抵抗器と同材料及び同プロセスで製造されたものである、温度補償RRAMセンシング回路。 - 前記温度補償基準回路によって発生させられる前記温度依存性基準信号は、温度依存性電流源であり、該電流源の温度依存性は前記メモリ抵抗器の抵抗状態の温度依存性と同じ方向であり、それにより前記比較回路によって提供される前記出力信号は温度変化に対して補償される、請求項17に記載の回路。
- 前記温度補償基準回路によって発生させられる前記温度依存性基準信号は温度依存性電圧源であり、それにより該電圧源の温度依存性は前記メモリ抵抗器の抵抗状態の温度依存性と同じ方向であり、前記比較回路によって提供される前記出力信号は温度変化に対して補償される、請求項17に記載の回路。
- 前記温度依存性素子は、前記メモリ抵抗器と同じ材料およびプロセスから製造される、請求項17に記載の回路。
- 前記センス信号および前記少なくとも1つの基準信号は電圧である、請求項17に記載の回路。
- 前記センス信号および前記少なくとも1つの基準信号は電流である、請求項17に記載の回路。
- 前記出力信号は前記メモリ抵抗器の抵抗状態を示す、請求項17に記載の回路。
- 温度変化に対する読み出し可能性を向上させる、RRAMデバイスにおいて選択された温度依存性メモリ抵抗器の抵抗状態をセンスする方法であって、該方法は、
a)温度依存性素子を含む温度補償基準信号回路を提供する工程と、
b)センシング信号を該メモリ抵抗器に印加することによって、センス信号を発生させる工程と、
c)該温度補償基準信号回路によって、少なくとも1つの温度依存性基準信号を発生させる工程と、
d)該センス信号を該少なくとも1つの基準信号と比較する工程と、
e)該比較する工程に応答して出力信号を提供する工程と
を包含し、
該温度依存性素子は、電気的に、該メモリ抵抗器の複数の抵抗状態のいずれかに応じた抵抗状態にプログラム可能となるよう、該メモリ抵抗器と同材料及び同プロセスで製造されたものである、方法。 - 前記センシング信号は電流源であり、前記センス信号および前記少なくとも1つの基準信号は電圧である、請求項24に記載の方法。
- 前記センシング信号は電圧源であり、前記センス信号および前記少なくとも1つの基準信号は電流である、請求項24に記載の方法。
- 前記温度依存性素子は、前記メモリ抵抗器と同じ材料およびプロセスから製造される、請求項24に記載の方法。
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US10/384,985 US6868025B2 (en) | 2003-03-10 | 2003-03-10 | Temperature compensated RRAM circuit |
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JP4187673B2 true JP4187673B2 (ja) | 2008-11-26 |
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EP (1) | EP1460637B1 (ja) |
JP (1) | JP4187673B2 (ja) |
KR (1) | KR100601806B1 (ja) |
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JP2004273110A (ja) | 2004-09-30 |
US20040179414A1 (en) | 2004-09-16 |
TW200425161A (en) | 2004-11-16 |
US20050127403A1 (en) | 2005-06-16 |
EP1460637A1 (en) | 2004-09-22 |
US6868025B2 (en) | 2005-03-15 |
KR20040080357A (ko) | 2004-09-18 |
US6967884B2 (en) | 2005-11-22 |
KR100601806B1 (ko) | 2006-07-19 |
EP1460637B1 (en) | 2008-04-30 |
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