JP4159657B2 - 同期型半導体記憶装置 - Google Patents

同期型半導体記憶装置 Download PDF

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Publication number
JP4159657B2
JP4159657B2 JP19762598A JP19762598A JP4159657B2 JP 4159657 B2 JP4159657 B2 JP 4159657B2 JP 19762598 A JP19762598 A JP 19762598A JP 19762598 A JP19762598 A JP 19762598A JP 4159657 B2 JP4159657 B2 JP 4159657B2
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JP
Japan
Prior art keywords
address
signal
response
internal
latch circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP19762598A
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English (en)
Japanese (ja)
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JP2000030463A (ja
JP2000030463A5 (enExample
Inventor
隆 関矢
知久 和田
邦彦 小猿
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP19762598A priority Critical patent/JP4159657B2/ja
Priority to US09/212,308 priority patent/US6026036A/en
Publication of JP2000030463A publication Critical patent/JP2000030463A/ja
Publication of JP2000030463A5 publication Critical patent/JP2000030463A5/ja
Application granted granted Critical
Publication of JP4159657B2 publication Critical patent/JP4159657B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/225—Clock input buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/06—Address interface arrangements, e.g. address buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/10—Decoders

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP19762598A 1998-07-13 1998-07-13 同期型半導体記憶装置 Expired - Fee Related JP4159657B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP19762598A JP4159657B2 (ja) 1998-07-13 1998-07-13 同期型半導体記憶装置
US09/212,308 US6026036A (en) 1998-07-13 1998-12-16 Synchronous semiconductor memory device having set up time of external address signal reduced

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19762598A JP4159657B2 (ja) 1998-07-13 1998-07-13 同期型半導体記憶装置

Publications (3)

Publication Number Publication Date
JP2000030463A JP2000030463A (ja) 2000-01-28
JP2000030463A5 JP2000030463A5 (enExample) 2005-10-27
JP4159657B2 true JP4159657B2 (ja) 2008-10-01

Family

ID=16377605

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19762598A Expired - Fee Related JP4159657B2 (ja) 1998-07-13 1998-07-13 同期型半導体記憶装置

Country Status (2)

Country Link
US (1) US6026036A (enExample)
JP (1) JP4159657B2 (enExample)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5656953A (en) * 1995-05-31 1997-08-12 Texas Instruments Incorporated Low overhead memory designs for IC terminals
US6069839A (en) * 1998-03-20 2000-05-30 Cypress Semiconductor Corp. Circuit and method for implementing single-cycle read/write operation(s), and random access memory including the circuit and/or practicing the method
KR100301047B1 (ko) * 1998-10-02 2001-09-06 윤종용 2비트프리페치용칼럼어드레스디코더를갖는반도체메모리장치
US7173867B2 (en) * 2001-02-02 2007-02-06 Broadcom Corporation Memory redundancy circuit techniques
US6745354B2 (en) 2000-02-02 2004-06-01 Broadcom Corporation Memory redundancy implementation
US6411557B2 (en) * 2000-02-02 2002-06-25 Broadcom Corporation Memory architecture with single-port cell and dual-port (read and write) functionality
US8164362B2 (en) * 2000-02-02 2012-04-24 Broadcom Corporation Single-ended sense amplifier with sample-and-hold reference
JP4156781B2 (ja) 2000-05-30 2008-09-24 株式会社東芝 半導体メモリ集積回路
US6714467B2 (en) * 2002-03-19 2004-03-30 Broadcom Corporation Block redundancy implementation in heirarchical RAM's
JP2003123478A (ja) 2001-10-03 2003-04-25 Fujitsu Ltd 半導体装置及び半導体記憶装置
WO2004076928A2 (en) 2003-02-21 2004-09-10 Middleby Corporation Self-cleaning oven
JP4641726B2 (ja) * 2004-01-07 2011-03-02 パナソニック株式会社 半導体記憶装置
US8087407B2 (en) 2004-03-23 2012-01-03 Middleby Corporation Conveyor oven apparatus and method
US9585400B2 (en) 2004-03-23 2017-03-07 The Middleby Corporation Conveyor oven apparatus and method
US20110048244A1 (en) * 2009-08-28 2011-03-03 Wiker John H Apparatus and method for controlling a combustion blower in a gas-fueled conveyor oven
US8839714B2 (en) 2009-08-28 2014-09-23 The Middleby Corporation Apparatus and method for controlling a conveyor oven
US8811109B2 (en) * 2012-02-27 2014-08-19 Qualcomm Incorporated Memory pre-decoder circuits employing pulse latch(es) for reducing memory access times, and related systems and methods
US8923090B1 (en) 2013-09-24 2014-12-30 Lsi Corporation Address decoding circuits for reducing address and memory enable setup time
JP6556435B2 (ja) * 2014-09-17 2019-08-07 東芝メモリ株式会社 半導体集積回路
IT202000029771A1 (it) * 2020-12-03 2022-06-03 Sk Hynix Inc Architettura di latch

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5086414A (en) * 1988-11-17 1992-02-04 Hitachi, Ltd. Semiconductor device having latch means
JPH09147595A (ja) * 1995-11-24 1997-06-06 Nec Corp 半導体記憶装置
JPH1074396A (ja) * 1996-08-30 1998-03-17 Nec Corp 半導体記憶装置
JP3361018B2 (ja) * 1996-11-11 2003-01-07 株式会社東芝 半導体記憶装置
JPH10334689A (ja) * 1997-05-30 1998-12-18 Fujitsu Ltd 半導体記憶装置

Also Published As

Publication number Publication date
JP2000030463A (ja) 2000-01-28
US6026036A (en) 2000-02-15

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