JP4074697B2 - 半導体装置 - Google Patents

半導体装置 Download PDF

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Publication number
JP4074697B2
JP4074697B2 JP32832297A JP32832297A JP4074697B2 JP 4074697 B2 JP4074697 B2 JP 4074697B2 JP 32832297 A JP32832297 A JP 32832297A JP 32832297 A JP32832297 A JP 32832297A JP 4074697 B2 JP4074697 B2 JP 4074697B2
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JP
Japan
Prior art keywords
power supply
potential
circuit
node
supply potential
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP32832297A
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English (en)
Japanese (ja)
Other versions
JPH11162194A (ja
JPH11162194A5 (enExample
Inventor
玄 森下
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP32832297A priority Critical patent/JP4074697B2/ja
Priority to US09/087,868 priority patent/US6038189A/en
Publication of JPH11162194A publication Critical patent/JPH11162194A/ja
Priority to US09/503,719 priority patent/US6434078B1/en
Publication of JPH11162194A5 publication Critical patent/JPH11162194A5/ja
Application granted granted Critical
Publication of JP4074697B2 publication Critical patent/JP4074697B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/12005—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising voltage or current generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
JP32832297A 1997-11-28 1997-11-28 半導体装置 Expired - Fee Related JP4074697B2 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP32832297A JP4074697B2 (ja) 1997-11-28 1997-11-28 半導体装置
US09/087,868 US6038189A (en) 1997-11-28 1998-06-01 Semiconductor device allowing external setting of internal power supply voltage generated by a voltage down converter at the time of testing
US09/503,719 US6434078B1 (en) 1997-11-28 2000-02-14 Semiconductor device allowing external setting of internal power supply voltage generated by a voltage down converter at the time of testing

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP32832297A JP4074697B2 (ja) 1997-11-28 1997-11-28 半導体装置

Publications (3)

Publication Number Publication Date
JPH11162194A JPH11162194A (ja) 1999-06-18
JPH11162194A5 JPH11162194A5 (enExample) 2005-06-30
JP4074697B2 true JP4074697B2 (ja) 2008-04-09

Family

ID=18208951

Family Applications (1)

Application Number Title Priority Date Filing Date
JP32832297A Expired - Fee Related JP4074697B2 (ja) 1997-11-28 1997-11-28 半導体装置

Country Status (2)

Country Link
US (2) US6038189A (enExample)
JP (1) JP4074697B2 (enExample)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4216415B2 (ja) 1999-08-31 2009-01-28 株式会社ルネサステクノロジ 半導体装置
JP4822572B2 (ja) * 1999-09-02 2011-11-24 ルネサスエレクトロニクス株式会社 半導体記憶装置
US6185139B1 (en) * 2000-01-12 2001-02-06 Motorola, Inc. Circuit and method for enabling semiconductor device burn-in
JP2001351383A (ja) * 2000-06-07 2001-12-21 Mitsubishi Electric Corp 半導体集積回路装置
JP4565716B2 (ja) * 2000-08-30 2010-10-20 ルネサスエレクトロニクス株式会社 半導体装置
US6522589B1 (en) * 2000-09-27 2003-02-18 Kabushiki Kaisha Toshiba Semiconductor apparatus and mode setting method for semiconductor apparatus
JP4656747B2 (ja) * 2001-03-30 2011-03-23 ルネサスエレクトロニクス株式会社 半導体装置
US6529436B1 (en) * 2001-04-26 2003-03-04 Lsi Logic Corporation Supply degradation compensation for memory self time circuits
JP4073708B2 (ja) * 2001-07-25 2008-04-09 株式会社ルネサステクノロジ 半導体集積回路
JP3866111B2 (ja) * 2002-01-18 2007-01-10 株式会社ルネサステクノロジ 半導体集積回路及びバーンイン方法
JP2004055009A (ja) 2002-07-18 2004-02-19 Renesas Technology Corp 半導体メモリモジュール
JP3852447B2 (ja) * 2003-06-03 2006-11-29 セイコーエプソン株式会社 出力回路及びそれを内蔵する半導体集積回路
JP2005071556A (ja) * 2003-08-28 2005-03-17 Renesas Technology Corp 半導体記憶装置および半導体集積回路装置
JP4516294B2 (ja) * 2003-09-30 2010-08-04 パナソニック株式会社 半導体装置及び半導体装置の製造方法
KR100626367B1 (ko) * 2003-10-02 2006-09-20 삼성전자주식회사 내부전압 발생장치
JP2005222580A (ja) * 2004-02-03 2005-08-18 Renesas Technology Corp 半導体記憶装置
JP4703133B2 (ja) * 2004-05-25 2011-06-15 ルネサスエレクトロニクス株式会社 内部電圧発生回路および半導体集積回路装置
EP1624559B1 (en) * 2004-08-04 2010-10-20 Infineon Technologies AG Method for controlling a switching converter and control device for a switching converter
US7248531B2 (en) * 2005-08-03 2007-07-24 Mosaid Technologies Incorporated Voltage down converter for high speed memory
US20070236275A1 (en) * 2006-04-07 2007-10-11 Mellanox Technologies Ltd. Global Reference Voltage Distribution System With Local Reference Voltages Referred to Ground And Supply
US9111602B2 (en) * 2006-04-07 2015-08-18 Mellanox Technologies, Ltd. Accurate global reference voltage distribution system with local reference voltages referred to local ground and locally supplied voltage
US7613043B2 (en) * 2006-05-15 2009-11-03 Apple Inc. Shifting reference values to account for voltage sag
US7639542B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Maintenance operations for multi-level data storage cells
US7852690B2 (en) * 2006-05-15 2010-12-14 Apple Inc. Multi-chip package for a flash memory
US7911834B2 (en) * 2006-05-15 2011-03-22 Apple Inc. Analog interface for a flash memory die
US7701797B2 (en) * 2006-05-15 2010-04-20 Apple Inc. Two levels of voltage regulation supplied for logic and data programming voltage of a memory device
US7551486B2 (en) * 2006-05-15 2009-06-23 Apple Inc. Iterative memory cell charging based on reference cell value
US7568135B2 (en) 2006-05-15 2009-07-28 Apple Inc. Use of alternative value in cell detection
US7639531B2 (en) * 2006-05-15 2009-12-29 Apple Inc. Dynamic cell bit resolution
US8000134B2 (en) 2006-05-15 2011-08-16 Apple Inc. Off-die charge pump that supplies multiple flash devices
US7511646B2 (en) * 2006-05-15 2009-03-31 Apple Inc. Use of 8-bit or higher A/D for NAND cell value
KR100799109B1 (ko) * 2006-06-30 2008-01-29 주식회사 하이닉스반도체 반도체 소자
KR100873613B1 (ko) * 2006-11-14 2008-12-12 주식회사 하이닉스반도체 반도체 메모리 장치의 전압 생성 회로 및 방법
JP4774000B2 (ja) * 2007-03-19 2011-09-14 富士通セミコンダクター株式会社 半導体集積回路及び半導体集積回路が組み込まれた半導体装置
JP5040014B2 (ja) * 2007-09-26 2012-10-03 ルネサスエレクトロニクス株式会社 半導体集積回路装置
KR100937939B1 (ko) * 2008-04-24 2010-01-21 주식회사 하이닉스반도체 반도체 소자의 내부전압 생성회로
JP5706635B2 (ja) * 2010-06-24 2015-04-22 ルネサスエレクトロニクス株式会社 半導体装置及びその内部回路の制御方法
JP2012234601A (ja) * 2011-05-06 2012-11-29 Toshiba Corp 不揮発性半導体メモリ
KR20130015942A (ko) * 2011-08-05 2013-02-14 에스케이하이닉스 주식회사 반도체메모리장치

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04243098A (ja) * 1991-01-16 1992-08-31 Matsushita Electron Corp 半導体記憶装置
JP2945508B2 (ja) * 1991-06-20 1999-09-06 三菱電機株式会社 半導体装置
KR950008453B1 (ko) 1992-03-31 1995-07-31 삼성전자주식회사 내부전원전압 발생회로
JP3495787B2 (ja) * 1994-06-30 2004-02-09 株式会社ルネサステクノロジ 半導体装置
JP3705842B2 (ja) * 1994-08-04 2005-10-12 株式会社ルネサステクノロジ 半導体装置
JPH08138382A (ja) 1994-11-09 1996-05-31 Nec Corp スタティックメモリ装置
US5762072A (en) * 1995-05-25 1998-06-09 Conlan; Robert W. Comparator apparatus and system for activity monitors
KR0149577B1 (ko) 1995-06-12 1998-12-01 김광호 반도체 메모리 장치의 내부 전원전압 발생회로
JPH0955098A (ja) * 1995-08-15 1997-02-25 Mitsubishi Electric Corp 半導体記憶装置
JPH09167488A (ja) * 1995-12-18 1997-06-24 Mitsubishi Electric Corp 半導体記憶装置
JP3839873B2 (ja) * 1996-07-03 2006-11-01 株式会社ルネサステクノロジ 半導体集積回路装置
JPH10199295A (ja) * 1997-01-10 1998-07-31 Fujitsu Ltd 半導体集積回路
JP4046382B2 (ja) * 1997-03-27 2008-02-13 株式会社ルネサステクノロジ 半導体集積回路装置
JP3313081B2 (ja) * 1999-03-05 2002-08-12 三菱電機株式会社 半導体装置

Also Published As

Publication number Publication date
US6038189A (en) 2000-03-14
US6434078B1 (en) 2002-08-13
JPH11162194A (ja) 1999-06-18
US20020021602A1 (en) 2002-02-21

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