JP4030875B2 - 高速メモリシステムにおいて読出しタイミングを同期させる方法 - Google Patents
高速メモリシステムにおいて読出しタイミングを同期させる方法 Download PDFInfo
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- JP4030875B2 JP4030875B2 JP2002568374A JP2002568374A JP4030875B2 JP 4030875 B2 JP4030875 B2 JP 4030875B2 JP 2002568374 A JP2002568374 A JP 2002568374A JP 2002568374 A JP2002568374 A JP 2002568374A JP 4030875 B2 JP4030875 B2 JP 4030875B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1689—Synchronisation and timing concerns
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4234—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus
- G06F13/4243—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a memory bus with synchronous protocol
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4072—Circuits for initialization, powering up or down, clearing memory or presetting
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/20—Memory cell initialisation circuits, e.g. when powering up or down, memory clear, latent image memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2281—Timing of a read operation
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- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Dram (AREA)
- Memory System (AREA)
- Read Only Memory (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Description
Claims (7)
- 少なくとも1つのメモリデバイスを有するメモリシステムを較正する方法であって、前記少なくとも1つのメモリデバイスはそれぞれ、少なくとも1つの読出しクロック線、少なくとも1つのコマンド線、少なくとも1つのフラグ線、および少なくとも1つのデータ線を介して、メモリコントローラ、フラグ源、および読出しクロック源に結合され、
(a)タイミングオフセットを0読出しクロックサイクルに設定するステップと、
(b)前記少なくとも1つのコマンド線を介して前記メモリコントローラから前記少なくとも1つのメモリデバイスのうちの選択されたメモリデバイスに較正コマンドを送るステップと、
(c)前記メモリコントローラから前記少なくとも1つのフラグ線上で、メモリデバイスからのデータの出力タイミングを較正するためのフラグ信号を送るステップであって、前記フラグ信号は、前記較正コマンドを送った時に対して相対的に読出しクロックサイクルの前記タイミングオフセットに等しい遅延後に送るステップと、
(d)前記選択されたメモリデバイスにおいて前記フラグ信号を受け取り、前記選択されたメモリデバイスにおいて前記フラグ信号を受け取った時に対して相対的に所定数の読出しクロックサイクルが経過した後で基準較正パターンを出力するステップと、
(e)前記メモリコントローラにおいて前記フラグ信号を前記フラグ線上で受け取り、前記メモリコントローラにおいて前記フラグ信号を受け取ってから所定数の読出しクロックサイクルが経過した後で、前記データ線からデータを読み取るのを開始するステップと、
(f)前記データが前記基準較正パターンに対応する場合に、前記タイミングオフセットが十分であると判断するステップと、
(g)前記データが前記基準較正パターンに対応しない場合に、前記タイミングオフセットが不十分であると判断するステップと、
(h)前記タイミングオフセットが不十分である場合に、前記タイミングオフセットを1読出しクロックサイクルだけ増加させて、ステップ(b)、(c)、(d)、(e)、(f)、(g)を繰り返すステップとを含むことを特徴とする方法。 - 前記選択されたメモリデバイスは、前記メモリコントローラから最も遠くに位置するメモリデバイスであることを特徴とする請求項1に記載の方法。
- 前記メモリシステムは、前記メモリコントローラに対して最も遠いメモリデバイスから最も近いメモリデバイスまで順番に並んだ複数のメモリデバイスを有し、
(i)順番に残りの各メモリデバイスに対してステップ(b)、(c)、(d)、(e)、(f)、(g)、(h)を繰り返すステップをさらに含むことを特徴とする請求項2に記載の方法。 - 複数のメモリデバイスを有するメモリモジュールであって、
前記複数のメモリデバイスの各々は、
メモリアレイと、
該メモリアレイに結合された少なくとも1つのデータ信号線と、
制御回路と、
該制御回路に結合された、読出しクロック信号を受け取るための読出しクロック信号線と、
前記制御回路に結合されたフラグ信号線であって、メモリデバイスからのデータの出力タイミングを較正するためのフラグ信号を受け取るためのフラグ信号線と、
前記制御回路に結合された、コマンドを受け取るための少なくとも1つのコマンド信号線と、
読出しコマンドのアサートとフラグ信号のアサートとの間に外部メモリコントローラが待機すべき提案遅延を記憶した構成メモリと
を備え、
前記制御回路は、前記制御回路が前記フラグ信号を受け取ってから所定数の読出しクロックサイクル後に、前に受け入れたコマンドに関連するデータを前記メモリデバイスに前記アレイから前記少なくとも1つのデータ信号線上に出力させることを特徴とするメモリモジュール。 - 前記提案遅延は、デバイス最低読出し待ち時間遅延およびシステム待ち時間からなることを特徴とする請求項4に記載のメモリモジュール。
- プロセッサと、
前記プロセッサに結合されたメモリコントローラと、
該メモリコントローラに結合された少なくとも1つのメモリモジュールであって、前記少なくとも1つのメモリモジュールの各々は複数のメモリデバイスを有し、当該複数のメモリデバイスは少なくとも1組で構成されているメモリモジュールとを備え、
前記複数のメモリデバイスの各々は、
読出しクロック信号を受け取るための読出しクロック信号線であって、前記少なくとも1つのメモリモジュールの他のメモリモジュールにおける対応の複数のメモリデバイスの読出しクロック信号線に結合された読出しクロック信号線と、
複数のコマンドを受け取るための少なくとも1つのコマンド信号線と、
メモリデバイスからのデータの出力タイミングを較正するためのフラグ信号を受け取るためのフラグ信号線であって、前記少なくとも1つのメモリモジュールの他のメモリモジュールにおける対応の複数のメモリデバイスのフラグ信号線に結合されたフラグ信号線とを備え、
前記フラグ信号は、該フラグ信号を受け取ってから所定数の読出しクロックサイクル後に、前記コマンド信号線上で受け取った前に受け入れたコマンドに対応するデータを前記メモリデバイスに出力させ、
前記少なくとも1つのメモリモジュールはそれぞれさらに、読出しコマンドのアサートとフラグ信号のアサートとの間に前記メモリコントローラが待機すべき提案遅延を記憶した構成メモリを備えることを特徴とするコンピュータシステム。 - 前記提案遅延は、デバイス最低読出し待ち時間遅延およびシステム待ち時間からなることを特徴とする請求項6に記載のコンピュータシステム。
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US09/790,538 US6445624B1 (en) | 2001-02-23 | 2001-02-23 | Method of synchronizing read timing in a high speed memory system |
PCT/US2002/002764 WO2002069341A2 (en) | 2001-02-23 | 2002-02-01 | A method of synchronizing read timing in a high speed memory system |
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JP2007174529A Division JP5415677B2 (ja) | 2001-02-23 | 2007-07-02 | 高速メモリシステムにおいて読出しタイミングを同期させる方法 |
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JP4030875B2 true JP4030875B2 (ja) | 2008-01-09 |
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JP2007174529A Expired - Fee Related JP5415677B2 (ja) | 2001-02-23 | 2007-07-02 | 高速メモリシステムにおいて読出しタイミングを同期させる方法 |
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US (3) | US6445624B1 (ja) |
EP (1) | EP1374244B1 (ja) |
JP (2) | JP4030875B2 (ja) |
KR (1) | KR100626506B1 (ja) |
CN (1) | CN100385570C (ja) |
AT (1) | ATE303649T1 (ja) |
DE (1) | DE60205877T2 (ja) |
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KR20220101502A (ko) | 2021-01-11 | 2022-07-19 | 에스케이하이닉스 주식회사 | 메모리 장치, 이를 포함하는 메모리 시스템 및 그것의 동작 방법 |
CN116206648B (zh) * | 2022-01-27 | 2024-02-20 | 北京超弦存储器研究院 | 动态存储器及其读写方法、存储装置 |
CN115080469A (zh) * | 2022-05-13 | 2022-09-20 | 珠海全志科技股份有限公司 | 一种存储器传输时延校准方法及装置 |
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US4519034A (en) | 1982-06-30 | 1985-05-21 | Elxsi | I/O Bus clock |
JPH05250280A (ja) * | 1992-03-09 | 1993-09-28 | Fujitsu Ltd | データ転送方法 |
US5748914A (en) | 1995-10-19 | 1998-05-05 | Rambus, Inc. | Protocol for communication with dynamic memory |
US5917760A (en) * | 1996-09-20 | 1999-06-29 | Sldram, Inc. | De-skewing data signals in a memory system |
JPH1166851A (ja) * | 1997-08-21 | 1999-03-09 | Mitsubishi Electric Corp | クロックシフト回路装置、クロックシフト回路およびこれを用いた同期型半導体記憶装置 |
JP3832947B2 (ja) * | 1997-11-14 | 2006-10-11 | 富士通株式会社 | データ転送メモリ装置 |
JP2000011681A (ja) * | 1998-06-22 | 2000-01-14 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP2000076122A (ja) * | 1998-08-31 | 2000-03-14 | Hitachi Ltd | データ処理装置 |
JP2000163965A (ja) * | 1998-11-27 | 2000-06-16 | Mitsubishi Electric Corp | 同期型半導体記憶装置 |
JP3706772B2 (ja) * | 1999-07-12 | 2005-10-19 | 富士通株式会社 | 半導体集積回路 |
DE60019081D1 (de) * | 2000-01-31 | 2005-05-04 | St Microelectronics Srl | Verschachtelter Burst-Speicher mit Burst-Zugriff bei synchronen Lesezyklen, wobei die beiden untergeordneten Speicherfelder unabhängig lesbar sind mit wahlfreiem Zugriff während asynchroner Lesezyklen |
US6445624B1 (en) * | 2001-02-23 | 2002-09-03 | Micron Technology, Inc. | Method of synchronizing read timing in a high speed memory system |
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EP1374244B1 (en) | 2005-08-31 |
DE60205877T2 (de) | 2006-06-29 |
EP1374244A2 (en) | 2004-01-02 |
CN1503974A (zh) | 2004-06-09 |
US6847583B2 (en) | 2005-01-25 |
CN100385570C (zh) | 2008-04-30 |
KR20040005877A (ko) | 2004-01-16 |
JP2004525453A (ja) | 2004-08-19 |
JP5415677B2 (ja) | 2014-02-12 |
US6445624B1 (en) | 2002-09-03 |
US6724666B2 (en) | 2004-04-20 |
DE60205877D1 (de) | 2005-10-06 |
ATE303649T1 (de) | 2005-09-15 |
US20020118578A1 (en) | 2002-08-29 |
WO2002069341A3 (en) | 2002-11-28 |
US20030002355A1 (en) | 2003-01-02 |
US20040160832A1 (en) | 2004-08-19 |
WO2002069341A2 (en) | 2002-09-06 |
KR100626506B1 (ko) | 2006-09-20 |
JP2007299522A (ja) | 2007-11-15 |
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