JP5044805B2 - 実ライトレイテンシーを測定しデータキャプチャの開始をデータのメモリ装置への到着に正確にアライメントする方法および装置 - Google Patents
実ライトレイテンシーを測定しデータキャプチャの開始をデータのメモリ装置への到着に正確にアライメントする方法および装置 Download PDFInfo
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- JP5044805B2 JP5044805B2 JP2009025395A JP2009025395A JP5044805B2 JP 5044805 B2 JP5044805 B2 JP 5044805B2 JP 2009025395 A JP2009025395 A JP 2009025395A JP 2009025395 A JP2009025395 A JP 2009025395A JP 5044805 B2 JP5044805 B2 JP 5044805B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/02—Detection or location of defective auxiliary circuits, e.g. defective refresh counters
- G11C29/028—Detection or location of defective auxiliary circuits, e.g. defective refresh counters with adaption or trimming of parameters
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
- G06F13/1694—Configuration of memory controller to different memory types
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
- G11C29/50012—Marginal testing, e.g. race, voltage or current testing of timing
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/22—Control and timing of internal memory operations
- G11C2207/2254—Calibration
Description
Claims (11)
- テストデータパターンの実受信タイムとテストデータパターンの予測受信タイムとの差を決定するためのエンコーダと、
入力データを受信するための入力端子パッドと、
前記入力端子パッドに結合した第1の入力端子を有するデシリアライザと、
前記デシリアライザの第2の入力端子に結合した出力端子を有し、前記デシリアライザに出力信号を供給する遅延回路と
を含み、
前記デシリアライザは、前記出力信号に応答して前記入力データのキャプチャを開始し、
前記遅延回路は、決定されたタイム差によって前記入力データの前記キャプチャの前記開始タイムを遅延させて、前記開始タイムを前記メモリへの前記入力データの到着にアライメントさせる
ことを特徴とするメモリ装置。 - 請求項1において、前記遅延回路は、
予め定めた数値を受信するように結合した入力端子を有し、前記数値をカウント開始点として使用する少なくとも1つのカウンタと、
前記少なくとも1つのカウンタに結合した検出回路であって、前記少なくとも1つのカウンタが、前記カウント中に、予め定めた数値に何時達したかを判断し、前記予め定めた数値に達した時に前記入力データの前記キャプチャを開始させる前記出力信号を供給する検出回路と
をさらに備えたことを特徴とするメモリ装置。 - 請求項2において、前記少なくとも1つのカウンタは、ラッチに結合した第1および第2のカウンタを含み、前記第1のカウンタは、前記数値を受信し、前記第2のカウンタとは独立にカウントを行うことを特徴とするメモリ装置。
- 請求項2において、前記少なくとも1つのカウンタは、減算カウンタであり、前記予め定めた数値は、0であることを特徴とするメモリ装置。
- プロセッサユニットと、前記プロセッサユニットに接続したメモリ装置とを含むプロセッサシステムであって、前記メモリ装置は、
テストデータパターンの実受信タイムとテストデータパターンの予測受信タイムとの差を決定するためのエンコーダと、
入力データを受信するための入力端子パッドと、
前記入力端子パッドに結合された第1の入力端子を有するデシリアライザと、
前記デシリアライザの第2の入力端子に結合した出力端子を有し、前記デシリアライザに出力信号を供給する遅延回路と
を含み、
前記デシリアライザは、前記出力信号に応答して前記入力データのキャプチャを開始し、
前記遅延回路は、決定されたタイム差によって前記入力データの前記キャプチャの前記開始タイムを遅延させて、前記開始タイムを前記メモリへの前記入力データの到着にアライメントさせる
ことを特徴とするプロセッサシステム。 - 請求項5において、前記遅延回路は、
予め定めた数値を受信するように結合した入力端子を有し、前記数値をカウント開始点として使用する少なくとも1つのカウンタと、
前記少なくとも1つのカウンタに結合した検出回路であって、前記少なくとも1つのカウンタが前記カウント中に予め定めた数値に何時達したかを判断し、前記予め定めた数値に達した時に前記入力データの前記キャプチャを開始させる出力信号を供給する検出回路と
をさらに備えたことを特徴とするプロセッサシステム。 - 請求項6において、前記少なくとも1つのカウンタは、ラッチに結合した第1および第2のカウンタを含み、
前記第1のカウンタは、前記数値を受信し、前記第2のカウンタとは独立にカウントを行う
ことを特徴とするプロセッサシステム。 - 請求項6において、前記少なくとも1つのカウンタは、減算カウンタであり、前記予め定めた数値は、0であることを特徴とするプロセッサシステム。
- 請求項5において、前記プロセッサユニットと前記メモリ装置とは、同一集積回路チップ上にあることを特徴とするプロセッサシステム。
- データをメモリ装置にライトする方法であって、
テストデータパターンの実受信タイムとテストデータパターンの予測受信タイムとの差を決定するステップと、
前記メモリ装置にライトコマンドを送出するステップと、
前記メモリ装置の指定されたライトレイテンシー時間に基づいて指定された時間だけ待機した後で、前記データを前記メモリ装置に送出するステップと、
決定されたタイム差によって前記データのキャプチャ開始を遅延させて、前記データの前記キャプチャ開始を前記メモリ装置による前記データの受信にアライメントさせるステップと
を含むことを特徴とする方法。 - 請求項10において、前記遅延ステップは、前記決定されたタイム差に対応する予め定めたクロックサイクル数だけ前記キャプチャ開始を遅延させるステップをさらに含むことを特徴とする方法。
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US09/874,289 US6697926B2 (en) | 2001-06-06 | 2001-06-06 | Method and apparatus for determining actual write latency and accurately aligning the start of data capture with the arrival of data at a memory device |
US09/874,289 | 2001-06-06 |
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JP2003502706A Division JP4672978B2 (ja) | 2001-06-06 | 2002-06-06 | 実ライトレイテンシーを測定しデータキャプチャの開始をデータのメモリ装置への到着に正確にアライメントする方法および装置 |
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JP2009104651A JP2009104651A (ja) | 2009-05-14 |
JP5044805B2 true JP5044805B2 (ja) | 2012-10-10 |
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JP2003502706A Expired - Fee Related JP4672978B2 (ja) | 2001-06-06 | 2002-06-06 | 実ライトレイテンシーを測定しデータキャプチャの開始をデータのメモリ装置への到着に正確にアライメントする方法および装置 |
JP2009025395A Expired - Fee Related JP5044805B2 (ja) | 2001-06-06 | 2009-02-05 | 実ライトレイテンシーを測定しデータキャプチャの開始をデータのメモリ装置への到着に正確にアライメントする方法および装置 |
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US (1) | US6697926B2 (ja) |
EP (1) | EP1407455A2 (ja) |
JP (2) | JP4672978B2 (ja) |
KR (1) | KR100596177B1 (ja) |
CN (1) | CN100565481C (ja) |
AU (1) | AU2002312350A1 (ja) |
WO (1) | WO2002099661A2 (ja) |
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-
2001
- 2001-06-06 US US09/874,289 patent/US6697926B2/en not_active Expired - Lifetime
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2002
- 2002-06-06 AU AU2002312350A patent/AU2002312350A1/en not_active Abandoned
- 2002-06-06 WO PCT/US2002/017849 patent/WO2002099661A2/en active Application Filing
- 2002-06-06 CN CNB028153650A patent/CN100565481C/zh not_active Expired - Fee Related
- 2002-06-06 KR KR1020037016031A patent/KR100596177B1/ko not_active IP Right Cessation
- 2002-06-06 EP EP02739714A patent/EP1407455A2/en not_active Withdrawn
- 2002-06-06 JP JP2003502706A patent/JP4672978B2/ja not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
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US20020188816A1 (en) | 2002-12-12 |
JP2004529453A (ja) | 2004-09-24 |
KR20040016881A (ko) | 2004-02-25 |
JP2009104651A (ja) | 2009-05-14 |
CN100565481C (zh) | 2009-12-02 |
US6697926B2 (en) | 2004-02-24 |
AU2002312350A1 (en) | 2002-12-16 |
WO2002099661A2 (en) | 2002-12-12 |
KR100596177B1 (ko) | 2006-07-03 |
CN1636196A (zh) | 2005-07-06 |
JP4672978B2 (ja) | 2011-04-20 |
WO2002099661A3 (en) | 2003-11-13 |
EP1407455A2 (en) | 2004-04-14 |
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