JP4008651B2 - 半導体装置とその製造方法 - Google Patents

半導体装置とその製造方法 Download PDF

Info

Publication number
JP4008651B2
JP4008651B2 JP2000333732A JP2000333732A JP4008651B2 JP 4008651 B2 JP4008651 B2 JP 4008651B2 JP 2000333732 A JP2000333732 A JP 2000333732A JP 2000333732 A JP2000333732 A JP 2000333732A JP 4008651 B2 JP4008651 B2 JP 4008651B2
Authority
JP
Japan
Prior art keywords
region
layer
electrode layer
gate electrode
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP2000333732A
Other languages
English (en)
Japanese (ja)
Other versions
JP2002141469A (ja
JP2002141469A5 (enExample
Inventor
正之 市毛
理一郎 白田
紀久子 杉前
敦祥 佐藤
祐司 竹内
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP2000333732A priority Critical patent/JP4008651B2/ja
Priority to US09/984,718 priority patent/US6921960B2/en
Publication of JP2002141469A publication Critical patent/JP2002141469A/ja
Publication of JP2002141469A5 publication Critical patent/JP2002141469A5/ja
Application granted granted Critical
Publication of JP4008651B2 publication Critical patent/JP4008651B2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/212—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only capacitors

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
JP2000333732A 2000-10-31 2000-10-31 半導体装置とその製造方法 Expired - Lifetime JP4008651B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP2000333732A JP4008651B2 (ja) 2000-10-31 2000-10-31 半導体装置とその製造方法
US09/984,718 US6921960B2 (en) 2000-10-31 2001-10-31 Capacitor element with an opening portion formed in a peripheral circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000333732A JP4008651B2 (ja) 2000-10-31 2000-10-31 半導体装置とその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006128379A Division JP4634963B2 (ja) 2006-05-02 2006-05-02 半導体装置とその製造方法

Publications (3)

Publication Number Publication Date
JP2002141469A JP2002141469A (ja) 2002-05-17
JP2002141469A5 JP2002141469A5 (enExample) 2005-06-09
JP4008651B2 true JP4008651B2 (ja) 2007-11-14

Family

ID=18809763

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2000333732A Expired - Lifetime JP4008651B2 (ja) 2000-10-31 2000-10-31 半導体装置とその製造方法

Country Status (2)

Country Link
US (1) US6921960B2 (enExample)
JP (1) JP4008651B2 (enExample)

Families Citing this family (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4313941B2 (ja) * 2000-09-29 2009-08-12 株式会社東芝 半導体記憶装置
US6590255B2 (en) * 2000-09-29 2003-07-08 Kabushiki Kaisha Toshiba Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
KR100481870B1 (ko) * 2002-12-06 2005-04-11 삼성전자주식회사 일회적 프로그래밍이 가능한 롬을 구비하는 반도체 장치및 그 제조방법
KR100628419B1 (ko) * 2003-02-26 2006-09-28 가부시끼가이샤 도시바 개선된 게이트 전극을 포함하는 불휘발성 반도체 기억 장치
US6909139B2 (en) 2003-06-27 2005-06-21 Infineon Technologies Ag One transistor flash memory cell
US7029968B2 (en) * 2003-12-05 2006-04-18 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming a PIP capacitor
JP4761745B2 (ja) * 2004-09-21 2011-08-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
JP4113199B2 (ja) 2005-04-05 2008-07-09 株式会社東芝 半導体装置
JP4129009B2 (ja) * 2005-05-31 2008-07-30 株式会社東芝 半導体集積回路装置
JP4664813B2 (ja) * 2005-12-21 2011-04-06 株式会社東芝 半導体記憶装置
JP4799196B2 (ja) 2006-01-31 2011-10-26 株式会社東芝 不揮発性半導体記憶装置
JP2007311566A (ja) * 2006-05-18 2007-11-29 Toshiba Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法
JP4864756B2 (ja) * 2007-02-09 2012-02-01 株式会社東芝 Ｎａｎｄ型不揮発性半導体記憶装置
JP2009010281A (ja) * 2007-06-29 2009-01-15 Renesas Technology Corp 半導体装置およびその製造方法
JP5129541B2 (ja) 2007-10-15 2013-01-30 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP5134975B2 (ja) * 2008-01-08 2013-01-30 株式会社東芝 半導体集積回路
KR101065140B1 (ko) 2008-03-17 2011-09-16 가부시끼가이샤 도시바 반도체 기억 장치
JP4660566B2 (ja) * 2008-03-17 2011-03-30 株式会社東芝 不揮発性半導体記憶装置
JP2009231445A (ja) * 2008-03-21 2009-10-08 Toshiba Corp 半導体記憶装置
JP2009295781A (ja) * 2008-06-05 2009-12-17 Toshiba Corp 半導体装置及びその製造方法
JP2010098067A (ja) 2008-10-15 2010-04-30 Toshiba Corp 半導体装置
JP2010251469A (ja) * 2009-04-14 2010-11-04 Toshiba Corp 半導体集積装置
JP5513927B2 (ja) 2010-02-25 2014-06-04 株式会社東芝 半導体装置と不揮発性半導体記憶装置
JP5732742B2 (ja) * 2010-04-16 2015-06-10 富士通セミコンダクター株式会社 半導体集積回路装置およびその製造方法
JP2012043856A (ja) * 2010-08-16 2012-03-01 Toshiba Corp 半導体装置およびその製造方法
US8415217B2 (en) * 2011-03-31 2013-04-09 Freescale Semiconductor, Inc. Patterning a gate stack of a non-volatile memory (NVM) with formation of a capacitor
US9082555B2 (en) 2011-08-22 2015-07-14 Micron Technology, Inc. Structure comprising multiple capacitors and methods for forming the structure
KR20130023995A (ko) * 2011-08-30 2013-03-08 에스케이하이닉스 주식회사 반도체 소자 및 이의 제조방법
JP2013143482A (ja) * 2012-01-11 2013-07-22 Toshiba Corp 半導体装置および半導体装置の製造方法
JP2013207123A (ja) 2012-03-29 2013-10-07 Toshiba Corp 半導体装置
KR102056867B1 (ko) 2013-03-04 2020-01-22 삼성전자주식회사 반도체 소자 및 그 제조방법
JP2015060895A (ja) * 2013-09-17 2015-03-30 株式会社東芝 半導体装置
US9398237B2 (en) * 2014-04-30 2016-07-19 Sony Corporation Image sensor with floating diffusion interconnect capacitor
JP6466148B2 (ja) * 2014-11-19 2019-02-06 東芝メモリ株式会社 半導体記憶装置
US9911665B2 (en) * 2014-12-30 2018-03-06 Globalfoundries Singapore Pte. Ltd. Integrated circuits, methods of forming the same, and methods of determining gate dielectric layer electrical thickness in integrated circuits
US9673207B2 (en) * 2015-08-20 2017-06-06 Sandisk Technologies Llc Shallow trench isolation trenches and methods for NAND memory
KR102411071B1 (ko) * 2017-05-29 2022-06-21 삼성전자주식회사 반도체 장치

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5550072A (en) * 1994-08-30 1996-08-27 National Semiconductor Corporation Method of fabrication of integrated circuit chip containing EEPROM and capacitor
JP3415712B2 (ja) * 1995-09-19 2003-06-09 松下電器産業株式会社 半導体装置及びその製造方法
TW396454B (en) * 1997-06-24 2000-07-01 Matsushita Electrics Corporati Semiconductor device and method for fabricating the same
SG74643A1 (en) * 1997-07-24 2000-08-22 Matsushita Electronics Corp Semiconductor device and method for fabricating the same
JP3519583B2 (ja) * 1997-09-19 2004-04-19 株式会社東芝 不揮発性半導体記憶装置およびその製造方法
JP2000150789A (ja) 1998-11-10 2000-05-30 Toshiba Corp 半導体集積回路
JP2000223570A (ja) * 1999-02-04 2000-08-11 Toshiba Corp 半導体装置及びその製造方法
US6291307B1 (en) * 1999-08-06 2001-09-18 Chartered Semiconductor Manufacturing Ltd. Method and structure to make planar analog capacitor on the top of a STI structure

Also Published As

Publication number Publication date
JP2002141469A (ja) 2002-05-17
US6921960B2 (en) 2005-07-26
US20020070402A1 (en) 2002-06-13

Similar Documents

Publication Publication Date Title
JP4008651B2 (ja) 半導体装置とその製造方法
US6781193B2 (en) Non-volatile memory device having floating trap type memory cell and method of forming the same
KR100681378B1 (ko) 반도체 장치 및 그 제조 방법
JP4898083B2 (ja) トレンチ隔離された半導体素子の形成方法及びそれによって形成されたトレンチ隔離された半導体素子
US7999328B2 (en) Isolation trench having first and second trench areas of different widths
US6391722B1 (en) Method of making nonvolatile memory having high capacitive coupling ratio
US9577115B2 (en) Semiconductor devices having air gaps
US11610842B2 (en) Memory device and method of manufacturing the same
US7339242B2 (en) NAND-type flash memory devices and fabrication methods thereof
CN102646665A (zh) 半导体器件及其制造方法
KR100672939B1 (ko) 저항 소자를 구비하는 반도체 소자 및 그 형성 방법
JP2010080853A (ja) 不揮発性半導体記憶装置およびその製造方法
US6590255B2 (en) Semiconductor memory device having memory cell section and peripheral circuit section and method of manufacturing the same
US9059300B2 (en) Nonvolatile semiconductor memory device having element isolating region of trench type
CN107039450A (zh) 半导体装置及其制造方法
US7825497B2 (en) Method of manufacture of contact plug and interconnection layer of semiconductor device
US8012826B2 (en) Semiconductor device and manufacturing method of same
CN112436011B (zh) 闪存器件及其制造方法
JP4634963B2 (ja) 半導体装置とその製造方法
US20040079984A1 (en) Polysilicon self-aligned contact and a polysilicon common source line and method of forming the same
TW202545293A (zh) 三維記憶體裝置及其形成方法
KR100671583B1 (ko) 반도체 소자 및 그 제조 방법

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20040820

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20040820

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20060220

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20060307

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20060502

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20070109

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20070309

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20070821

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20070830

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100907

Year of fee payment: 3

R151 Written notification of patent or utility model registration

Ref document number: 4008651

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R151

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100907

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110907

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110907

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120907

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120907

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20130907

Year of fee payment: 6

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313111

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

EXPY Cancellation because of completion of term