JP3988227B2 - 半導体チップ搭載用基板の製造法および半導体装置 - Google Patents

半導体チップ搭載用基板の製造法および半導体装置 Download PDF

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Publication number
JP3988227B2
JP3988227B2 JP33005297A JP33005297A JP3988227B2 JP 3988227 B2 JP3988227 B2 JP 3988227B2 JP 33005297 A JP33005297 A JP 33005297A JP 33005297 A JP33005297 A JP 33005297A JP 3988227 B2 JP3988227 B2 JP 3988227B2
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JP
Japan
Prior art keywords
metal layer
semiconductor chip
layer
manufacturing
etching
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP33005297A
Other languages
English (en)
Japanese (ja)
Other versions
JPH11163207A (ja
JPH11163207A5 (enExample
Inventor
英博 中村
聡夫 山崎
茂樹 市村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
Resonac Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Showa Denko Materials Co Ltd, Resonac Corp filed Critical Hitachi Chemical Co Ltd
Priority to JP33005297A priority Critical patent/JP3988227B2/ja
Publication of JPH11163207A publication Critical patent/JPH11163207A/ja
Publication of JPH11163207A5 publication Critical patent/JPH11163207A5/ja
Application granted granted Critical
Publication of JP3988227B2 publication Critical patent/JP3988227B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Wire Bonding (AREA)
JP33005297A 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置 Expired - Fee Related JP3988227B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33005297A JP3988227B2 (ja) 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33005297A JP3988227B2 (ja) 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2006293148A Division JP4428376B2 (ja) 2006-10-27 2006-10-27 半導体チップ搭載用基板の製造法

Publications (3)

Publication Number Publication Date
JPH11163207A JPH11163207A (ja) 1999-06-18
JPH11163207A5 JPH11163207A5 (enExample) 2005-07-14
JP3988227B2 true JP3988227B2 (ja) 2007-10-10

Family

ID=18228248

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33005297A Expired - Fee Related JP3988227B2 (ja) 1997-12-01 1997-12-01 半導体チップ搭載用基板の製造法および半導体装置

Country Status (1)

Country Link
JP (1) JP3988227B2 (enExample)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW522530B (en) * 1999-08-02 2003-03-01 Toyo Kohan Co Ltd Semiconductor package unit
TW512467B (en) 1999-10-12 2002-12-01 North Kk Wiring circuit substrate and manufacturing method therefor
JP3752949B2 (ja) * 2000-02-28 2006-03-08 日立化成工業株式会社 配線基板及び半導体装置
JP4023076B2 (ja) 2000-07-27 2007-12-19 富士通株式会社 表裏導通基板及びその製造方法
JP2002050870A (ja) * 2000-08-01 2002-02-15 Hitachi Chem Co Ltd 接続基板とその接続基板を用いた多層配線板と半導体パッケージ用基板と半導体パッケージ並びに接続基板の製造方法とその方法を用いた多層配線板の製造方法と半導体パッケージ用基板の製造方法と半導体パッケージの製造方法
KR100695303B1 (ko) * 2000-10-31 2007-03-14 삼성전자주식회사 제어 신호부 및 그 제조 방법과 이를 포함하는 액정 표시장치 및 그 제조 방법
JP4586058B2 (ja) * 2001-03-28 2010-11-24 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 層間接続部材
JP3682500B2 (ja) * 2001-04-16 2005-08-10 日本重化学工業株式会社 プリント配線基板、及び、プリント配線基板の製造方法
WO2003021668A1 (en) * 2001-08-31 2003-03-13 Hitachi Chemical Co.,Ltd. Wiring board, semiconductor device and method for producing them
AU2003220938A1 (en) * 2002-05-28 2003-12-12 Hitachi Chemical Co., Ltd. Substrate, wiring board, semiconductor package-use substrate, semiconductor package and production methods for them
JP2004079773A (ja) 2002-08-19 2004-03-11 Taiyo Yuden Co Ltd 多層プリント配線板及びその製造方法
CN102970829B (zh) * 2003-09-12 2016-01-20 独立行政法人产业技术综合研究所 衬底的制备方法
JP2005340372A (ja) * 2004-05-25 2005-12-08 Toyo Ink Mfg Co Ltd 配線回路基板用の積層体ユニットの製造方法
JP2006147810A (ja) * 2004-11-19 2006-06-08 Casio Comput Co Ltd 半導体装置およびその製造方法
JP4798557B2 (ja) * 2005-01-31 2011-10-19 独立行政法人産業技術総合研究所 プローブカード、およびその製造方法。
US7759782B2 (en) 2006-04-07 2010-07-20 Tessera, Inc. Substrate for a microelectronic package and method of fabricating thereof
JP4407702B2 (ja) * 2007-02-09 2010-02-03 富士通株式会社 表裏導通基板の製造方法および表裏導電基板
KR100866577B1 (ko) * 2007-09-28 2008-11-03 삼성전기주식회사 인쇄회로기판의 층간 도통방법
JP4603080B2 (ja) * 2009-01-13 2010-12-22 テセラ・インターコネクト・マテリアルズ，インコーポレイテッド 配線回路基板
JP5152601B2 (ja) * 2010-06-01 2013-02-27 日立化成工業株式会社 薄板状物品を用いた接続基板の製造方法と多層配線板の製造方法
US9365947B2 (en) 2013-10-04 2016-06-14 Invensas Corporation Method for preparing low cost substrates
US9646917B2 (en) 2014-05-29 2017-05-09 Invensas Corporation Low CTE component with wire bond interconnects

Also Published As

Publication number Publication date
JPH11163207A (ja) 1999-06-18

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