JP3955810B2 - ウェーハの諸部分を電気的に分離するためのシステム - Google Patents

ウェーハの諸部分を電気的に分離するためのシステム Download PDF

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Publication number
JP3955810B2
JP3955810B2 JP2002298439A JP2002298439A JP3955810B2 JP 3955810 B2 JP3955810 B2 JP 3955810B2 JP 2002298439 A JP2002298439 A JP 2002298439A JP 2002298439 A JP2002298439 A JP 2002298439A JP 3955810 B2 JP3955810 B2 JP 3955810B2
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Japan
Prior art keywords
wafer
insulating layer
conductor
semiconductor wafer
via structure
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Expired - Fee Related
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JP2002298439A
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English (en)
Japanese (ja)
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JP2003151978A5 (enExample
JP2003151978A (ja
Inventor
ピーター・ジョージ・ハートウェル
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HP Inc
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Hewlett Packard Co
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Publication date
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Publication of JP2003151978A publication Critical patent/JP2003151978A/ja
Publication of JP2003151978A5 publication Critical patent/JP2003151978A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/217—Through-semiconductor vias, e.g. TSVs comprising ring-shaped isolation structures outside of the via holes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W44/00—Electrical arrangements for controlling or matching impedance
    • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]
    • H10W44/203—Electrical connections
    • H10W44/209—Vertical interconnections, e.g. vias
    • H10W44/212—Coaxial feed-throughs in substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
JP2002298439A 2001-10-18 2002-10-11 ウェーハの諸部分を電気的に分離するためのシステム Expired - Fee Related JP3955810B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/035,792 2001-10-18
US10/035,792 US6750516B2 (en) 2001-10-18 2001-10-18 Systems and methods for electrically isolating portions of wafers

Publications (3)

Publication Number Publication Date
JP2003151978A JP2003151978A (ja) 2003-05-23
JP2003151978A5 JP2003151978A5 (enExample) 2005-09-29
JP3955810B2 true JP3955810B2 (ja) 2007-08-08

Family

ID=21884809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002298439A Expired - Fee Related JP3955810B2 (ja) 2001-10-18 2002-10-11 ウェーハの諸部分を電気的に分離するためのシステム

Country Status (3)

Country Link
US (2) US6750516B2 (enExample)
EP (1) EP1306901A3 (enExample)
JP (1) JP3955810B2 (enExample)

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JP4439976B2 (ja) 2004-03-31 2010-03-24 Ｎｅｃエレクトロニクス株式会社 半導体装置およびその製造方法
JP4568039B2 (ja) 2004-06-30 2010-10-27 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール
JP4795677B2 (ja) * 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 半導体装置およびそれを用いた半導体モジュール、ならびに半導体装置の製造方法
JP4577687B2 (ja) * 2005-03-17 2010-11-10 エルピーダメモリ株式会社 半導体装置
CN101589543B (zh) 2005-05-18 2012-10-31 科隆科技公司 微机电换能器
US8247945B2 (en) 2005-05-18 2012-08-21 Kolo Technologies, Inc. Micro-electro-mechanical transducers
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US7560813B2 (en) 2005-06-14 2009-07-14 John Trezza Chip-based thermo-stack
US8456015B2 (en) 2005-06-14 2013-06-04 Cufer Asset Ltd. L.L.C. Triaxial through-chip connection
US7687400B2 (en) 2005-06-14 2010-03-30 John Trezza Side stacking apparatus and method
US7942182B2 (en) 2005-06-14 2011-05-17 Cufer Asset Ltd. L.L.C. Rigid-backed, membrane-based chip tooling
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US7767493B2 (en) 2005-06-14 2010-08-03 John Trezza Post & penetration interconnection
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US7807550B2 (en) * 2005-06-17 2010-10-05 Dalsa Semiconductor Inc. Method of making MEMS wafers
US9601474B2 (en) * 2005-07-22 2017-03-21 Invensas Corporation Electrically stackable semiconductor wafer and chip packages
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JP4847072B2 (ja) * 2005-08-26 2011-12-28 本田技研工業株式会社 半導体集積回路装置およびその製造方法
WO2007023947A1 (ja) * 2005-08-26 2007-03-01 Hitachi, Ltd. 半導体装置の製造方法および半導体装置
US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same
JP5021992B2 (ja) * 2005-09-29 2012-09-12 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
JP2007180529A (ja) * 2005-12-02 2007-07-12 Nec Electronics Corp 半導体装置およびその製造方法
US20070126085A1 (en) 2005-12-02 2007-06-07 Nec Electronics Corporation Semiconductor device and method of manufacturing the same
WO2007089206A1 (en) * 2006-02-01 2007-08-09 Silex Microsystems Ab Vias and method of making
EP2002477B1 (en) 2006-03-27 2011-12-21 Philips Intellectual Property & Standards GmbH A fabrication method for a low ohmic through substrate connection for semiconductor carriers
US7687397B2 (en) 2006-06-06 2010-03-30 John Trezza Front-end processed wafer having through-chip connections
US20080067665A1 (en) * 2006-09-20 2008-03-20 Azniza Binti Abd Aziz Via structure
US7670874B2 (en) * 2007-02-16 2010-03-02 John Trezza Plated pillar package formation
JP5563186B2 (ja) * 2007-03-30 2014-07-30 ピーエスフォー ルクスコ エスエイアールエル 半導体装置及びその製造方法
US7799612B2 (en) * 2007-06-25 2010-09-21 Spansion Llc Process applying die attach film to singulated die
US20090146295A1 (en) * 2007-12-11 2009-06-11 Hidefumi Narita Ceramic substrate having thermal via
US8242593B2 (en) * 2008-01-27 2012-08-14 International Business Machines Corporation Clustered stacked vias for reliable electronic substrates
WO2010023812A1 (ja) * 2008-08-28 2010-03-04 パナソニック株式会社 半導体装置
KR20100042021A (ko) * 2008-10-15 2010-04-23 삼성전자주식회사 반도체 칩, 스택 모듈, 메모리 카드 및 반도체 칩의 제조 방법
TWI470766B (zh) * 2009-03-10 2015-01-21 日月光半導體製造股份有限公司 晶片結構、晶圓結構以及晶片製程
JP5150665B2 (ja) * 2010-03-03 2013-02-20 株式会社東芝 不揮発性半導体記憶装置
US8455349B2 (en) * 2010-04-28 2013-06-04 Headway Technologies, Inc. Layered chip package and method of manufacturing same
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Also Published As

Publication number Publication date
EP1306901A3 (en) 2005-09-14
US6750516B2 (en) 2004-06-15
US20030077877A1 (en) 2003-04-24
US7115505B2 (en) 2006-10-03
EP1306901A2 (en) 2003-05-02
US20040192029A1 (en) 2004-09-30
JP2003151978A (ja) 2003-05-23

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