ATE538496T1 - Herstellungsmethode für eine niederohmige substratdurchgangsverbindung für halbleiterträger - Google Patents

Herstellungsmethode für eine niederohmige substratdurchgangsverbindung für halbleiterträger

Info

Publication number
ATE538496T1
ATE538496T1 AT07735144T AT07735144T ATE538496T1 AT E538496 T1 ATE538496 T1 AT E538496T1 AT 07735144 T AT07735144 T AT 07735144T AT 07735144 T AT07735144 T AT 07735144T AT E538496 T1 ATE538496 T1 AT E538496T1
Authority
AT
Austria
Prior art keywords
connection
twi
front surface
low
integrated circuit
Prior art date
Application number
AT07735144T
Other languages
English (en)
Inventor
Gereon Vogtmeier
Roger Steadman
Ralf Dorscheid
Jeroen Jonkers
Original Assignee
Koninkl Philips Electronics Nv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv filed Critical Koninkl Philips Electronics Nv
Application granted granted Critical
Publication of ATE538496T1 publication Critical patent/ATE538496T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
AT07735144T 2006-03-27 2007-03-16 Herstellungsmethode für eine niederohmige substratdurchgangsverbindung für halbleiterträger ATE538496T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP06111756 2006-03-27
PCT/IB2007/050914 WO2007110799A2 (en) 2006-03-27 2007-03-16 Low ohmic through substrate interconnection for semiconductor carriers

Publications (1)

Publication Number Publication Date
ATE538496T1 true ATE538496T1 (de) 2012-01-15

Family

ID=38267584

Family Applications (1)

Application Number Title Priority Date Filing Date
AT07735144T ATE538496T1 (de) 2006-03-27 2007-03-16 Herstellungsmethode für eine niederohmige substratdurchgangsverbindung für halbleiterträger

Country Status (6)

Country Link
US (1) US8633572B2 (de)
EP (1) EP2002477B1 (de)
JP (1) JP5431918B2 (de)
CN (1) CN101410972B (de)
AT (1) ATE538496T1 (de)
WO (1) WO2007110799A2 (de)

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US8630033B2 (en) 2008-12-23 2014-01-14 Silex Microsystems Ab Via structure and method thereof
SE533992C2 (sv) 2008-12-23 2011-03-22 Silex Microsystems Ab Elektrisk anslutning i en struktur med isolerande och ledande lager
US8729713B2 (en) 2008-12-23 2014-05-20 Silex Microsystems Ab Via structure and method thereof
JP5330115B2 (ja) * 2009-06-17 2013-10-30 浜松ホトニクス株式会社 積層配線基板
US8487425B2 (en) 2011-06-23 2013-07-16 International Business Machines Corporation Optimized annular copper TSV
EP2597677B1 (de) * 2011-11-23 2014-08-06 ams AG Halbleitervorrichtung mit Substratdurchgang, der von einer Lötkugel abgedeckt wird, und zugehöriges Herstellungsverfahren
US9496337B2 (en) * 2013-12-19 2016-11-15 Infineon Technologies Austria Ag Method for producing a semiconductor device having a beveled edge termination
US9526468B2 (en) 2014-09-09 2016-12-27 General Electric Company Multiple frame acquisition for exposure control in X-ray medical imagers

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US3962052A (en) * 1975-04-14 1976-06-08 International Business Machines Corporation Process for forming apertures in silicon bodies
JPH0821675B2 (ja) 1987-11-13 1996-03-04 日産自動車株式会社 半導体装置
JPH047845A (ja) * 1990-04-25 1992-01-13 Mitsubishi Electric Corp 半導体装置の製造方法
CN1187800C (zh) * 1997-04-03 2005-02-02 株式会社山武 电路板以及检测器及其制造方法
JP3184493B2 (ja) * 1997-10-01 2001-07-09 松下電子工業株式会社 電子装置の製造方法
US7786562B2 (en) * 1997-11-11 2010-08-31 Volkan Ozguz Stackable semiconductor chip layer comprising prefabricated trench interconnect vias
FR2797140B1 (fr) * 1999-07-30 2001-11-02 Thomson Csf Sextant Procede de fabrication de connexions traversantes dans un substrat et substrat equipe de telles connexions
US6649993B2 (en) * 2001-03-16 2003-11-18 Agilent Technologies, Inc. Simplified upper electrode contact structure for PIN diode active pixel sensor
JP2002289623A (ja) 2001-03-28 2002-10-04 Toshiba Corp 半導体装置及びその製造方法
JP3941416B2 (ja) 2001-04-26 2007-07-04 ソニー株式会社 高周波モジュール装置及びその製造方法
US6787916B2 (en) * 2001-09-13 2004-09-07 Tru-Si Technologies, Inc. Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity
US6750516B2 (en) 2001-10-18 2004-06-15 Hewlett-Packard Development Company, L.P. Systems and methods for electrically isolating portions of wafers
GB2392307B8 (en) * 2002-07-26 2006-09-20 Detection Technology Oy Semiconductor structure for imaging detectors
SE526366C3 (sv) * 2003-03-21 2005-10-26 Silex Microsystems Ab Elektriska anslutningar i substrat
US6908856B2 (en) 2003-04-03 2005-06-21 Interuniversitair Microelektronica Centrum (Imec) Method for producing electrical through hole interconnects and devices made thereof
EP2704187B1 (de) 2003-04-03 2015-08-19 Imec Verfahren zur Herstellung von elektrischen Durchkontaktierungen und damit hergestellte Vorrichtung
EP1519410A1 (de) 2003-09-25 2005-03-30 Interuniversitair Microelektronica Centrum vzw ( IMEC) Methode zur Herstellung von elektrisch leitenden Durchführungen
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US7633167B2 (en) * 2005-09-29 2009-12-15 Nec Electronics Corporation Semiconductor device and method for manufacturing same

Also Published As

Publication number Publication date
CN101410972A (zh) 2009-04-15
US20090079021A1 (en) 2009-03-26
EP2002477B1 (de) 2011-12-21
US8633572B2 (en) 2014-01-21
WO2007110799A2 (en) 2007-10-04
WO2007110799A3 (en) 2007-12-13
JP2009531849A (ja) 2009-09-03
EP2002477A2 (de) 2008-12-17
JP5431918B2 (ja) 2014-03-05
CN101410972B (zh) 2010-09-08

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