JP3690827B2 - メモリ装置付電子回路 - Google Patents

メモリ装置付電子回路 Download PDF

Info

Publication number
JP3690827B2
JP3690827B2 JP20524894A JP20524894A JP3690827B2 JP 3690827 B2 JP3690827 B2 JP 3690827B2 JP 20524894 A JP20524894 A JP 20524894A JP 20524894 A JP20524894 A JP 20524894A JP 3690827 B2 JP3690827 B2 JP 3690827B2
Authority
JP
Japan
Prior art keywords
memory device
memory
electronic circuit
test
column
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP20524894A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0785700A (ja
Inventor
サチデブ マノジ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of JPH0785700A publication Critical patent/JPH0785700A/ja
Application granted granted Critical
Publication of JP3690827B2 publication Critical patent/JP3690827B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/34—Accessing multiple bits simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C2029/5006—Current

Landscapes

  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Tests Of Electronic Circuits (AREA)
JP20524894A 1993-09-01 1994-08-30 メモリ装置付電子回路 Expired - Fee Related JP3690827B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP93202555 1993-09-01
NL93202555:4 1993-09-01

Publications (2)

Publication Number Publication Date
JPH0785700A JPH0785700A (ja) 1995-03-31
JP3690827B2 true JP3690827B2 (ja) 2005-08-31

Family

ID=8214072

Family Applications (1)

Application Number Title Priority Date Filing Date
JP20524894A Expired - Fee Related JP3690827B2 (ja) 1993-09-01 1994-08-30 メモリ装置付電子回路

Country Status (7)

Country Link
US (1) US5491665A (enExample)
JP (1) JP3690827B2 (enExample)
KR (1) KR100339321B1 (enExample)
DE (1) DE69429225T2 (enExample)
MY (1) MY131610A (enExample)
SG (1) SG48339A1 (enExample)
TW (1) TW260788B (enExample)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07159496A (ja) * 1993-10-12 1995-06-23 At & T Global Inf Solutions Internatl Inc 集積回路の検査のための装置及びその方法
EP0691612A1 (en) * 1994-07-07 1996-01-10 International Business Machines Corporation A test circuit of embedded arrays in mixed logic and memory chips
KR0142638B1 (ko) * 1994-12-27 1998-08-17 김주용 플래쉬 메모리 장치
JP2783243B2 (ja) * 1996-02-06 1998-08-06 日本電気株式会社 Ｃｍｏｓ集積回路の故障検出方法及び装置
JPH09292438A (ja) * 1996-04-30 1997-11-11 Toshiba Corp Ｃｍｏｓ集積回路装置、その検査方法及び検査装置
US5745405A (en) * 1996-08-26 1998-04-28 Taiwan Semiconductor Manufacturing Company, Ltd Process leakage evaluation and measurement method
US6551857B2 (en) * 1997-04-04 2003-04-22 Elm Technology Corporation Three dimensional structure integrated circuits
US5835429A (en) * 1997-05-09 1998-11-10 Lsi Logic Corporation Data retention weak write circuit and method of using same
JPH11260924A (ja) * 1998-03-10 1999-09-24 Mitsubishi Electric Corp 半導体集積回路装置のテスト方法
ITMI981564A1 (it) * 1998-07-09 2000-01-09 St Microelectronics Srl Memoria non volatile in grado di eseguire un programma autonomamente
US6141272A (en) * 1999-09-02 2000-10-31 Micron Technology, Inc. Method and apparatus for programmable control signal generation for a semiconductor device
JP2001283598A (ja) * 2000-03-29 2001-10-12 Nec Kansai Ltd Ｓｒａｍペレットにおける冗長回路切り替えのための検査方法
US6208572B1 (en) * 2000-06-12 2001-03-27 International Business Machines Corporation Semiconductor memory device having resistive bitline contact testing
US6549483B2 (en) * 2001-03-30 2003-04-15 Atmos Corporation RAM having dynamically switchable access modes
US6681350B2 (en) * 2001-05-05 2004-01-20 Cadence Design Systems, Inc. Method and apparatus for testing memory cells for data retention faults
US7053647B2 (en) * 2004-05-07 2006-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Method of detecting potential bridging effects between conducting lines in an integrated circuit
US7216270B1 (en) 2004-05-14 2007-05-08 National Semiconductor Corporation System and method for providing testing and failure analysis of integrated circuit memory devices
DE102004040750B4 (de) * 2004-08-23 2008-03-27 Qimonda Ag Speicherzellenanordnung mit Speicherzellen vom CBRAM-Typ und Verfahren zum Programmieren derselben
US7855924B2 (en) * 2006-05-19 2010-12-21 Arm Limited Data processing memory circuit having pull-down circuit with on/off configuration
US20080198674A1 (en) * 2007-02-21 2008-08-21 Jan Keller Method of testing an integrated circuit, method of determining defect resistivity changing cells, testing device, and computer program adapted to perform a method for testing an integrated circuit
KR20090002849A (ko) * 2007-07-04 2009-01-09 삼성전자주식회사 비트라인 누설 전류를 검출하는 메모리 장치
US8526252B2 (en) * 2009-03-17 2013-09-03 Seagate Technology Llc Quiescent testing of non-volatile memory array
US10437557B2 (en) * 2018-01-31 2019-10-08 Micron Technology, Inc. Determination of a match between data values stored by several arrays

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2812004B2 (ja) * 1991-06-27 1998-10-15 日本電気株式会社 スタティック型ランダムアクセスメモリ装置
KR940006676B1 (ko) * 1991-10-14 1994-07-25 삼성전자 주식회사 시험회로를 내장한 기억용 반도체 집적회로

Also Published As

Publication number Publication date
MY131610A (en) 2007-08-30
US5491665A (en) 1996-02-13
KR100339321B1 (ko) 2002-11-23
TW260788B (enExample) 1995-10-21
DE69429225D1 (de) 2002-01-10
JPH0785700A (ja) 1995-03-31
SG48339A1 (en) 1998-04-17
KR950009742A (ko) 1995-04-24
DE69429225T2 (de) 2002-08-14

Similar Documents

Publication Publication Date Title
JP3690827B2 (ja) メモリ装置付電子回路
KR101492667B1 (ko) 반도체 메모리 디바이스 테스트 방법, 반도체 메모리 디바이스 테스트 회로, 집적 회로 및 ａｔｅ 장치
US4757503A (en) Self-testing dynamic ram
US5638331A (en) Burn-in test circuit and method in semiconductor memory device
US6501692B1 (en) Circuit and method for stress testing a static random access memory (SRAM) device
US3995215A (en) Test technique for semiconductor memory array
EP0642134A2 (en) Test of a static random access memory
JPH05304266A (ja) スタティックランダムアクセスメモリアレイを試験する方法及び装置
KR100367191B1 (ko) 테스트수단을구비한전자회로및메모리셀테스트방법
JPH04216400A (ja) 半導体記憶装置およびその検査方法
JP2003272399A (ja) 半導体メモリの検査、欠陥救済方法、及び半導体メモリ
US6590818B1 (en) Method and apparatus for soft defect detection in a memory
US6167541A (en) Method for detecting or preparing intercell defects in more than one array of a memory device
US5432744A (en) Dynamic semiconductor memory circuit
US4800332A (en) Reconfigurable integrated circuit with enhanced testability of memory cell leakage
KR100796050B1 (ko) 반도체 메모리 장치 및 멀티플렉서 제어 방법
JP4782937B2 (ja) 半導体記憶装置
JP3267301B2 (ja) 検査回路を有する回路装置
KR950005578B1 (ko) 기억셀을 테스트하기 위한 회로 배열 및 그 방법
JP2000195300A (ja) フラッシュメモリ及びその試験方法
US5570317A (en) Memory circuit with stress circuitry for detecting defects
JP5587141B2 (ja) 半導体装置
EP0642137B1 (en) Quiescent-current testable RAM
CA1238124A (en) Stability testing of semiconductor memories
JPH0577178B2 (enExample)

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20040729

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20040831

A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20041129

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20041202

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20050228

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20050531

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20050614

R150 Certificate of patent or registration of utility model

Free format text: JAPANESE INTERMEDIATE CODE: R150

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20080624

Year of fee payment: 3

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090624

Year of fee payment: 4

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090624

Year of fee payment: 4

S111 Request for change of ownership or part of ownership

Free format text: JAPANESE INTERMEDIATE CODE: R313113

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20090624

Year of fee payment: 4

R350 Written notification of registration of transfer

Free format text: JAPANESE INTERMEDIATE CODE: R350

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20100624

Year of fee payment: 5

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110624

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20110624

Year of fee payment: 6

FPAY Renewal fee payment (event date is renewal date of database)

Free format text: PAYMENT UNTIL: 20120624

Year of fee payment: 7

LAPS Cancellation because of no payment of annual fees