JP3614993B2 - テスト回路 - Google Patents

テスト回路 Download PDF

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Publication number
JP3614993B2
JP3614993B2 JP23284596A JP23284596A JP3614993B2 JP 3614993 B2 JP3614993 B2 JP 3614993B2 JP 23284596 A JP23284596 A JP 23284596A JP 23284596 A JP23284596 A JP 23284596A JP 3614993 B2 JP3614993 B2 JP 3614993B2
Authority
JP
Japan
Prior art keywords
output
circuit
scan
test
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP23284596A
Other languages
English (en)
Japanese (ja)
Other versions
JPH1078475A5 (enExample
JPH1078475A (ja
Inventor
徳哉 大澤
秀史 前野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Renesas Technology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp filed Critical Renesas Technology Corp
Priority to JP23284596A priority Critical patent/JP3614993B2/ja
Priority to US08/788,838 priority patent/US5905737A/en
Publication of JPH1078475A publication Critical patent/JPH1078475A/ja
Publication of JPH1078475A5 publication Critical patent/JPH1078475A5/ja
Application granted granted Critical
Publication of JP3614993B2 publication Critical patent/JP3614993B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/30—Accessing single arrays
    • G11C29/32—Serial access; Scan testing

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
JP23284596A 1996-09-03 1996-09-03 テスト回路 Expired - Fee Related JP3614993B2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP23284596A JP3614993B2 (ja) 1996-09-03 1996-09-03 テスト回路
US08/788,838 US5905737A (en) 1996-09-03 1997-01-27 Test circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP23284596A JP3614993B2 (ja) 1996-09-03 1996-09-03 テスト回路

Publications (3)

Publication Number Publication Date
JPH1078475A JPH1078475A (ja) 1998-03-24
JPH1078475A5 JPH1078475A5 (enExample) 2004-09-09
JP3614993B2 true JP3614993B2 (ja) 2005-01-26

Family

ID=16945712

Family Applications (1)

Application Number Title Priority Date Filing Date
JP23284596A Expired - Fee Related JP3614993B2 (ja) 1996-09-03 1996-09-03 テスト回路

Country Status (2)

Country Link
US (1) US5905737A (enExample)
JP (1) JP3614993B2 (enExample)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH11153650A (ja) * 1997-11-20 1999-06-08 Mitsubishi Electric Corp 半導体集積回路装置
JPH11352188A (ja) * 1998-06-11 1999-12-24 Mitsubishi Electric Corp 半導体装置
DE19911939C2 (de) * 1999-03-17 2001-03-22 Siemens Ag Verfahren für den eingebauten Selbsttest einer elektronischen Schaltung
JP3459799B2 (ja) 1999-10-19 2003-10-27 Ｎｅｃエレクトロニクス株式会社 テスト回路およびテスト回路生成装置、テスト回路生成方法およびその記録媒体
US6272657B1 (en) * 1999-10-19 2001-08-07 Atmel Corporation Apparatus and method for progammable parametric toggle testing of digital CMOS pads
JP2001165999A (ja) * 1999-12-14 2001-06-22 Mitsubishi Electric Corp 半導体集積回路およびこれを用いた半導体集積回路装置
JP2003344500A (ja) * 2002-05-29 2003-12-03 Nec Electronics Corp マクロテスト回路
JP2004030829A (ja) 2002-06-27 2004-01-29 Oki Electric Ind Co Ltd 半導体記憶装置
US6990621B2 (en) * 2002-12-20 2006-01-24 Intel Corporation Enabling at speed application of test patterns associated with a wide tester interface on a low pin count tester
JP2006236551A (ja) * 2005-01-28 2006-09-07 Renesas Technology Corp テスト機能を有する半導体集積回路および製造方法
KR100675015B1 (ko) * 2006-02-24 2007-01-29 삼성전자주식회사 스캔 기능 및 컬럼 리던던시를 포함하는 내장형 메모리장치, 리던던시 리페어 및 스캔 방법
US7665003B2 (en) * 2006-12-15 2010-02-16 Qualcomm Incorporated Method and device for testing memory
JP2009180532A (ja) * 2008-01-29 2009-08-13 Renesas Technology Corp 標準セルおよび半導体装置
JP5911816B2 (ja) * 2013-02-26 2016-04-27 株式会社東芝 半導体集積回路装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4503537A (en) * 1982-11-08 1985-03-05 International Business Machines Corporation Parallel path self-testing system
US5155432A (en) * 1987-10-07 1992-10-13 Xilinx, Inc. System for scan testing of logic circuit networks
JPH01110274A (ja) * 1987-10-23 1989-04-26 Sony Corp 試験回路
EP0628831B1 (en) * 1988-09-07 1998-03-18 Texas Instruments Incorporated Bidirectional boundary scan test cell
JP2676169B2 (ja) * 1989-12-27 1997-11-12 三菱電機株式会社 スキャンパス回路
JPH03252569A (ja) * 1990-02-26 1991-11-11 Advanced Micro Devicds Inc スキャンパス用レジスタ回路
JP2741119B2 (ja) * 1991-09-17 1998-04-15 三菱電機株式会社 バイパススキャンパスおよびそれを用いた集積回路装置
US5471481A (en) * 1992-05-18 1995-11-28 Sony Corporation Testing method for electronic apparatus
JP2871291B2 (ja) * 1992-05-20 1999-03-17 日本電気株式会社 論理集積回路
JPH0690265A (ja) * 1992-09-08 1994-03-29 Fujitsu Ltd 準同期検波復調部
US5428622A (en) * 1993-03-05 1995-06-27 Cyrix Corporation Testing architecture with independent scan paths
KR0123751B1 (ko) * 1993-10-07 1997-11-25 김광호 반도체장치 및 그 제조방법
JP3325727B2 (ja) * 1994-05-26 2002-09-17 三菱電機株式会社 半導体メモリの検査装置
JP2561032B2 (ja) * 1994-06-14 1996-12-04 日本電気株式会社 半導体集積回路のテスト方式
US5592493A (en) * 1994-09-13 1997-01-07 Motorola Inc. Serial scan chain architecture for a data processing system and method of operation

Also Published As

Publication number Publication date
US5905737A (en) 1999-05-18
JPH1078475A (ja) 1998-03-24

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