JP3377375B2 - 自己整合メタラジ - Google Patents

自己整合メタラジ

Info

Publication number
JP3377375B2
JP3377375B2 JP21484996A JP21484996A JP3377375B2 JP 3377375 B2 JP3377375 B2 JP 3377375B2 JP 21484996 A JP21484996 A JP 21484996A JP 21484996 A JP21484996 A JP 21484996A JP 3377375 B2 JP3377375 B2 JP 3377375B2
Authority
JP
Japan
Prior art keywords
contact hole
undesired
sublithographic
image
sacrificial material
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP21484996A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09129733A (ja
Inventor
ジョン・エドワード・クローニン
カーター・ウェリング・カーンタ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH09129733A publication Critical patent/JPH09129733A/ja
Application granted granted Critical
Publication of JP3377375B2 publication Critical patent/JP3377375B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Electrodes Of Semiconductors (AREA)
JP21484996A 1995-08-22 1996-08-14 自己整合メタラジ Expired - Fee Related JP3377375B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/517,782 US5759911A (en) 1995-08-22 1995-08-22 Self-aligned metallurgy
US08/517782 1995-08-22

Publications (2)

Publication Number Publication Date
JPH09129733A JPH09129733A (ja) 1997-05-16
JP3377375B2 true JP3377375B2 (ja) 2003-02-17

Family

ID=24061208

Family Applications (1)

Application Number Title Priority Date Filing Date
JP21484996A Expired - Fee Related JP3377375B2 (ja) 1995-08-22 1996-08-14 自己整合メタラジ

Country Status (4)

Country Link
US (2) US5759911A (enExample)
JP (1) JP3377375B2 (enExample)
KR (1) KR100201035B1 (enExample)
TW (1) TW307039B (enExample)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2934353B2 (ja) * 1992-06-24 1999-08-16 三菱電機株式会社 半導体装置およびその製造方法
US5846876A (en) * 1996-06-05 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit which uses a damascene process for producing staggered interconnect lines
EP0912996B1 (en) * 1996-07-18 2002-01-02 Advanced Micro Devices, Inc. Integrated circuit which uses an etch stop for producing staggered interconnect lines
US5854515A (en) * 1996-07-23 1998-12-29 Advanced Micro Devices, Inc. Integrated circuit having conductors of enhanced cross-sectional area
US5847462A (en) * 1996-11-14 1998-12-08 Advanced Micro Devices, Inc. Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
JP3856544B2 (ja) * 1997-10-29 2006-12-13 株式会社ルネサステクノロジ 半導体装置及びその製造方法
US6057239A (en) * 1997-12-17 2000-05-02 Advanced Micro Devices, Inc. Dual damascene process using sacrificial spin-on materials
US6051369A (en) * 1998-01-08 2000-04-18 Kabushiki Kaisha Toshiba Lithography process using one or more anti-reflective coating films and fabrication process using the lithography process
US6027994A (en) * 1998-06-22 2000-02-22 United Microelectronics Corp. Method to fabricate a dual metal-damascene structure in a substrate
US6025259A (en) * 1998-07-02 2000-02-15 Advanced Micro Devices, Inc. Dual damascene process using high selectivity boundary layers
US6127263A (en) 1998-07-10 2000-10-03 Applied Materials, Inc. Misalignment tolerant techniques for dual damascene fabrication
TW437040B (en) 1998-08-12 2001-05-28 Applied Materials Inc Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics
US6225207B1 (en) * 1998-10-01 2001-05-01 Applied Materials, Inc. Techniques for triple and quadruple damascene fabrication
US6200906B1 (en) * 1998-12-17 2001-03-13 Micron Technology, Inc. Stepped photoresist profile and opening formed using the profile
US20030089987A1 (en) * 1999-02-05 2003-05-15 Suketu A. Parikh Dual damascene misalignment tolerant techniques for vias and sacrificial etch segments
US6265301B1 (en) * 1999-05-12 2001-07-24 Taiwan Semiconductor Manufacturing Company Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures
US6734110B1 (en) * 1999-10-14 2004-05-11 Taiwan Semiconductor Manufacturing Company Damascene method employing composite etch stop layer
JP2001185613A (ja) * 1999-12-24 2001-07-06 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6596591B1 (en) * 2000-12-18 2003-07-22 Advanced Micro Devices, Inc. Methods to form reduced dimension bit-line isolation in the manufacture of non-volatile memory devices
US6650000B2 (en) 2001-01-16 2003-11-18 International Business Machines Corporation Apparatus and method for forming a battery in an integrated circuit
US6380077B1 (en) * 2001-04-13 2002-04-30 United Microelectronics Corp. Method of forming contact opening
US6777260B1 (en) * 2003-08-14 2004-08-17 Silicon Storage Technology, Inc. Method of making sub-lithographic sized contact holes
JP4476171B2 (ja) * 2005-05-30 2010-06-09 富士通マイクロエレクトロニクス株式会社 半導体装置の製造方法
US7651942B2 (en) * 2005-08-15 2010-01-26 Infineon Technologies Ag Metal interconnect structure and method
KR100952483B1 (ko) * 2008-02-18 2010-04-13 삼성전기주식회사 인쇄회로기판 및 그 제조방법
US20100007028A1 (en) * 2008-07-11 2010-01-14 Infineon Technologies Austria Ag Device including an imide layer with non-contact openings and method
US8304916B1 (en) 2011-07-06 2012-11-06 Northrop Grumman Systems Corporation Half-through vias for suppression of substrate modes
US8883638B2 (en) * 2012-01-18 2014-11-11 United Microelectronics Corp. Method for manufacturing damascene structure involving dummy via holes
US11195792B2 (en) * 2020-01-10 2021-12-07 International Business Machines Corporation Top via stack
CN113488392B (zh) * 2021-07-13 2022-08-02 武汉新芯集成电路制造有限公司 集成电路器件制造方法

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3600169A1 (de) * 1985-01-07 1986-07-10 Canon K.K., Tokio/Tokyo Maskenstruktur zur lithographie, verfahren zu ihrer herstellung und lithographisches verfahren
US4789648A (en) * 1985-10-28 1988-12-06 International Business Machines Corporation Method for producing coplanar multi-level metal/insulator films on a substrate and for forming patterned conductive lines simultaneously with stud vias
US4921723A (en) * 1987-10-16 1990-05-01 The Curators Of The University Of Missouri Process for applying a composite insulative coating to a substrate
US5106780A (en) * 1988-08-05 1992-04-21 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US4987101A (en) * 1988-12-16 1991-01-22 International Business Machines Corporation Method for providing improved insulation in VLSI and ULSI circuits
KR920005453B1 (ko) * 1989-05-13 1992-07-04 현대전자산업 주식회사 반도체 접속장치 형성방법
US5118382A (en) * 1990-08-10 1992-06-02 Ibm Corporation Elimination of etch stop undercut
US5100838A (en) * 1990-10-04 1992-03-31 Micron Technology, Inc. Method for forming self-aligned conducting pillars in an (IC) fabrication process
US5286674A (en) * 1992-03-02 1994-02-15 Motorola, Inc. Method for forming a via structure and semiconductor device having the same
JP3271094B2 (ja) * 1993-07-05 2002-04-02 ソニー株式会社 積層配線基板及びその製造方法
KR950025908A (ko) * 1994-02-03 1995-09-18 김주용 반도체소자 제조방법
US5710460A (en) * 1995-04-21 1998-01-20 International Business Machines Corporation Structure for reducing microelectronic short circuits using spin-on glass as part of the interlayer dielectric
US5525552A (en) * 1995-06-08 1996-06-11 Taiwan Semiconductor Manufacturing Company Method for fabricating a MOSFET device with a buried contact
US5539255A (en) * 1995-09-07 1996-07-23 International Business Machines Corporation Semiconductor structure having self-aligned interconnection metallization formed from a single layer of metal

Also Published As

Publication number Publication date
KR100201035B1 (ko) 1999-06-15
US5759911A (en) 1998-06-02
KR970013084A (ko) 1997-03-29
JPH09129733A (ja) 1997-05-16
US5976963A (en) 1999-11-02
TW307039B (enExample) 1997-06-01

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