JP3151829B2 - デジタル位相ロック・ループ - Google Patents

デジタル位相ロック・ループ

Info

Publication number
JP3151829B2
JP3151829B2 JP50313296A JP50313296A JP3151829B2 JP 3151829 B2 JP3151829 B2 JP 3151829B2 JP 50313296 A JP50313296 A JP 50313296A JP 50313296 A JP50313296 A JP 50313296A JP 3151829 B2 JP3151829 B2 JP 3151829B2
Authority
JP
Japan
Prior art keywords
output
input
coupled
input coupled
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP50313296A
Other languages
English (en)
Japanese (ja)
Other versions
JPH09502594A (ja
Inventor
キリアン,マーベリック・マーティン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Publication of JPH09502594A publication Critical patent/JPH09502594A/ja
Application granted granted Critical
Publication of JP3151829B2 publication Critical patent/JP3151829B2/ja
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/099Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • H03L7/085Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Manipulation Of Pulses (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
JP50313296A 1994-06-30 1995-05-15 デジタル位相ロック・ループ Expired - Fee Related JP3151829B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US269,245 1994-06-30
US08/269,245 1994-06-30
US08/269,245 US5502751A (en) 1994-06-30 1994-06-30 Digital phase locked loop

Publications (2)

Publication Number Publication Date
JPH09502594A JPH09502594A (ja) 1997-03-11
JP3151829B2 true JP3151829B2 (ja) 2001-04-03

Family

ID=23026436

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50313296A Expired - Fee Related JP3151829B2 (ja) 1994-06-30 1995-05-15 デジタル位相ロック・ループ

Country Status (7)

Country Link
US (1) US5502751A (sv)
JP (1) JP3151829B2 (sv)
KR (1) KR100222360B1 (sv)
CN (1) CN1059523C (sv)
GB (1) GB2296397B (sv)
SE (1) SE518155C2 (sv)
WO (1) WO1996001005A1 (sv)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7697027B2 (en) 2001-07-31 2010-04-13 Donnelly Corporation Vehicular video system
KR102566909B1 (ko) * 2021-12-08 2023-08-16 주식회사 셀코스 자외선 경화 장치

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6076096A (en) * 1998-01-13 2000-06-13 Motorola Inc. Binary rate multiplier
US6415008B1 (en) 1998-12-15 2002-07-02 BéCHADE ROLAND ALBERT Digital signal multiplier
KR100432422B1 (ko) * 1998-12-18 2004-09-10 서창전기통신 주식회사 단일위상동기루프구조를갖는무선주파수송수신모듈제어방법
US6609781B2 (en) 2000-12-13 2003-08-26 Lexmark International, Inc. Printer system with encoder filtering arrangement and method for high frequency error reduction
CN102360191B (zh) * 2011-08-30 2013-07-03 北京交通大学 滚轮式双轴光电编码器数据处理仪

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0176993B1 (en) * 1984-09-28 1990-03-14 Kabushiki Kaisha Toshiba Reference signal reproduction apparatus
US4964117A (en) * 1988-10-04 1990-10-16 Vtc Incorporated Timing synchronizing circuit for baseband data signals
JPH02124637A (ja) * 1988-11-02 1990-05-11 Nec Corp 同期検出回路
US5278874A (en) * 1992-09-02 1994-01-11 Motorola, Inc. Phase lock loop frequency correction circuit

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7697027B2 (en) 2001-07-31 2010-04-13 Donnelly Corporation Vehicular video system
US8405725B2 (en) 2001-07-31 2013-03-26 Donnelly Corporation Vehicular video processor module
US9191574B2 (en) 2001-07-31 2015-11-17 Magna Electronics Inc. Vehicular vision system
US9376060B2 (en) 2001-07-31 2016-06-28 Magna Electronics Inc. Driver assist system for vehicle
US9656608B2 (en) 2001-07-31 2017-05-23 Magna Electronics Inc. Driver assist system for vehicle
US9834142B2 (en) 2001-07-31 2017-12-05 Magna Electronics Inc. Driving assist system for vehicle
US10046702B2 (en) 2001-07-31 2018-08-14 Magna Electronics Inc. Control system for vehicle
KR102566909B1 (ko) * 2021-12-08 2023-08-16 주식회사 셀코스 자외선 경화 장치

Also Published As

Publication number Publication date
JPH09502594A (ja) 1997-03-11
KR100222360B1 (ko) 1999-10-01
KR960705397A (ko) 1996-10-09
SE9600726L (sv) 1996-04-30
SE9600726D0 (sv) 1996-02-27
CN1130000A (zh) 1996-08-28
US5502751A (en) 1996-03-26
GB2296397B (en) 1999-01-06
SE518155C2 (sv) 2002-09-03
GB9603602D0 (en) 1996-04-17
GB2296397A (en) 1996-06-26
CN1059523C (zh) 2000-12-13
WO1996001005A1 (en) 1996-01-11

Similar Documents

Publication Publication Date Title
US6577174B2 (en) Phase lock loop system and method
US6285219B1 (en) Dual mode phase and frequency detector
JP3151829B2 (ja) デジタル位相ロック・ループ
JPH0292021A (ja) ディジタルpll回路
EP1257059B1 (en) Method and apparatus for synchronizing slave network node to master network node
US6757349B1 (en) PLL frequency synthesizer with lock detection circuit
JPH11220385A (ja) クロック信号生成回路及びデータ信号生成回路
JP2917522B2 (ja) クロック同期方法および回路
JP2996205B2 (ja) Pdh低速信号切替式dpll
US5572554A (en) Synchronizer and method therefor
JP2964916B2 (ja) ディジタル位相同期回路及びこれを用いたデータ受信回路
JP2651688B2 (ja) ディジタルpll回路
JPS61140221A (ja) タイミング発生回路
GB2240241A (en) Data transmission systems
JP3005549B1 (ja) Pll回路及びそのpll同期方法
JPH11313049A (ja) 自営用phs(登録商標)親機システムにおけるisdn網とのクロック同期補正方法および回路
JP3033543B2 (ja) フレーム同期回路
JP3808424B2 (ja) Pll回路および位相同期方法
JP2798918B2 (ja) パルス幅変調回路
JP3729041B2 (ja) クロック補正回路
JPH0983354A (ja) Dpll回路
KR20010008836A (ko) 이동통신시스템의 위상비교기를 이용한 클럭 동기장치
JPH06140928A (ja) ドリフト検出回路
KR100247006B1 (ko) 영위상에러 빌딩된 디지털프로세서 위상동기루프
JPH07114397B2 (ja) 位相同期回路

Legal Events

Date Code Title Description
R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

LAPS Cancellation because of no payment of annual fees