JP2570499B2 - フリップチップ集積回路の背面接地 - Google Patents
フリップチップ集積回路の背面接地Info
- Publication number
- JP2570499B2 JP2570499B2 JP5513402A JP51340293A JP2570499B2 JP 2570499 B2 JP2570499 B2 JP 2570499B2 JP 5513402 A JP5513402 A JP 5513402A JP 51340293 A JP51340293 A JP 51340293A JP 2570499 B2 JP2570499 B2 JP 2570499B2
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- semiconductor device
- flip chip
- metallization pattern
- chip carrier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000000758 substrate Substances 0.000 claims description 51
- 238000001465 metallisation Methods 0.000 claims description 18
- 239000004065 semiconductor Substances 0.000 claims description 17
- 239000000945 filler Substances 0.000 claims description 14
- 229910052751 metal Inorganic materials 0.000 claims description 14
- 239000002184 metal Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 8
- 239000004020 conductor Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 229920000642 polymer Polymers 0.000 claims description 4
- ISWSIDIOOBJBQZ-UHFFFAOYSA-N Phenol Chemical compound OC1=CC=CC=C1 ISWSIDIOOBJBQZ-UHFFFAOYSA-N 0.000 claims description 3
- 229920002313 fluoropolymer Polymers 0.000 claims description 3
- 239000004811 fluoropolymer Substances 0.000 claims description 3
- 229920001721 polyimide Polymers 0.000 claims description 3
- 239000009719 polyimide resin Substances 0.000 claims description 3
- -1 CEM Substances 0.000 claims 1
- 239000000919 ceramic Substances 0.000 claims 1
- 229910000679 solder Inorganic materials 0.000 description 8
- 238000000034 method Methods 0.000 description 7
- 239000004593 Epoxy Substances 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- JOYRKODLDBILNP-UHFFFAOYSA-N Ethyl urethane Chemical compound CCOC(N)=O JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 2
- 238000011049 filling Methods 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 239000002861 polymer material Substances 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910000831 Steel Inorganic materials 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 229910010293 ceramic material Inorganic materials 0.000 description 1
- 238000003486 chemical etching Methods 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 238000009713 electroplating Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 125000003700 epoxy group Chemical group 0.000 description 1
- 229920000126 latex Polymers 0.000 description 1
- 239000004816 latex Substances 0.000 description 1
- 230000013011 mating Effects 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920003223 poly(pyromellitimide-1,4-diphenyl ether) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000728 polyester Polymers 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 239000000565 sealant Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910001220 stainless steel Inorganic materials 0.000 description 1
- 239000010935 stainless steel Substances 0.000 description 1
- 239000010959 steel Substances 0.000 description 1
- 238000001029 thermal curing Methods 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/145—Organic substrates, e.g. plastic
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
- H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
- H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
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- H—ELECTRICITY
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- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
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- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01014—Silicon [Si]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01057—Lanthanum [La]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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- H01L2924/01087—Francium [Fr]
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Dispersion Chemistry (AREA)
- Wire Bonding (AREA)
Description
し、特に、フリップチップ半導体デバイスに関する。
器、例えばチップキャリアやデュアルインラインパッケ
ージ(DIP)にパッケージされ、プリント回路基板上で
他の部品と相互接続される。集積回路は、集積回路の能
動または上部表面がキャリア基板に対して反対を向いた
状態で、キャリア基板に接続される。ICと基板との相互
接続は典型的に、ICのパッドとプリント回路基板上の回
路とを溶接する細い金属線やワイヤボンドによって行わ
れる。
集積回路がハンダバンプや他の金属相互接続の手段によ
って、直接基板に接着されるものであり、それは能動面
がプリント回路基板に面した状態でマウントされる。こ
のタイプの相互接続は、費用を削減し、信頼性を向上さ
せ、手作業や自動ワイヤボンディングによる低生産性を
除去する。さらにこの方法はワイヤボンディング方法の
場合おける周辺接続の使用の制限がなく、内部接続やア
レイ接続にも使用できる。フリップチップやコントロー
ル・コラプス・チップ接続(control−collapse−chip
−connection)(C4)は、ぬれ性を有する金属端子上に
置かれたハンダバンプと、その対の基板上のぬれ性を有
するハンダ金属端子のフットプリントを利用する。上下
を逆さまにしたフリップチップを基板に整列させて、全
ての内部接続がハンダリフローによって同時に作られ
る。これはチップの能動面が上を向き、基板にワイヤボ
ンドされる従来のボンディング方法とは正反対である。
ワイヤボンドされると、チップの背面接地面への接地接
続は、チップの背面接地面とプリント回路基板の接地と
の間に導電性接続を形成することによって行うことがで
きる。これは、例えば導電性エポキシやハンダ手段によ
って容易に成し遂げることができる。フリップチップデ
バイスでは、接地面が基板から離れているので、ICの接
地面基板の接地への接続は比較的に困難である。ワイヤ
ボンドによってICの接地と基板の接地との間を形成する
こはできるが、これはフリップチップマウンティング設
計によって実現される利益を損なう。
を達成する方法において、煩わしくなく、コストがかか
らず、信頼性のないワイヤボンドを使用しない方法が必
要である。
に金属被膜パターンを有する基板、および能動面とその
反対の面に接地面を有する半導体デバイスから構成され
る半導体デバイスパッケージが提供される。半導体デバ
イスは基板に面した能動面で基板の金属被膜パターンに
電気的に接続される。ポリマー充填材は、半導体デバイ
スと基板との空間を実質的に充填する。電気的導電性材
料は半導体デバイスの露出した接地面と、金属被膜パタ
ーンの少なくとも一部を覆い、半導体の接地面と基板上
の金属被膜パターンとの電気的接続を提供する。
がパッドグリッドアレイチップキャリア(pad grid arr
ay chip carrier)の場合である。チップキャリアは、
少なくとも1つの表面上に金属被膜パターンと、フリッ
プチップとを有するプリント回路基板から構成される。
フリップチップは一方の面に能動面を、第2の反対の面
には接地面を有する。フリップチップは能動面がプリン
ト回路基板に面するように金属被膜パターンに電気的に
接続される。充填材はフリップチップと基板の金属被膜
パターンとの空間を実質的に充填し、金属の被膜はフリ
ップチップの接地面と金属被膜パターンのすくなくとも
一部とを電気的に接続する。
ントされたフリップチップの横断面図を表す。
してあるが、集積回路10は一方の面に能動面12を有し、
他の面に接地面14を有する。能動面12には集積回路に存
在する通常の回路の全て、例えば、トランジスタ、抵
抗、アレイ、入出力パッドおよびパッシベーションがあ
る。接地面14は典形的に一連の金属面であるがパターン
を有することもある。集積回路またはフリップチップ10
の能動面12上の入出力パッド16は、ハンダバンプ18をパ
ットに付着することにより金属被膜化される。パッドの
金属被膜化は、金球をボンディングしたり、他の金属を
メッキ又は沈積させることで成し遂げることもできる。
パッドおよびハンダバンプ18に対応して金属被膜パター
ンまたは導電パターン22を有する。さらに、基板20も接
地平面、1つのランナまたは複数のランナからなる接地
接続26を有する。基板は、FR−4、強化ポリイミド樹
脂、強化ポリエステル、フルオロポリマ、CEM、紙フェ
ノール、KAPTON(商標)、あるいはセラミック材料のよ
うな、硬質またはフレキシブルプリント回路基板材であ
る。好適実施例では基板20はプリント回路基板材料であ
り、チップキャリアを形成するように、集積回路とほぼ
同一あるいはやや大きめのサイズである。チップキャリ
アは典型的にリードレスであり、キャリア基板の下面の
配列上に配置された複数のハンダ付け可能な接点を有す
る周辺型(perimeter type)のキャリアまたはパッドグ
リッドアレイチップである。またはピンが基板上に配置
されることもある。他の実施例ではキャリア基板20はず
っと大きくして、たとえば通常プリント回路基板上にあ
るような抵抗、コンデンサ、スイッチなどの他の部品を
有してもよい。
ような状態で、基板20に接続される。IC10と基板20との
相互接続は、ハンダバンプ18を基板のパッド22と整合さ
せ、リフローさせることによって接続される。
組立体は封止材30で下面充填される。液体ポリマー、典
型的にエポキシ、ウレタン、アクリルがフリップチップ
と基板との間に形成された隙間に加えられる。封止材30
は、IC10の周囲に加えられるか、または基板にあるホー
ル24と通して基板の背面から加えることができる。充填
材の例としては、米国特許第4、999、6999号に見い出
すことができる。充填ポリマー材30はフリップチップIC
の能動面12の外界からの保護に役立ち、かつフリップチ
ップの基板への接着を機械的に助ける。充填材30はフリ
ップチップと基板との間の空間を充填し、またフリップ
チップの周囲を越えて一定の距離まで延在する。表面張
力および界面活性要素が、へこみすみ肉(concave fill
et)28をフリップチップの周囲に形成させる。液体ポリ
マー材30はその後、熱的硬化をさせるためにオーブンの
中に移すような適切な手段によって、または2種の材料
の場合には室温によって、紫外線によって、放射線によ
って、あるいは高周波エネルギーによって硬化される。
続するために、導電性材料の一連のフィルムまたは被膜
がフィルップチップおよび基板上に加えられる。導電性
材料35の被膜が加えられ、フリップチップIC、充填材の
へこみすみ肉、基板20の一部および基板の接地接続26を
覆う。このようにして基板接地26とICの背面接地14とが
接続される。導電被膜35は、要求されるパッケージに応
じて様々の形態がある。例えば、パッドアレイチップキ
ャリアが組み立てられる場合は、導電被膜35は銅、アル
ミニューム、チタン、クロムまたはニッケルのようなス
パッタ金属フィルムである。スパッタフィルム35は、導
電性を向上させ剥離に対する機械的抵抗を強めるため
に、銅などの金属を無電解メッキまたは電解メッキする
方法によって付加的にメッキされる。もしフリップチッ
プIC10が付加的な部品を有する回路ボードやマザーボー
ドのような大きな組立部品の一部分である場合は、導電
被膜35はIC上やICまたは基板上に施されたスクリーン印
刷の導電エポキシによって電気的に形成される。導電ポ
リマーの例としては金属入りエポキシ、銅、ニッケル、
銀、金、鋼、ステンレス鋼、他の金属を含有するウレタ
ンである。
際、充填材がフリップチップを越えて基板上の接地接続
26を覆うまで延在させないことは大変重要である。これ
を防ぐ簡易な方法として、充填材の拡がりを防ぐために
接地ピンの領域に肉寄せ材を加えることである。集積回
路を封入する場合に肉寄せ材または障壁を使用すること
は、米国特許第4、843、036号で開示されており、参考
まで本明細書に組み入れられる。同一の技術は充填材を
加えるときにも使用される。さらに、接地26も充填材30
が接地を覆うことを防ぐために、フォトレジストまたは
ラテックスマスクのような一時的にマスキングで覆って
もよい。充填材は後に機械的剥離によって、科学的エッ
チングによって、またはレーザービームによって除去さ
れる。いずれにしても基板10上の接地接続26は汚染され
ることなく導電材35によって背面接地14に有効に接続さ
れなければならない。
との簡単で丈夫な接続を、容易かつ経済的に作ることが
できる。このような接続は、ワイヤボンディングの必要
性をなくし、さらに環境損傷から能動面および集積回路
を保護するパッケージを提供する。これらの例は説明の
方法に沿って紹介してきたが、その方法に制限されるも
のではなく、本発明は添付の請求の範囲以外により限定
されるものではない。
Claims (7)
- 【請求項1】半導体デバイスパッケージであって、 少なくとも第1表面上に金属被膜パターンを有する基
板; 第1面上に能動面および反対の第2面上に接地面を有す
る半導体デバイスであって、前記半導体デバイスは前記
基板の金属被膜パターンに対し、その能動面が前記基板
第1表面と向かい合うようにして、電気的に接続される
半導体デバイス; 前記半導体デバイスと前記基板金属被膜パターンとの間
の空間を実質的に充填するポリマー充填材;および 前記金属被膜パターンの少なくとも一部で前記半導体デ
バイスの接地面を覆う電気的導電材であって、前記接地
面と前記金属被膜パターンの一部とを電気的に接続する
電気的導電材; から構成される半導体デバイスパッケージ。 - 【請求項2】前記電気的導電材が前記ポリマー充填材の
一部分および前記基板の一部分を覆う請求項1記載の半
導体デバイスパッケージ。 - 【請求項3】前記基板がセラミック、フレキシブルフィ
ルム、またはFR−4、ポリイミド樹脂、CEM、紙フェノ
ールまたはフルオロポリマーから選択されるプリント回
路基板材料である請求項1記載の半導体デバイスパッケ
ージ。 - 【請求項4】パッドグリッドアレイチップキャリアであ
って、 少なくとも第1面上に金属被膜パターンを有するプリン
ト回路基板; 第1面上に能動面および反対の第2面上に接地面を有す
るフリップチップであって、前記フリップチップは前記
プリント回路基板の第1面に面する前記能動面において
前記金属被膜パターンに電気的に接続されるフリップチ
ップ; 前記フリップチップと前記基板金属被膜パターンとの間
の空間を実質的に充填する充填材;および 前記金属被膜パターンの少なくとも一部分で前記フリッ
プチップの接地面を電気的に接続する金属被膜; から構成されるパッドグリッドアレイチップキャリア - 【請求項5】前記金属被膜が前記充填材の一部分、およ
び前記プリント回路基板の一部分も覆う請求項4記載の
パッドグリッドアレイチップキャリア。 - 【請求項6】前記基板がFR−4、ポリイミド樹脂、CE
M、紙フェノールまたはフルオロポリマーから選択され
るプリント回路基板である請求項4記載のパッドグリッ
ドアレイチップキャリア。 - 【請求項7】前記基板が前記フリップチップと実質的に
同一サイズであり、チップキャリアを形成する請求項4
記載のパッドグリッドアレイチップキャリア。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US825,367 | 1992-01-24 | ||
US07/825,367 US5311059A (en) | 1992-01-24 | 1992-01-24 | Backplane grounding for flip-chip integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH07503579A JPH07503579A (ja) | 1995-04-13 |
JP2570499B2 true JP2570499B2 (ja) | 1997-01-08 |
Family
ID=25243838
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP5513402A Expired - Lifetime JP2570499B2 (ja) | 1992-01-24 | 1993-01-19 | フリップチップ集積回路の背面接地 |
Country Status (5)
Country | Link |
---|---|
US (1) | US5311059A (ja) |
EP (1) | EP0623242A4 (ja) |
JP (1) | JP2570499B2 (ja) |
KR (1) | KR0138966B1 (ja) |
WO (1) | WO1993015521A1 (ja) |
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GB1213726A (en) * | 1968-01-26 | 1970-11-25 | Ferranti Ltd | Improvements relating to electrical circuit assemblies |
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US3858455A (en) * | 1973-08-27 | 1975-01-07 | Clark Equipment Co | Transmissions |
JPS61276240A (ja) * | 1985-05-30 | 1986-12-06 | Mitsubishi Electric Corp | 混成集積回路 |
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JPH0294535A (ja) * | 1988-09-30 | 1990-04-05 | Nec Corp | 混成集積回路 |
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JPH03179796A (ja) * | 1989-12-07 | 1991-08-05 | Matsushita Electric Ind Co Ltd | ハイブリッド集積回路 |
US4999699A (en) * | 1990-03-14 | 1991-03-12 | International Business Machines Corporation | Solder interconnection structure and process for making |
US5121190A (en) * | 1990-03-14 | 1992-06-09 | International Business Machines Corp. | Solder interconnection structure on organic substrates |
-
1992
- 1992-01-24 US US07/825,367 patent/US5311059A/en not_active Expired - Lifetime
-
1993
- 1993-01-19 JP JP5513402A patent/JP2570499B2/ja not_active Expired - Lifetime
- 1993-01-19 WO PCT/US1993/000720 patent/WO1993015521A1/en not_active Application Discontinuation
- 1993-01-19 EP EP93904663A patent/EP0623242A4/en not_active Withdrawn
-
1994
- 1994-07-20 KR KR94702488A patent/KR0138966B1/ko active
Also Published As
Publication number | Publication date |
---|---|
KR0138966B1 (en) | 1998-04-30 |
JPH07503579A (ja) | 1995-04-13 |
US5311059A (en) | 1994-05-10 |
EP0623242A1 (en) | 1994-11-09 |
EP0623242A4 (en) | 1995-05-03 |
WO1993015521A1 (en) | 1993-08-05 |
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