JPH0294535A - 混成集積回路 - Google Patents

混成集積回路

Info

Publication number
JPH0294535A
JPH0294535A JP63246515A JP24651588A JPH0294535A JP H0294535 A JPH0294535 A JP H0294535A JP 63246515 A JP63246515 A JP 63246515A JP 24651588 A JP24651588 A JP 24651588A JP H0294535 A JPH0294535 A JP H0294535A
Authority
JP
Japan
Prior art keywords
pellet
circuit board
board
solder bumps
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63246515A
Other languages
English (en)
Inventor
Nobuo Fukuda
福田　信夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63246515A priority Critical patent/JPH0294535A/ja
Publication of JPH0294535A publication Critical patent/JPH0294535A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405—Shape
    • H01L2224/24051—Conformal with the semiconductor or solid-state device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/24225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/24226—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2499—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids
    • H01L2224/24996—Auxiliary members for HDI interconnects, e.g. spacers, alignment aids being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/24998—Reinforcing structures, e.g. ramp-like support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73259—Bump and HDI connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/82007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting a build-up interconnect during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/82—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • H01L2224/821—Forming a build-up interconnect
    • H01L2224/82101—Forming a build-up interconnect by additive methods, e.g. direct writing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92124—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a build-up interconnect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H05K1/095—Dispersed materials, e.g. conductive pastes or inks for polymer thick films, i.e. having a permanent organic polymeric binder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体素子や受動素子を搭載接続してなる混成
集積回路に関し、特に実装密度の向上を図った混成集積
回路に関する。
〔従来の技術］ 従来、この種の混成集積回路は所要の薄膜多層回路を形
成した回路基板上に、半導体ペレットの裏面を各種ペー
ストや半田等を用いてボンディングし、その上で半導体
ペレットの電極パッドと回路基板とをワイヤで電気接続
している。この場合、半導体ペレットのサブストレート
を所定の電位にする場合には、導電性のペーストを用い
てボンディングを行って回路基板に電気接続させ、フロ
ーティング状態とする場合には絶縁性のペーストを用い
てボンディングを行っている。
〔発明が解決しようとする課題〕
上述した従来の混成集積回路は、半導体ペレットの電極
パッドと回路基板の電気接続をワイヤで行っているため
、回路基板側にはワイヤをボンディングするための端子
が必要となる。したがって、これらの端子を配設する領
域を回路基板に確保することが要求され、実装密度の向
上を図る上での障害になるとともに、混成集積回路全体
の寸法が大きくなり、電子機器の低価格化、小形化、薄
形化の要求に充分に対応できないという問題がある。
本発明は実装密度を向上して上述した問題を解消するこ
とを可能とした混成集積回路を提供することを目的とす
る。
〔課題を解決するための手段〕
本発明の混成集積回路は、半田バンプを設けた半導体ベ
レットを回路基板上に搭載し、半田バンプを接続して回
路基板に電気接続するとともに、この半田バンプを絶縁
性樹脂により被覆し、かつ半導体ベレットの裏面と回路
基板とを導電性樹脂等により電気的に接続している。
〔作用〕
上述した構成では、半導体ベレットと回路基板とを接続
するワイヤを不要にして実装密度を向上でき、かつ半導
体ベレットの封止性を高めるとともに、サブストレート
の電気接続を可能とする。
［実施例〕 次に、本発明を図面を参照して説明する。
第１図は本発明の第１実施例の断面図である。
図において、回路基板１はセラミック基板２の表面に薄
膜多層回路３を形成し、所要の回路パターンを構成して
いる。
この薄膜多層回路３は、第２図にその一部を拡大図示す
るように、セラミック基板２の表面に、薄膜導体１１を
スパッタ法で成膜し、公知のフォトレジスト技術を用い
て導体回路を形成する。そして、この上に感光性ポリイ
ミド１２をスピンオン法で塗布し、ブリベータ後に露光
、現像を行い層間接続用スルーホール１３やその他の不
用部のポリイミドを除去する。なお、３５０″Ｃ，１時
間の条件でポリイミドの硬化を行う。これを複数回繰り
返すことで、薄膜多層回路３が形成される。
そして、第１図のように、この回路基板１の所要箇所に
は、半導体ベレット４を、その表面を下側に向けて搭載
する。この半導体ベレット４は、電極パッドに半田をメ
ツキすることにより半田バンプ５を形成し、この半田バ
ンプ５を前記薄膜多層回路３の所要箇所に接触させ、加
熱溶融することで接続を行っている。
更に、搭載、接続した半導体ベレット４の周囲に絶縁性
エポキシ樹脂６を塗布し、半導体ベレット４の裏面（上
面）を除く領域を被覆する。この樹脂の塗布に際しては
、デイスペンサーを用い、その後１５０“Ｃ，１２０分
で硬化する。このときエポキシ樹脂の粘度が低下し、エ
ポキシ樹脂は毛細管現象で半導体ベレット４と回路基板
１の間に浸透して半田バンプ５を被覆する。
また、半導体ベレット４の裏面からその一側部の回路基
板１上にわたって、例えばデイスペンサーで銀ペースト
７を塗布し、半導体ベレット４のサブストレートを回路
基板１に電気的に接続する。
この銀ペースト７は回路基板１上の受動素子の搭載電極
にも塗布しておき、後に各受動素子８を搭載する。
なお、図示は省略するが、外装樹脂で回路基板全体を被
覆している。
この構成によれば、半導体ベレット４は表面の電極パッ
ドに設けた半田バンプ５を直接回路基板１に接続してい
るので、半導体ベレット４と回路基板ｌとを電気接続す
るワイヤが不要となり、回路基板１側にもワイヤを接続
するための端子を設ける必要がない。このため、この分
のスペースを削減でき、実装密度の向上を図ることがで
きる。
なお、半導体ベレット４のサブストレートを回路基板１
に電気接続する際には、上述のように銀ペースト７を利
用すればよい。サブストレートをフローティング状態と
する際には、この銀ペーストの塗布を行わなければよい
。
第３図は本発明の第２実施例を示す断面図であり、この
実施例では、回路基板に半導体メモリペレットを搭載し
た例を示している。
即ち、第１の実施例と同様に回路基板１に半田バンプ５
を利用して半導体メモリペレット４Ａを搭載接続する。
その上で、α線発生源であるウランＵ、トリウムＴｒの
含有量を低α線化（１０−５カウント／　ｈ−ｃ［以下
）した高純度シリコン樹脂９をｌ０ＣＰの粘度にして半
導体メモリペレット４Ａの周辺にデイスペンサー法で塗
布する。そして、真空装置内で半導体メモリペレット４
Ａと回路基板１との隙間にシリコン樹脂９を脱泡充填し
７０°Ｃ１６０分＋　１５０″Ｃ，１２０分のステップ
キュアーで硬化する。
しかる上で、同様にデイスペンサー法で絶縁性エポキシ
樹脂６を塗布し、シリコンを被覆する。
また、必要があれば、第１実施例と同様に銀ペーストア
を用いて半導体メモリペレット４Ａの裏面を回路基板１
に電気接続することは勿論である。
この実施例では、回路基板１上における実装密度の向上
を達成できるとともに、半導体メモリペレット４Ａにお
けるα線障害をシリコン樹脂９で防止することができる
。
〔発明の効果〕
以上説明したように本発明は、回路基板上に搭載する半
導体ペレットを半田バンプを接続して回路基板に電気接
続しているので、回路基板にワイヤ接続用の端子を設け
る必要はなく、実装密度の向上を図ることができる。ま
た、半田バンプを絶縁性樹脂により被覆し、かつ半導体
ペレットの裏面と回路基板とを導電性樹脂等により電気
的に接続しているので、半導体ペレットの封止性を高め
、かつ半導体ペレットのサブストレートへの電位の供給
を可能とする効果がある。
【図面の簡単な説明】
第１図は本発明の第１実施例の断面図、第２図は回路基
板の一部の拡大断面図、第３図は本発明の第２実施例の
断面図である。 ｌ・・・回路基板、２・・・セラミック基板、３・・・
薄膜多層回路、４・・・半導体ペレット、４Ａ・・・半
導一体メモリペレット、５・・・半田バンプ、６・・・
絶縁性エポキシ樹脂、７・・・銀ペースト、８・・・受
動素子、９・・・シリコン樹脂、１１・・・薄膜導体、
１２・・・ポリイミド樹脂、１３・・・スルーホール。

Claims (1)

    【特許請求の範囲】
  1. １．半田バンプを設けた半導体ペレットを回路基板上に
    搭載するとともに、該半田バンプを接続して回路基板に
    電気接続し、前記半田バンプを絶縁性樹脂により被覆す
    る一方、前記半導体ペレットの裏面と回路基板とを導電
    性樹脂等により電気的に接続したことを特徴とする混成
    集積回路。
JP63246515A 1988-09-30 1988-09-30 混成集積回路 Pending JPH0294535A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63246515A JPH0294535A (ja) 1988-09-30 1988-09-30 混成集積回路

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63246515A JPH0294535A (ja) 1988-09-30 1988-09-30 混成集積回路

Publications (1)

Publication Number Publication Date
JPH0294535A true JPH0294535A (ja) 1990-04-05

Family

ID=17149542

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63246515A Pending JPH0294535A (ja) 1988-09-30 1988-09-30 混成集積回路

Country Status (1)

Country Link
JP (1) JPH0294535A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0623242A1 (en) * 1992-01-24 1994-11-09 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
EP0682812A1 (en) * 1993-02-04 1995-11-22 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
EP1263043A1 (en) * 2001-05-30 2002-12-04 Alcatel Electronic element with a shielding

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0623242A1 (en) * 1992-01-24 1994-11-09 Motorola, Inc. Backplane grounding for flip-chip integrated circuit
EP0623242A4 (en) * 1992-01-24 1995-05-03 Motorola Inc GROUNDING OF BOTTOM OF BASKET FOR INTEGRATED CHIP WITH PROTUBERANCES.
EP0682812A1 (en) * 1993-02-04 1995-11-22 Motorola, Inc. Thermally conductive integrated circuit package with radio frequency shielding
EP0682812A4 (en) * 1993-02-04 1998-04-15 Motorola Inc THERMAL-CONDUCTIVE HOUSING FOR INTEGRATED CIRCUITS WITH RADIO FREQUENCY SHIELDING.
EP1263043A1 (en) * 2001-05-30 2002-12-04 Alcatel Electronic element with a shielding
US6713878B2 (en) 2001-05-30 2004-03-30 Stmicroelectronics Electronic element with a shielding

Similar Documents

Publication Publication Date Title
JP3633559B2 (ja) 半導体装置及びその製造方法、回路基板並びに電子機器
JP2592038B2 (ja) 半導体チップ実装方法および基板構造体
JP3499202B2 (ja) 半導体装置の製造方法
JP2565300B2 (ja) 半導体装置
US6744122B1 (en) Semiconductor device, method of manufacture thereof, circuit board, and electronic device
JPH09260552A (ja) 半導体チップの実装構造
JPH05211275A (ja) 半導体装置及びその製造方法
JPH1145954A (ja) フリップチップ接続方法、フリップチップ接続構造体およびそれを用いた電子機器
JPH1116949A (ja) Ａｃｆ接合構造
JPH0294535A (ja) 混成集積回路
JPS63244631A (ja) 混成集積回路装置の製造方法
JPH10340925A (ja) 半導体装置およびその製造方法
JP2630294B2 (ja) 混成集積回路装置およびその製造方法
JPH03257854A (ja) 半導体装置
JP2841825B2 (ja) 混成集積回路
JP3255090B2 (ja) チップの実装構造およびバンプの形成方法
JP2841822B2 (ja) 混成集積回路の製造方法
JP2583242Y2 (ja) 半導体装置
JP3033541B2 (ja) Ｔａｂテープ、半導体装置及び半導体装置の製造方法
JPH0955448A (ja) 半導体装置の製造方法
JPH10144728A (ja) 表面実装部品及びこれを用いたプリント配線板
JPH10125730A (ja) 実装構造体およびその製造方法
JP3257931B2 (ja) 半導体パッケージとその製造方法および半導体装置
JPH0536299Y2 (ja)
JPH0789575B2 (ja) 半導体チップ搭載用プリント配線板