JP2025096318A5 - - Google Patents

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Publication number
JP2025096318A5
JP2025096318A5 JP2025060441A JP2025060441A JP2025096318A5 JP 2025096318 A5 JP2025096318 A5 JP 2025096318A5 JP 2025060441 A JP2025060441 A JP 2025060441A JP 2025060441 A JP2025060441 A JP 2025060441A JP 2025096318 A5 JP2025096318 A5 JP 2025096318A5
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JP
Japan
Prior art keywords
forming
array
insulating
wafer
insulating structure
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2025060441A
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English (en)
Japanese (ja)
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JP2025096318A (ja
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Priority claimed from PCT/CN2018/118705 external-priority patent/WO2020107452A1/en
Application filed filed Critical
Priority to JP2025060441A priority Critical patent/JP2025096318A/ja
Publication of JP2025096318A publication Critical patent/JP2025096318A/ja
Publication of JP2025096318A5 publication Critical patent/JP2025096318A5/ja
Pending legal-status Critical Current

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JP2025060441A 2018-11-30 2025-04-01 接合メモリ装置およびその製作方法 Pending JP2025096318A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2025060441A JP2025096318A (ja) 2018-11-30 2025-04-01 接合メモリ装置およびその製作方法

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
PCT/CN2018/118705 WO2020107452A1 (en) 2018-11-30 2018-11-30 Bonded memory device and fabrication methods thereof
JP2021509877A JP7442504B2 (ja) 2018-11-30 2018-11-30 接合メモリ装置およびその製作方法
JP2023203903A JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法
JP2025060441A JP2025096318A (ja) 2018-11-30 2025-04-01 接合メモリ装置およびその製作方法

Related Parent Applications (1)

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JP2023203903A Division JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法

Publications (2)

Publication Number Publication Date
JP2025096318A JP2025096318A (ja) 2025-06-26
JP2025096318A5 true JP2025096318A5 (https=) 2025-08-14

Family

ID=66060256

Family Applications (3)

Application Number Title Priority Date Filing Date
JP2021509877A Active JP7442504B2 (ja) 2018-11-30 2018-11-30 接合メモリ装置およびその製作方法
JP2023203903A Active JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法
JP2025060441A Pending JP2025096318A (ja) 2018-11-30 2025-04-01 接合メモリ装置およびその製作方法

Family Applications Before (2)

Application Number Title Priority Date Filing Date
JP2021509877A Active JP7442504B2 (ja) 2018-11-30 2018-11-30 接合メモリ装置およびその製作方法
JP2023203903A Active JP7661454B2 (ja) 2018-11-30 2023-12-01 接合メモリ装置およびその製作方法

Country Status (7)

Country Link
US (3) US11114453B2 (https=)
EP (2) EP4471855A3 (https=)
JP (3) JP7442504B2 (https=)
KR (1) KR102482697B1 (https=)
CN (2) CN111739792B (https=)
TW (1) TWI694596B (https=)
WO (1) WO2020107452A1 (https=)

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