JP2024541052A5 - - Google Patents

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Publication number
JP2024541052A5
JP2024541052A5 JP2024525953A JP2024525953A JP2024541052A5 JP 2024541052 A5 JP2024541052 A5 JP 2024541052A5 JP 2024525953 A JP2024525953 A JP 2024525953A JP 2024525953 A JP2024525953 A JP 2024525953A JP 2024541052 A5 JP2024541052 A5 JP 2024541052A5
Authority
JP
Japan
Prior art keywords
process according
dielectric layer
charge trap
period
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2024525953A
Other languages
English (en)
Japanese (ja)
Other versions
JP2024541052A (ja
Filing date
Publication date
Priority claimed from FR2111876A external-priority patent/FR3129029B1/fr
Application filed filed Critical
Publication of JP2024541052A publication Critical patent/JP2024541052A/ja
Publication of JP2024541052A5 publication Critical patent/JP2024541052A5/ja
Pending legal-status Critical Current

Links

JP2024525953A 2021-11-09 2022-10-19 電荷トラップ層が設けられた支持基板を用意するための方法 Pending JP2024541052A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FR2111876 2021-11-09
FR2111876A FR3129029B1 (fr) 2021-11-09 2021-11-09 Procede de preparation d’un substrat support muni d’une couche de piegeage de charges
PCT/FR2022/051974 WO2023084168A1 (fr) 2021-11-09 2022-10-19 Procede de preparation d'un substrat support muni d'une couche de piegeage de charges

Publications (2)

Publication Number Publication Date
JP2024541052A JP2024541052A (ja) 2024-11-06
JP2024541052A5 true JP2024541052A5 (https=) 2025-08-28

Family

ID=80786168

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2024525953A Pending JP2024541052A (ja) 2021-11-09 2022-10-19 電荷トラップ層が設けられた支持基板を用意するための方法

Country Status (8)

Country Link
US (1) US20240387243A1 (https=)
EP (1) EP4430653B1 (https=)
JP (1) JP2024541052A (https=)
KR (1) KR20240091354A (https=)
CN (1) CN117999634A (https=)
FR (1) FR3129029B1 (https=)
TW (1) TW202329362A (https=)
WO (1) WO2023084168A1 (https=)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1087041B1 (en) 1999-03-16 2009-01-07 Shin-Etsu Handotai Co., Ltd Production method for silicon wafer and silicon wafer
FR2838865B1 (fr) 2002-04-23 2005-10-14 Soitec Silicon On Insulator Procede de fabrication d'un substrat avec couche utile sur support de resistivite elevee
FR2860341B1 (fr) 2003-09-26 2005-12-30 Soitec Silicon On Insulator Procede de fabrication de structure multicouche a pertes diminuees
FR2933233B1 (fr) 2008-06-30 2010-11-26 Soitec Silicon On Insulator Substrat de haute resistivite bon marche et procede de fabrication associe
FR2953640B1 (fr) 2009-12-04 2012-02-10 S O I Tec Silicon On Insulator Tech Procede de fabrication d'une structure de type semi-conducteur sur isolant, a pertes electriques diminuees et structure correspondante
FR2973159B1 (fr) 2011-03-22 2013-04-19 Soitec Silicon On Insulator Procede de fabrication d'un substrat de base
FR2985812B1 (fr) 2012-01-16 2014-02-07 Soitec Silicon On Insulator Procede et dispositif de test de substrats semi-conducteurs pour applications radiofrequences
US9768056B2 (en) 2013-10-31 2017-09-19 Sunedison Semiconductor Limited (Uen201334164H) Method of manufacturing high resistivity SOI wafers with charge trapping layers based on terminated Si deposition
JP6100200B2 (ja) 2014-04-24 2017-03-22 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
JP6353814B2 (ja) * 2015-06-09 2018-07-04 信越半導体株式会社 貼り合わせsoiウェーハの製造方法
WO2020008116A1 (fr) 2018-07-05 2020-01-09 Soitec Substrat pour un dispositif integre radioafrequence et son procede de fabrication

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