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  • H10P14/6304—Formation by oxidation, e.g. oxidation of the substrate
  • H10P14/6306—Formation by oxidation, e.g. oxidation of the substrate of the semiconductor materials
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  • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
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Definitions

• TITLE METHOD FOR PREPARING A SUPPORT SUBSTRATE PROVIDED WITH A CHARGE-TRAPPING LAYER
• the present invention relates to a process for preparing a support substrate comprising a charge trapping layer. It also relates to a process for transferring a thin layer onto such a support substrate to form a composite substrate.
• These support and composite substrates find a significant application in the field of integrated radiofrequency devices, that is to say electronic devices processing signals whose frequency is between about 3 kHz and 300 GHz, for example in the field of telecommunications (telephony , Wi-Fi , Bluetooth...) .
• This layer can consist, for example, of a layer of 0.1 to 10 microns of polycrystalline silicon formed on a base substrate of monocrystalline silicon which is often chosen to be highly resistive (that is to say having a higher resistivity to 500 ohms.cm, or even greater than 1000 ohms.cm).
• the joints of the grains forming the polycrystal then constitute traps for the charge carriers, these being able to come from the trapping layer itself or the underlying substrate. In this way, the appearance of a conductive plane under the insulation is prevented.
• the manufacture of this type of well-known SOI substrate is for example described in the documents FR2860341, FR2933233, FR2953640, US2015115480, US7268060, US6544656 or WO2020008116.
• a layer of amorphous dielectric typically a layer of silicon dioxide.
• the amorphous dielectric layer makes it possible to preserve the polycrystalline character of the trapping layer by avoiding its recrystallization when the stack is brought to temperature.
• Document EP3136421 thus proposes forming a polycrystalline silicon trapping layer on a base substrate having a resistivity of 700 Ohms-cm.
• the base substrate is oxidized by simple cleaning or by dry oxidation.
• the trapping layer is formed in two successive deposition steps using a trichlorosilane precursor gas.
• the first step aims to form a seed layer at relatively low temperature, below 1010° C., directly on the silicon oxide layer, and the second step is carried out at a temperature higher than the first.
• this approach makes it possible to form the trapping layer quickly, and without excessively deforming the base substrate, which could prevent assembly by molecular adhesion of this substrate when it is intended to form a support substrate for a silicon on insulator substrate.
• the document EP3309819 proposes to form, during two successive steps carried out in separate equipment, a layer dielectric on an exposed face of a base substrate and a charge trapping layer on the dielectric layer.
• the charge trapping layer is conducted at a temperature between 1050°C and 1200°C.
• the trapping layer is formed on a dielectric layer of a silicon base substrate without removing the base substrate from the equipment used to form this stack. It may be a chamber of an epitaxy frame.
• the base substrate is placed in the chamber of the equipment, and an oxidizing gas is circulated in this chamber to superficially form the dielectric layer during an oxidation step carried out at a temperature of order of 1100°C. Then, without extracting the base substrate from the chamber, a carrier gas is circulated to evacuate the oxidizing gas and the temperature of the chamber and/or of the substrate is brought to a relatively low deposition temperature, of the order of 900 °C or less.
• the precursor gas containing silicon is introduced to gradually form, by deposition, the polycrystalline silicon layer on the dielectric layer.
• the precursor gas containing silicon is introduced to gradually form, by deposition, the polycrystalline silicon layer on the dielectric layer.
• An object of the invention is to propose a process for preparing a support substrate provided with a charge trapping layer which at least partly addresses this problem. More specifically, an object of the invention is to propose a method for preparing a support substrate provided with a charge trapping layer, the implementation time of which, at comparable quality, is reduced in comparison with the methods of the state of the art. More precisely still, an object of the invention is to propose a process for preparing a support substrate provided with a charge trapping layer which does not require a seed portion formed at a relatively low temperature of approximately 1010° C. or less. . BRIEF DESCRIPTION OF THE INVENTION
• the object of the invention proposes a process for preparing a support substrate provided with a charge trapping layer.
• the method includes introducing a single crystal silicon base substrate having a resistivity greater than 500 ohm. cm in a chamber of a deposition equipment and, without extracting the base substrate from the chamber and while sweeping the chamber with the aid of a carrier gas, the following successive steps: forming a dielectric layer on an exposed face the base substrate by introducing a reactive gas into the chamber over a first period of time; forming a polysilicon charge trapping layer directly on the dielectric layer by introducing a silicon-containing precursor gas into the chamber during a second time period subsequent to the first.
• the time during which the dielectric layer is exposed only to the carrier gas, between the first period of time and the second period of time, is less than 30 seconds.
• the step of forming the charge trapping layer is carried out at a temperature strictly between 1010°C and 1200°C.
• the surface condition of this layer is conditioned or maintained to make it particularly suitable for receiving a quality polycrystalline silicon layer, identical to that obtained at a much lower temperature in an approach in accordance with the state of the art.
• the carrier gas comprises, or consists of, hydrogen
• the silicon-containing precursor gas is chosen from the list consisting of silane, disilane, trichlorosilane, dicholorosilane and silicon tetrachloride
• the dielectric layer is made of silicon oxide and the reactive gas comprises between 0.1% and 10% oxygen in a neutral gas such as argon
• the step of forming the dielectric layer is carried out at a temperature between 1010° C.
• the dielectric layer has a thickness greater than 0.5 nm; the step of forming the charge trapping layer is carried out at a temperature above 1050° C., or at 1100° C.; the charge trapping layer and the dielectric layer are formed at respective temperatures which are identical to within 50° C.; the time during which the dielectric layer is exposed only to the carrier gas is less than 20 seconds or less than 15 seconds; the charge trapping layer has a thickness of between 0.1 and 10 microns.
• Figure 1 shows a support substrate according to a first embodiment
• Figure 2 shows a support substrate according to a second embodiment
• Figure 3 shows a composite substrate which comprises a support substrate according to the present invention
• Figure 4 illustrates the succession of the two main steps of a method according to the invention.
• a support substrate 1 of one embodiment comprises a base substrate 2, a dielectric layer 3 disposed on the base substrate 2 and a charge trapping layer 4 disposed on the dielectric layer 3 and in contact with this layer.
• the support substrate 1 can take the form of a wafer, circular, of standardized size, for example 200 mm or 300 mm, even 450 mm in diameter. But the invention is in no way limited to these dimensions or to this shape.
• the base substrate 2 is made of monocrystalline silicon and has a thickness of several hundreds of microns.
• the base substrate 2 has a high resistivity, strictly greater than 500 or 1000 ohms. cm, and more preferably still greater than 3000 ohms. cm. This limits the density of charges, holes or electrons, which are likely to move in the base substrate 2, and therefore deteriorate the RF performance of the final substrate S.
• It may be for example a CZ substrate with a low interstitial oxygen content which has, as is well known per se, a resistivity which can be greater than 1000 ohms. cm.
• the invention is not limited to a base substrate 2 having such a resistivity, and it also provides RF performance advantages when the base substrate 2 has a more consistent resistivity, less than or equal to 500 ohms. cm, or 100 ohms. cm or less. In this case, it may be a more standard monocrystalline CZ substrate, the resistivity of which is less than 500 ohms. cm. This approach is advantageous, in that such a substrate can be provided easily and at low cost.
• the support substrate may also include, in particular when the base substrate 2 has a resistivity less than or equal to 500 ohms.com, an intrinsic monocrystalline silicon layer 5, that is to say unintentionally doped and therefore particularly resistive, arranged between the base substrate 2 and the dielectric layer 3.
• the layer of intrinsic monocrystalline silicon 5 advantageously has a resistivity greater than 2000 ohm. cm, which can even reach 20 kohm.cm or more. Its thickness can be between 0.5 and 100 microns, and preferably between 5 and 20 microns.
• the dielectric layer 3 for example made of silicon oxide or silicon nitride, has a thickness greater than 0.5 nm, for example between 0.5 nm and 50 nm.
• This dielectric layer 3, amorphous, makes it possible to form the charge trapping layer 4 in a polycrystalline form, and to avoid or limit the recrystallization of this layer, when the support substrate 1 is exposed to a high temperature, during the formation of this layer 4 or during the subsequent heat treatments that the support substrate 1 is subjected to.
• the support substrate 1 also includes a charge trapping layer 4 of polycrystalline silicon, arranged on and directly in contact with the dielectric layer 3.
• the trapping layer 4 has a resistivity greater than 500 ohm. cm, preferably greater than 1 kohm.cm.
• the function of the trapping layer is to trap the charge carriers which may be present in the support 1 and to limit their mobility.
• the charge trapping layer 4 has a thickness typically comprised between 0.1 micron and 10 microns, or even more.
• the trapping layer 4 due to its non-crystalline nature, has structural defects such as dislocations, grain boundaries, amorphous zones, interstices, inclusions, pores defining the grains of the layer, etc. These Structural defects form traps for the charges likely to flow through the material, for example at the level of incomplete or dangling chemical bonds. This prevents conduction in the trapping layer, and the substrate support 1 therefore has a high radiofrequency performance.
• This performance can be established by a so-called “second harmonic distortion” characterization measurement on a support thus prepared. This measurement is typically performed at 900 MHz. It is generally sought for the distortion measurement to be less than ⁇ 70 dB so that the support substrate can be considered to have high radio frequency performance.
• the dimension of the grains of the trapping layer 4 of polycrystalline silicon is advantageously between 50 nm (below which their thermal stability is no longer ensured and where there is a risk of their recrystallization at temperature) and 2000 nm (beyond which the RF performance of the supporting substrate is affected).
• FIG. 3 represents a composite substrate S which comprises a support substrate 1 in accordance with the present invention.
• the composite substrate comprises, on support substrate 1, a thin film 6 preferably made of crystalline material.
• the thin film 6 can be made of semiconductor material, such as silicon, or of piezoelectric material, such as lithium tantalate (LiTaOs) or lithium niobate (LiNbOs).
• the composite substrate S of FIG. 3 can be formed in many ways from the support substrate 1, but advantageously this formation comprises a step of transferring the thin film 6 onto this support substrate. As is well known per se, this transfer is usually carried out by assembling so-called “main” faces of a donor substrate and of the support substrate 1. Provision is generally made to provide at least one of these faces with a layer of dielectric assembly 7, typically of silicon oxide, which can be formed by heat treatment or by deposition. The assembly preferably implements bonding by molecular adhesion.
• the thickness of the donor substrate is reduced in order to form the thin film 6.
• This reduction step can be carried out by mechanical or chemical thinning. It can also be performed by fracturing at the level of a fragile zone previously introduced into the donor substrate, for example in accordance with the principles of Smart CutTM technology.
• Thin film 6 finishing steps such as a polishing step, heat treatment under a reducing or neutral atmosphere or sacrificial oxidation can be linked with the thickness reduction step.
• the donor substrate may be a simple substrate, that is to say not comprising any integrated devices, or alternatively the donor substrate may have been previously treated in order to produce integrated devices on its surface.
• the base substrate 2 in monocrystalline silicon is introduced into a chamber of deposition equipment.
• This equipment may correspond to epitaxy deposition equipment. It comprises a susceptor arranged in the chamber to receive the base substrate and to expose one of these faces to the atmosphere and to the gas flows circulating in the chamber.
• the susceptor can be mobile, and in particular have a rotational movement to angularly standardize the exposure of the free face of the base substrate 2 to the flow of gas.
• the latter is provided with a plurality of inlet ports, and with at least one exhaust port.
• the chamber is also equipped with a device for heating the substrate, the gases and/or the walls of the chamber, for example lamps emitting radiation capable of heating the free surface of the base substrate.
• a plurality of ducts fluidly connected to the inlet ports of the chamber makes it possible to introduce with a controlled flow rate the gases allowing the treatment of the base substrate 2.
• This is in particular a reactive, oxidizing or nitriding gas, a carrier gas, for example a mixture of argon and hydrogen, or hydrogen, and a precursor gas containing silicon.
• This precursor gas can be, for example, silane, disilane, trichlorosilane, dicholorosilane and silicon tetrachloride.
• the equipment can of course be provided with other conduits to introduce other gases into the chamber.
• the equipment is also provided with a control device configured to control all the parameters (flow rates of the various gases, temperature, pressure, etc.) of the preparation process implemented.
• the process for preparing the support substrate in accordance with the previous section of the present description notably comprises two main steps, which are carried out without extracting the base substrate 2 from the chamber of the equipment. Consequently, the base substrate is not exposed to gases or atmospheres other than those which are introduced or present in the chamber throughout the duration of the preparation process.
• the carrier gas GPo is introduced into the chamber at a determined flow rate via an inlet port to sweep it throughout the duration of the process for preparing the donor substrate, and in particular during the two main steps of this process.
• the dielectric layer 3 is formed on the exposed face of the base substrate 2 by introducing into the chamber, and with a chosen flow rate, a reactive gas GR, during a first time period T1.
• the heating device is controlled so that the dielectric layer is formed at a temperature typically between 900°C and 1150°C, and preferably between 950°C and 1100°C.
• this reactive gas can be formed from an oxidizing gas or a nitriding gas.
• the dielectric layer is made of silicon oxide, and in this case the reactive gas can for example comprise between 0.1% and 10% oxygen in a neutral gas such as argon.
• the oxidizing atmosphere of the chamber is maintained for a duration chosen (the first period of time) according to the desired thickness of the dielectric layer 3.
• the dielectric layer 3 has a thickness greater than 0.5 nm.
• a charge trapping layer 4 is formed in polycrystalline silicon directly on the dielectric layer 3 by introducing into the chamber, and with a chosen flow rate, the precursor gas GPr containing silicon, at the during a second time period T2 subsequent to the first time period T1.
• the amorphous nature of the dielectric layer prevents the crystallization of the trapping layer which forms during this second stage, which could occur if this dielectric layer was not present.
• the sequence of the first and second stages is carried out in a controlled manner, in particular to prevent a mixture of reactive and precursor gases from occurring, which could cause unwanted chemical reactions in the chamber and prevent the deposit of a target quality trapping layer.
• the first stage during which the reactive gas forms the atmosphere of the chamber does not overlap the second stage during which the precursor gas forms the atmosphere of the chamber. bedroom .
• the carrier gas which constantly sweeps the chamber throughout the duration of the preparation process, expels the reactive gas from the chamber.
• This transition period is also used to adjust the temperature of the chamber and/or of the substrate, in the case where the temperature of the first stage is different from the temperature of the second stage.
• the precursor gas is introduced into the chamber.
• the atmosphere and the temperature of this chamber are therefore perfectly suited to the formation of a quality charge trapping layer 4 .
• the carrier gas and the precursor gas circulate simultaneously in the chamber during the remainder of this second process step.
• the growth of the trapping layer is carried out, at least on a seed portion in contact with the dielectric layer, at a relatively low temperature of 1010° C. or less in order to obtain a layer of satisfactory quality.
• This quality is measured in particular by measuring second harmonic distortion. It is also measured by the stress in the charge trapping layer 4 which can tend to deform the substrate if it is too great. It is generally sought to limit this deformation (typically a curvature designated by the English term “bow” in semiconductor technology), for a substrate 300 mm in diameter, to less than 200 microns or even less than 100 microns.
• the inventors of the present application observed that it was possible to obtain a trapping layer 4 of quality quite similar to that of the state of the art, by carrying out this second step at a relatively higher temperature, strictly greater than 1010° C., provided that the duration of the transition period Tt did not exceed 30 seconds.
• the formation of the charge trapping layer 4 can be conducted at a temperature above 1010° C., and typically between 1010° C. and 1200° C., while exhibiting an acceptable quality of this layer, both in deformation and in measurement of distortion of second harmonic.
• the surface condition of this layer 3 is conditioned or maintained. to make it particularly suitable for the direct growth of the trapping layer 4 at a much higher temperature than in the state of the art.
• the growth rate at 950°C is of the order of 0.8 microns per minute, of the order of 1.25 microns per minute at 1000°C and of the order of 2 microns per minute at 1100°C, which is notably higher than the 0.3 micron per minute observed at 900°C.
• the rate of production of a support substrate is then significantly improved compared to the rate obtained using the methods of the state of the art. This is particularly the case when the trapping layer is relatively thick, greater than 2 microns.
• the step of forming this layer 4 is preferably carried out at a temperature strictly above 1010° C., at 1050° C., or above 1100° C. .
• the latter is carried out for a period of time sufficient to form a targeted thickness of polycrystalline silicon, directly on the dielectric layer 3.
• the treatment temperature can be lowered during this period, for example by 50° C. with respect to the temperature of the first period of time.
• the charge trapping layer 4 and the dielectric layer 3 are formed at identical respective temperatures to within 50° C.
• the two stages can be linked together as was presented previously by maintaining the same temperature of 1050° C. or 1100° C. for the first and the second stage. Since it is not necessary to raise or lower the temperature between the two stages, the duration of the transition period can be reduced more easily, under 30 seconds, for example under 20 seconds or even 15 seconds.
• the dielectric layer 3 can be formed at a temperature higher, lower or equal to the temperature at which the charge trapping layer 4 is formed.
• the first step of forming dielectric layer 3 can be preceded by deoxidation annealing of the base substrate in a reducing or slightly reducing atmosphere, at a temperature between 900° C. and 1200° C., to eliminate a native oxide optionally present superficially on the base substrate 2 .
• This annealing can be carried out while only the carrier gas circulates in the chamber, for a period of several seconds to several minutes, depending on the chosen temperature, in order to eliminate this native oxide.
• the treatment method comprises, between the deoxidation annealing and the first step of formation of the dielectric layer 3 , the formation of this epitaxial layer of intrinsic silicon 5 on the base substrate 2 , at a temperature of epitaxy typically between 900°C and 1200°C.
• the carrier and precursor gases containing silicon can be circulated simultaneously in the chamber.
• these steps of deoxidation annealing and/or formation of an epitaxial layer are also carried out "in situ", that is to say without extracting the base substrate 2 from the chamber of the equipment and without expose the free surface of the support 1 being prepared to gases or atmospheres other than those which are introduced or present in the chamber throughout the duration of the process.

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Citations (11)

• 2021
  • 2021-11-09 FR FR2111876A patent/FR3129029B1/fr active Active
• 2022
  • 2022-10-19 EP EP22835457.7A patent/EP4430653B1/fr active Active
  • 2022-10-19 CN CN202280064300.9A patent/CN117999634A/zh active Pending
  • 2022-10-19 KR KR1020247018657A patent/KR20240091354A/ko active Pending
  • 2022-10-19 WO PCT/FR2022/051974 patent/WO2023084168A1/fr not_active Ceased
  • 2022-10-19 US US18/688,606 patent/US20240387243A1/en active Pending
  • 2022-10-19 JP JP2024525953A patent/JP2024541052A/ja active Pending
  • 2022-11-09 TW TW111142742A patent/TW202329362A/zh unknown

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