JP2021517737A - 選択的ボンドアウトのための電源島セグメンテーション - Google Patents
選択的ボンドアウトのための電源島セグメンテーション Download PDFInfo
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- 230000008878 coupling Effects 0.000 claims description 9
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- 238000005859 coupling reaction Methods 0.000 claims description 9
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- 238000000034 method Methods 0.000 description 2
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- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0616—Random array, i.e. array with no symmetry
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- H01L2224/061—Disposition
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- H01L2224/06177—Combinations of arrays with different layouts
Abstract
Description
Claims (20)
- 基板上に形成された半導体ダイを具備する半導体チップであって、前記半導体ダイは、
前記基板上に形成された第1の電源メッシュと、
前記基板上に形成され、前記第1の電源メッシュから電気的に分離されるように構成された第2の電源メッシュと、
前記基板上に形成された第1の回路ブロックであって、前記第1の回路ブロックに電力を供給するように構成された前記第1の電源メッシュに電気的に接続された第1の回路ブロックと、
前記基板上に形成された第2の回路ブロックであって、前記第2の回路ブロックに電力を供給するように構成された第2の電源メッシュに電気的に接続された前記第2の回路ブロックと、
前記第1の回路ブロックに通信可能に結合され、前記第2の回路ブロックから通信的に分離された第1の複数の外部回路接続部と、
前記第2の回路ブロックに通信可能に結合され、前記第1の回路ブロックから通信的に分離された第2の複数の外部回路接続部と、
前記基板上に形成され、第1の一つ以上の外部信号を受信するように通信可能に結合するように構成された一つ以上の第1の信号ピンと、
前記基板上に形成され、第2の一つ以上の外部信号を受信するように通信可能に結合するように構成された一つ以上の第2の信号ピンとを具備する、半導体チップ。 - 前記第2の回路ブロックは、稼働しないように構成されている請求項1に記載の半導体チップ。
- 前記第1の回路ブロックは、前記一つ以上の第1の信号ピンの少なくとも一つおよび前記一つ以上の第2の信号ピンの少なくとも一つに結合されている請求項2に記載の半導体チップ。
- 前記第2の回路ブロックは、前記一つ以上の第2の信号ピンの少なくとも一つに結合され、且つ前記一つ以上の第1の信号ピンのうちのいずれにも結合されていない請求項3に記載の半導体チップ。
- 前記一つ以上の第1の信号ピンは、電源を受け取るように構成され、前記一つ以上の第2の信号ピンは、グランド電源を受け取るように構成されている請求項4に記載の半導体チップ。
- 前記第2の電源メッシュは、前記電源から電力を受け取らない請求項5に記載の半導体チップ。
- 前記第1の電源メッシュは、グランドに接続するように構成された接続部の第1の層と、電源に接続するように構成された接続部の第2の層とを提供することによってセグメント化され、前記第2の電源メッシュは、グランドに接続するように構成された接続部の第3の層と、電源に接続するように構成された接続部の第4の層とを提供することによってセグメント化されている請求項4に記載の半導体チップ。
- 前記第3の層および前記第4の層に接続された信号ピンそれぞれは前記電源に結合されていない請求項7に記載の半導体チップ。
- 前記第3層および前記第4層に接続された信号ピンそれぞれはグランド電源に結合されている請求項8に記載の半導体チップ。
- 前記第1の回路ブロックを通る電流のフローは、前記第2の回路ブロックにおける漏れ電流を含まない請求項1に記載の半導体チップ。
- 前記第1の回路ブロックおよび前記第2の回路ブロックは、ボールグリッドアレイで実現される請求項1に記載の半導体チップ。
- 前記第2の回路ブロックは、複数のボール接続部によって、グランド電源に接続される請求項11に記載の半導体チップ。
- 前記第1の複数の外部回路接続部に結合された複数の外部デバイスをさらに具備する請求項1に記載の半導体チップ。
- 基板上に形成された半導体ダイを製造する製造方法であって、
前記基板上に第1の回路ブロックを形成することと、
前記基板上に第2の回路ブロックを形成することと、
前記半導体ダイを、第1の電源メッシュと、電気的に電離された第2の電源メッシュとにセグメント化することと、
前記第1の電源メッシュは、前記第1の回路ブロックに電気的に結合し、前記第1の回路ブロックに電力を供給するように構成されており、前記第2の電源メッシュは、前記第2の回路ブロックに電気的に結合し、前記第2の回路ブロックに電力を供給するように構成されており、
第1の複数の外部回路接続部が前記第2の回路ブロックから通信的に分離するように、前記第1の複数の外部回路接続部を前記第1の回路ブロックに通信可能に結合することと、
第2の複数の外部回路接続部が前記第1の回路ブロックから通信的に分離するように、前記第2の複数の外部回路接続部を前記第2の回路ブロックに通信可能に結合することと、
前記第1の電源メッシュを、一つ以上の外部信号を受け取るように構成された一つ以上の第1の信号ピンに接続することと、
前記第2の電源メッシュを、一つ以上の外部信号を受け取るように構成された一つ以上の第2の信号ピンに接続することとを具備する、製造方法。 - 前記一つ以上第1の信号ピンに電源信号を供給し、前記一つ以上の第2の信号ピンにグランド信号を供給することをさらに具備する請求項14に記載の製造方法。
- 複数の外部デバイスを、前記第1の複数の外部回路接続部に結合することをさらに具備する請求項15に記載の製造方法。
- 前記半導体ダイを前記第1の電源メッシュと前記第2の電源メッシュとにセグメント化することは、グランドに接続するように構成された接続部の第1の層と、電源に接続するように構成された接続部の第2の層とを提供することを具備し、前記第2の電源メッシュは、グランドに接続するように構成された第3の層と、前記電源に接続するように構成された第4の層とを提供することによってセグメント化される請求項14に記載の製造方法。
- 前記一つ以上の第1の信号ピンに電源信号を供給することによって第1の電源メッシュを通して電流のフローを供給することをさらに具備し、前記第1の電源メッシュを通る電流のフローは、前記第2の電源メッシュにおける漏れ電流を誘発しない請求項14に記載の製造方法。
- 前記第1の回路ブロックを形成すること、および前記第2の回路ブロックを形成することとは、前記第1の回路ブロック、および前記第2の回路ブロックをボールグリッドアレイで実現することをさらに具備する請求項14に記載の製造方法。
- 第1の個数のボール接続部によって、前記一つ以上の第1の信号ピンに前記第1の回路ブロックを接続することをさらに具備し、前記一つ以上の第1の信号ピンし、前記第1の電源メッシュを通して前記第1の回路ブロックに電力を供給するように構成されている請求項19に記載の製造方法。
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US15/920,002 US10629533B2 (en) | 2018-03-13 | 2018-03-13 | Power island segmentation for selective bond-out |
US15/920,002 | 2018-03-13 | ||
PCT/IB2019/000225 WO2019175656A1 (en) | 2018-03-13 | 2019-03-08 | Power island segmentation for selective bond-out |
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JP7317848B2 JP7317848B2 (ja) | 2023-07-31 |
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JP (1) | JP7317848B2 (ja) |
CN (1) | CN112204735B (ja) |
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US11449660B1 (en) * | 2020-03-10 | 2022-09-20 | Synopsys, Inc. | Method to perform secondary-PG aware buffering in IC design flow |
TWI767841B (zh) * | 2021-09-17 | 2022-06-11 | 智原科技股份有限公司 | 運用於積體電路的電源網結構 |
CN113838815A (zh) * | 2021-09-23 | 2021-12-24 | 西安紫光国芯半导体有限公司 | 基板和芯片组件 |
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US20200227353A1 (en) | 2020-07-16 |
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