JP2020170798A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2020170798A JP2020170798A JP2019071739A JP2019071739A JP2020170798A JP 2020170798 A JP2020170798 A JP 2020170798A JP 2019071739 A JP2019071739 A JP 2019071739A JP 2019071739 A JP2019071739 A JP 2019071739A JP 2020170798 A JP2020170798 A JP 2020170798A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 230000005611 electricity Effects 0.000 claims 1
- 239000002184 metal Substances 0.000 abstract description 19
- 239000000758 substrate Substances 0.000 description 22
- 230000014759 maintenance of location Effects 0.000 description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 5
- 229920005591 polysilicon Polymers 0.000 description 5
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004044 response Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/18—Peripheral circuit regions
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B10/00—Static random access memory [SRAM] devices
- H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Static Random-Access Memory (AREA)
- Semiconductor Memories (AREA)
Abstract
Description
さらに本発明は、読出しマージンやデータの保持に影響を与えることなく書込みマージンを改善することができる半導体装置を提供することを目的とする。
本発明は、
110:メモリセルアレイ
120:入出力バッファ
130:コントローラ
140:行選択・駆動回路
150:S/D端子線駆動回路
160:列選択回路
170:読出し・書込み回路
180:基板端子線駆動回路
190:内部電圧発生回路
Psub:基板端子(PMOSトランジスタ)
Psd:S/D端子(PMOSトランジスタ)
Nsub:基板端子(NMOSトランジスタ)
Nsd;S/D端子(NMOSトランジスタ)
Psub0〜Psubm:基板端子線
Psd0〜Psdn:S/D端子線
Claims (10)
- 一対のP型のプルアップ用トランジスタおよび一対のN型のプルダウン用トランジスタを含むラッチ回路と一対のN型のアクセス用トランジスタとを含むメモリセルが複数形成されたメモリセルアレイを含む半導体装置であって、
第1の方向に延在し、前記プルダウン用トランジスタと前記アクセス用トランジスタとが形成されたPウエル領域と、
第1の方向に延在し、前記プルアップ用トランジスタが形成されたNウエル領域と、
前記Pウエル領域および前記Nウエル領域上を第1の方向と直交する第2の方向に延在し、前記Nウエル領域内に形成された前記プルアップ用トランジスタの共通のS/D領域に電気的に接続された第1の配線層と、
前記Nウエル領域上を第1の方向に延在し、前記Nウエル領域に電気的に接続された第2の配線層と、
を有する半導体装置。 - 前記Pウエル領域は、一方のプルダウン用トランジスタおよび一方のアクセス用トランジスが形成された第1のPウエル領域と、他方のプルダウン用トランジスタおよびアクセス用トランジスタが形成された第2のPウエル領域とを含み、
前記Nウエル領域は、第1のPウエル領域と第2のPウエル領域との間に配置される、請求項1に記載の半導体装置。 - 前記第1の配線層は、前記第2の配線層と電気的に分離され、前記第1の配線層は、前記第2の配線層よりも上層または下層である、請求項1または2に記載の半導体装置。
- 半導体装置はさらに、
前記Pウエル領域および前記Nウエル領域上を第2の方向に延在し、前記アクセス用トランジスタのゲートに電気的に接続されたワード線と、
前記Pウエル領域上を第1の方向に延在し、前記アクセス用トランジスタのS/D領域に電気的に接続されたビット線とを有する、請求項1ないし3いずれか1つに記載された半導体装置。 - 半導体装置はさらに、
選択されたメモリセルにデータを書込む書込み手段を含み、
前記書込み手段は、前記第1の配線層を介してS/D領域に第1の電圧を印加し、かつ前記第2の配線層を介して前記Nウエル領域に第2の電圧を印加し、第1の電圧が第2の電圧よりも小さい、請求項1ないし4いずれか1つに記載の半導体装置。 - 半導体装置はさらに、
選択されたメモリセルからデータを読み出す読出し手段を含み、
前記読出し手段は、前記第1の配線層を介してS/D領域に第3の電圧を印加し、かつ前記第2の配線層を介して前記Nウエル領域に第4の電圧を印加し、第3の電圧が第4の電圧と等しいかそれよりも高い、請求項1ないし5いずれか1つに記載の半導体装置。 - 半導体装置はさらに、
行アドレスに基づきワード線を選択しアクセス用トランジスタを導通させるワード線選択手段を含み、
前記書込み手段は、前記ワード線選択手段によってアクセス用トランジスタが導通する期間内において前記第1の電圧を一定期間印加する、請求項5に記載の半導体装置。 - 前記読出し手段は、
前記ワード線選択手段によってアクセス用トランジスタが導通する期間内において前記第3の電圧を一定期間印加する、請求項6に記載の半導体装置。 - 前記書込み手段は、行アドレスに基づき複数の第1の配線層の中から第1の配線層を選択し、かつ列アドレスに基づき複数の第2の配線層の中から第2の配線層を選択し、選択された第1の配線層に前記第1の電圧を印加し、選択された第2の配線層に前記第2の電圧を印加する、請求項5または7に記載の半導体装置。
- 前記読出し手段は、行アドレスに基づき複数の第1の配線層の中から第1の配線層を選択し、かつ列アドレスに基づき複数の第2の配線層の中から第2の配線層を選択し、選択された第1の配線層に前記第3の電圧を印加し、選択された第2の配線層に前記第4の電圧を印加する、請求項6または8に記載の半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019071739A JP6901515B2 (ja) | 2019-04-04 | 2019-04-04 | 半導体装置 |
TW108142103A TWI735081B (zh) | 2019-04-04 | 2019-11-20 | 半導體裝置 |
KR1020200031592A KR102233532B1 (ko) | 2019-04-04 | 2020-03-13 | 반도체 장치 |
CN202010212472.9A CN111798899B (zh) | 2019-04-04 | 2020-03-24 | 半导体装置 |
US16/830,983 US11430796B2 (en) | 2019-04-04 | 2020-03-26 | SRAM layout scheme for improving write margin |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019071739A JP6901515B2 (ja) | 2019-04-04 | 2019-04-04 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2020170798A true JP2020170798A (ja) | 2020-10-15 |
JP6901515B2 JP6901515B2 (ja) | 2021-07-14 |
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JP2019071739A Active JP6901515B2 (ja) | 2019-04-04 | 2019-04-04 | 半導体装置 |
Country Status (5)
Country | Link |
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US (1) | US11430796B2 (ja) |
JP (1) | JP6901515B2 (ja) |
KR (1) | KR102233532B1 (ja) |
CN (1) | CN111798899B (ja) |
TW (1) | TWI735081B (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001338993A (ja) * | 2000-03-24 | 2001-12-07 | Toshiba Corp | 半導体装置 |
JP2004303340A (ja) * | 2003-03-31 | 2004-10-28 | Renesas Technology Corp | 半導体記憶装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5351208A (en) * | 1992-04-27 | 1994-09-27 | Integrated Information Technology, Inc. | Content addressable memory |
JP4565700B2 (ja) * | 1999-05-12 | 2010-10-20 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP2003218238A (ja) * | 2001-11-14 | 2003-07-31 | Mitsubishi Electric Corp | 半導体記憶装置 |
JP4822791B2 (ja) * | 2005-10-04 | 2011-11-24 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7535788B2 (en) | 2006-12-08 | 2009-05-19 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dynamic power control for expanding SRAM write margin |
JP5263495B2 (ja) * | 2008-01-25 | 2013-08-14 | ルネサスエレクトロニクス株式会社 | スタティック型半導体記憶装置 |
JP5932133B2 (ja) | 2012-03-30 | 2016-06-08 | インテル コーポレイション | 書込マージンを改善されたメモリセル |
US9171608B2 (en) * | 2013-03-15 | 2015-10-27 | Qualcomm Incorporated | Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods |
US9208854B2 (en) * | 2013-12-06 | 2015-12-08 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three dimensional dual-port bit cell and method of assembling same |
US9305633B2 (en) * | 2014-04-17 | 2016-04-05 | Stmicroelectronics International N.V. | SRAM cell and cell layout method |
WO2017046850A1 (ja) * | 2015-09-14 | 2017-03-23 | 株式会社 東芝 | 半導体メモリデバイス |
US9515077B1 (en) * | 2015-12-18 | 2016-12-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Layout of static random access memory cell |
US11094685B2 (en) * | 2016-11-29 | 2021-08-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | Static random access memory device |
-
2019
- 2019-04-04 JP JP2019071739A patent/JP6901515B2/ja active Active
- 2019-11-20 TW TW108142103A patent/TWI735081B/zh active
-
2020
- 2020-03-13 KR KR1020200031592A patent/KR102233532B1/ko active IP Right Grant
- 2020-03-24 CN CN202010212472.9A patent/CN111798899B/zh active Active
- 2020-03-26 US US16/830,983 patent/US11430796B2/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001338993A (ja) * | 2000-03-24 | 2001-12-07 | Toshiba Corp | 半導体装置 |
JP2004303340A (ja) * | 2003-03-31 | 2004-10-28 | Renesas Technology Corp | 半導体記憶装置 |
Also Published As
Publication number | Publication date |
---|---|
CN111798899A (zh) | 2020-10-20 |
CN111798899B (zh) | 2022-06-17 |
US20200321343A1 (en) | 2020-10-08 |
KR20200118364A (ko) | 2020-10-15 |
KR102233532B1 (ko) | 2021-03-30 |
TW202038231A (zh) | 2020-10-16 |
US11430796B2 (en) | 2022-08-30 |
TWI735081B (zh) | 2021-08-01 |
JP6901515B2 (ja) | 2021-07-14 |
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