JP2019535138A5 - - Google Patents

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Publication number
JP2019535138A5
JP2019535138A5 JP2019516495A JP2019516495A JP2019535138A5 JP 2019535138 A5 JP2019535138 A5 JP 2019535138A5 JP 2019516495 A JP2019516495 A JP 2019516495A JP 2019516495 A JP2019516495 A JP 2019516495A JP 2019535138 A5 JP2019535138 A5 JP 2019535138A5
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Japan
Prior art keywords
defect
wafer
embedded
location
positioning system
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JP2019516495A
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Japanese (ja)
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JP2019535138A (ja
JP6918931B2 (ja
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Priority claimed from US15/430,817 external-priority patent/US10082470B2/en
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JP2019516495A 2016-09-27 2017-09-26 半導体ウエハ検査のための欠陥マーキング Active JP6918931B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201662400182P 2016-09-27 2016-09-27
US62/400,182 2016-09-27
US15/430,817 US10082470B2 (en) 2016-09-27 2017-02-13 Defect marking for semiconductor wafer inspection
US15/430,817 2017-02-13
PCT/US2017/053540 WO2018064072A1 (en) 2016-09-27 2017-09-26 Defect marking for semiconductor wafer inspection

Publications (3)

Publication Number Publication Date
JP2019535138A JP2019535138A (ja) 2019-12-05
JP2019535138A5 true JP2019535138A5 (enExample) 2020-11-12
JP6918931B2 JP6918931B2 (ja) 2021-08-11

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JP2019516495A Active JP6918931B2 (ja) 2016-09-27 2017-09-26 半導体ウエハ検査のための欠陥マーキング

Country Status (7)

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US (1) US10082470B2 (enExample)
JP (1) JP6918931B2 (enExample)
KR (1) KR102235580B1 (enExample)
CN (1) CN109690748B (enExample)
SG (1) SG11201900913VA (enExample)
TW (1) TWI722246B (enExample)
WO (1) WO2018064072A1 (enExample)

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CN117197025A (zh) * 2022-05-31 2023-12-08 鸿海精密工业股份有限公司 瑕疵检测方法、电子设备及存储介质
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