JP2019066766A - 半導体装置およびその製造方法 - Google Patents
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 70
- 238000004519 manufacturing process Methods 0.000 title claims description 34
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 238000005468 ion implantation Methods 0.000 claims abstract description 34
- 238000011144 upstream manufacturing Methods 0.000 claims description 8
- 150000002500 ions Chemical class 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 6
- 238000000206 photolithography Methods 0.000 claims description 5
- 239000010410 layer Substances 0.000 description 87
- 229910010271 silicon carbide Inorganic materials 0.000 description 17
- 238000000034 method Methods 0.000 description 16
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 14
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 6
- 238000010586 diagram Methods 0.000 description 5
- 239000011229 interlayer Substances 0.000 description 5
- 238000000059 patterning Methods 0.000 description 5
- 229910052757 nitrogen Inorganic materials 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 230000015556 catabolic process Effects 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 3
- 230000007423 decrease Effects 0.000 description 3
- 239000002019 doping agent Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- -1 Nitrogen ions Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004590 computer program Methods 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 230000001133 acceleration Effects 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000000446 fuel Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 230000001105 regulatory effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1608—Silicon carbide
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
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- H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
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Abstract
Description
本開示の実施形態を説明する前に、本開示の基礎となった知見を説明する。以下、パワー半導体デバイスを半導体装置と称する。
バルク基板と、
前記バルク基板の表面に形成されたエピタキシャル層と、
を備え、
前記バルク基板の前記表面の一部は、少なくとも1つの凹部または凸部によって規定されたアライメントパターンを含むアライメント領域を有し、
前記アライメント領域の少なくとも一部にはイオン注入層が形成されている、
半導体装置。
前記バルク基板に垂直な方向から見たとき、
前記エピタキシャル層は、前記少なくとも1つの凹部または凸部が有する端の一部と重なるファセット面を有する、
項目1に記載の半導体装置。
前記ファセット面は、前記少なくとも1つの凹部または凸部が有する前記端と平行な一対の辺を有し、
前記バルク基板を下とし、前記エピタキシャル層を上とすると、
前記イオン注入層の少なくとも一部は、前記一対の辺のうち、より高い位置にある辺の真下に位置する、
項目2に記載の半導体装置。
前記バルク基板は、オフ基板であり、
前記アライメントパターンは、前記少なくとも1つの凹部によって規定され、
前記少なくとも1つの凹部が有する前記端の一部は、前記オフ基板のオフ方向に垂直であり、かつ、前記オフ方向の下流側に位置する、
項目2または3に記載の半導体装置。
前記バルク基板は、オフ基板であり、
前記アライメントパターンは、前記少なくとも1つの凸部によって規定され、
前記少なくとも1つの凸部が有する前記端の一部は、前記オフ基板のオフ方向に垂直であり、かつ、前記オフ方向の上流側に位置する、
項目2または3に記載の半導体装置。
前記半導体装置はMOS−FETである、
項目1から5のいずれかに記載の半導体装置。
バルク基板を用意する第1の工程と、
前記バルク基板の表面にレジスト膜を形成する第2の工程と、
前記レジスト膜の一部をフォトリソグラフィーによって除去することにより、マスク層を形成する第3の工程と、
前記マスク層を用いて前記バルク基板のエッチングを行うことにより、アライメントパターンを有するアライメント領域を形成する第4の工程と、
前記マスク層を除去する第5の工程と、
前記アライメント領域の少なくとも一部にイオン注入を行う第6の工程と、
を包含する、
半導体装置の製造方法。
前記第6の工程を、MOSFETの製造工程において周辺領域にイオン注入を行う際に、行う、
項目7に記載の半導体装置の製造方法。
以下では、模式図を用いて、本開示を包括的に説明する。本開示の実施形態における半導体装置は、例えば、MOSFET(Metal Oxide Semiconductor Field Effect Transistor)またはショットキーバリアダイオードである。
13 p型ウェル領域
14 ソース領域
15 コンタクト領域
16 エピタキシャル層
16c チャネル層
17 ゲート絶縁膜
18 ゲート電極
19 ソース電極
20 ファセット面
20s 辺
21 アライメントパターン
21a 凹部
21e 凹部の端
22 オフ方向
23a 新たな凹部
23e 新たな凹部の端
25 イオン注入層
31 マスク層
31F レジスト膜
38 層間絶縁膜
39 上部配線電極
40 ドレイン電極
90 ユニットセル
91 アライメント領域
92 周辺領域
93 素子領域
94 周辺領域に隣接する領域
95 スクライブ領域
96 ショット領域
100 半導体装置
200 半導体装置
Claims (8)
- バルク基板と、
前記バルク基板の表面に形成されたエピタキシャル層と、
を備え、
前記バルク基板の前記表面の一部は、少なくとも1つの凹部または凸部によって規定されたアライメントパターンを含むアライメント領域を有し、
前記アライメント領域の少なくとも一部にはイオン注入層が形成されている、
半導体装置。 - 前記バルク基板に垂直な方向から見たとき、
前記エピタキシャル層は、前記少なくとも1つの凹部または凸部が有する端の一部と重なるファセット面を有する、
請求項1に記載の半導体装置。 - 前記ファセット面は、前記少なくとも1つの凹部または凸部が有する前記端と平行な一対の辺を有し、
前記バルク基板を下とし、前記エピタキシャル層を上とすると、
前記イオン注入層の少なくとも一部は、前記一対の辺のうち、より高い位置にある辺の真下に位置する、
請求項2に記載の半導体装置。 - 前記バルク基板は、オフ基板であり、
前記アライメントパターンは、前記少なくとも1つの凹部によって規定され、
前記少なくとも1つの凹部が有する前記端の一部は、前記オフ基板のオフ方向に垂直であり、かつ、前記オフ方向の下流側に位置する、
請求項2または3に記載の半導体装置。 - 前記バルク基板は、オフ基板であり、
前記アライメントパターンは、前記少なくとも1つの凸部によって規定され、
前記少なくとも1つの凸部が有する前記端の一部は、前記オフ基板のオフ方向に垂直であり、かつ、前記オフ方向の上流側に位置する、
請求項2または3に記載の半導体装置。 - 前記半導体装置はMOS−FETである、
請求項1から5のいずれかに記載の半導体装置。 - バルク基板を用意する第1の工程と、
前記バルク基板の表面にレジスト膜を形成する第2の工程と、
前記レジスト膜の一部をフォトリソグラフィーによって除去することにより、マスク層を形成する第3の工程と、
前記マスク層を用いて前記バルク基板のエッチングを行うことにより、アライメントパターンを有するアライメント領域を形成する第4の工程と、
前記マスク層を除去する第5の工程と、
前記アライメント領域の少なくとも一部にイオン注入を行う第6の工程と、
を包含する、
半導体装置の製造方法。 - 前記第6の工程を、MOSFETの製造工程において周辺領域にイオン注入を行う際に、行う、
請求項7に記載の半導体装置の製造方法。
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JP2017194440A JP6975912B2 (ja) | 2017-10-04 | 2017-10-04 | 半導体装置およびその製造方法 |
US16/140,776 US10763331B2 (en) | 2017-10-04 | 2018-09-25 | Semiconductor device including ion implanted alignment marks and method of manufacturing the same |
CN201811135177.7A CN109616464A (zh) | 2017-10-04 | 2018-09-27 | 半导体装置及其制造方法 |
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JPS5939041A (ja) * | 1982-08-27 | 1984-03-03 | Hitachi Ltd | 半導体装置の製造方法 |
JPS6473718A (en) * | 1987-09-16 | 1989-03-20 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
JP2000292905A (ja) * | 1999-04-12 | 2000-10-20 | Hitachi Ltd | パタンデータの作成方法および固体素子の製造方法 |
JP2005019898A (ja) * | 2003-06-27 | 2005-01-20 | Denso Corp | 半導体基板およびその製造方法 |
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US6297108B1 (en) * | 2000-03-10 | 2001-10-02 | United Microelectronics Corp. | Method of forming a high voltage MOS transistor on a semiconductor wafer |
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US7611961B2 (en) * | 2006-12-20 | 2009-11-03 | Macronix International Co., Ltd. | Method for fabricating semiconductor wafer with enhanced alignment performance |
JP5240164B2 (ja) * | 2009-11-09 | 2013-07-17 | 株式会社デンソー | 炭化珪素半導体装置の製造方法 |
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- 2018-09-25 US US16/140,776 patent/US10763331B2/en active Active
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Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5939041A (ja) * | 1982-08-27 | 1984-03-03 | Hitachi Ltd | 半導体装置の製造方法 |
JPS6473718A (en) * | 1987-09-16 | 1989-03-20 | Hitachi Ltd | Manufacture of semiconductor integrated circuit device |
JP2000292905A (ja) * | 1999-04-12 | 2000-10-20 | Hitachi Ltd | パタンデータの作成方法および固体素子の製造方法 |
JP2005019898A (ja) * | 2003-06-27 | 2005-01-20 | Denso Corp | 半導体基板およびその製造方法 |
JP2007280978A (ja) * | 2006-04-03 | 2007-10-25 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JP2008053363A (ja) * | 2006-08-23 | 2008-03-06 | Matsushita Electric Ind Co Ltd | 半導体基板およびその製造方法 |
WO2012028109A1 (en) * | 2010-09-01 | 2012-03-08 | Csmc Technologies Fab1 Co., Ltd. | Semicondunctor device and method of fabricating the same |
JP2013232565A (ja) * | 2012-04-27 | 2013-11-14 | National Institute Of Advanced Industrial & Technology | 炭化珪素半導体素子の製造方法 |
CN105047547A (zh) * | 2015-07-08 | 2015-11-11 | 泰科天润半导体科技(北京)有限公司 | 一种用于碳化硅器件的对准标记及其制备方法 |
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US20190103463A1 (en) | 2019-04-04 |
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