JP2019046916A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 35
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- 238000004519 manufacturing process Methods 0.000 description 31
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 17
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- 150000004706 metal oxides Chemical class 0.000 description 4
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- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 4
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41741—Source or drain electrodes for field effect devices for vertical or pseudo-vertical devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/4234—Gate electrodes for transistors with charge trapping gate insulator
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
Abstract
Description
図2は、メモリセルアレイ1の模式平面図である。
図3は、図2におけるA−A’断面図である。
破線は、リンドープシリコン(リン濃度1020atoms/cm-3程)から成長するシリコンのインキュベーションタイムを表す。
実線は、アンドープシリコンから成長するシリコンのインキュベーションタイムを表す。
図26は、図25におけるB−B’断面図である。
Claims (5)
- ドーパントを含む半導体層を有するソース層と、
前記ソース層上に設けられ、絶縁体を介して積層された複数の電極層を有する積層体と、
前記積層体内を前記積層体の積層方向に延び、前記積層体を複数のブロックに分離する複数の分離部と、
前記複数の分離部の間のエリアに配置された複数の柱状部であって、前記積層体内および前記半導体層内を前記積層方向に延び、前記半導体層に接する側壁部を有する複数の半導体ボディを有する複数の柱状部と、
前記複数の柱状部の間のエリアで前記柱状部に離間して前記半導体層中に設けられ、前記分離部と前記柱状部との間のエリアにおける前記半導体層中には設けられていないドーパント拡散防止膜と、
を備えた半導体装置。 - 前記ドーパント拡散防止膜は、前記積層方向に対して直交する面方向に広がり、前記柱状部の周囲を囲んでいる請求項1記載の半導体装置。
- 前記柱状部は、前記半導体ボディの側面に設けられた絶縁膜を有し、
前記絶縁膜は、前記半導体ボディの前記側壁部と前記半導体層とが接する部分で前記積層方向に分断され、
前記ドーパント拡散防止膜は、前記絶縁膜が分断された部分の側方に位置する請求項2記載の半導体装置。 - 前記半導体層は、
前記柱状部の下端部を囲む第1半導体層と、
前記ドーパント拡散防止膜を介して、前記第1半導体層上に設けられた半導体部と、
を有する請求項2記載の半導体装置。 - 前記半導体部のドーパント濃度は、前記第1半導体層のドーパント濃度よりも低い請求項4記載の半導体装置。
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JP2017167063A JP6842386B2 (ja) | 2017-08-31 | 2017-08-31 | 半導体装置 |
US15/915,601 US10411028B2 (en) | 2017-08-31 | 2018-03-08 | Semiconductor device and method for manufacturing same |
US16/516,830 US10490565B1 (en) | 2017-08-31 | 2019-07-19 | Semiconductor device and method for manufacturing same |
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JP2017167063A JP6842386B2 (ja) | 2017-08-31 | 2017-08-31 | 半導体装置 |
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JP6842386B2 JP6842386B2 (ja) | 2021-03-17 |
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JP (1) | JP6842386B2 (ja) |
Cited By (2)
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JP2022529571A (ja) * | 2020-03-20 | 2022-06-23 | 長江存儲科技有限責任公司 | 三次元メモリデバイス及びその動作方法 |
JP7333464B2 (ja) | 2019-08-26 | 2023-08-24 | マイクロン テクノロジー,インク. | 集積アセンブリ及び集積アセンブリを形成する方法 |
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