JP7417387B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP7417387B2 JP7417387B2 JP2019162305A JP2019162305A JP7417387B2 JP 7417387 B2 JP7417387 B2 JP 7417387B2 JP 2019162305 A JP2019162305 A JP 2019162305A JP 2019162305 A JP2019162305 A JP 2019162305A JP 7417387 B2 JP7417387 B2 JP 7417387B2
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- 239000004065 semiconductor Substances 0.000 title claims description 106
- 238000004519 manufacturing process Methods 0.000 title claims description 13
- 239000000758 substrate Substances 0.000 claims description 32
- 229910052796 boron Inorganic materials 0.000 claims description 31
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 30
- 238000005530 etching Methods 0.000 claims description 18
- 238000000034 method Methods 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 5
- 230000015572 biosynthetic process Effects 0.000 claims description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 16
- 229910052710 silicon Inorganic materials 0.000 description 16
- 239000010703 silicon Substances 0.000 description 16
- 230000004048 modification Effects 0.000 description 13
- 238000012986 modification Methods 0.000 description 13
- 239000013078 crystal Substances 0.000 description 12
- 238000003860 storage Methods 0.000 description 9
- 239000007789 gas Substances 0.000 description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 6
- 229910052814 silicon oxide Inorganic materials 0.000 description 6
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 description 5
- 230000000052 comparative effect Effects 0.000 description 5
- 230000006870 function Effects 0.000 description 5
- 229910000041 hydrogen chloride Inorganic materials 0.000 description 4
- IXCSERBJSXMMFS-UHFFFAOYSA-N hydrogen chloride Substances Cl.Cl IXCSERBJSXMMFS-UHFFFAOYSA-N 0.000 description 4
- 238000001020 plasma etching Methods 0.000 description 4
- 229910052581 Si3N4 Inorganic materials 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000000926 separation method Methods 0.000 description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 3
- 239000011800 void material Substances 0.000 description 3
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000000460 chlorine Substances 0.000 description 2
- MROCJMGDEKINLD-UHFFFAOYSA-N dichlorosilane Chemical compound Cl[SiH2]Cl MROCJMGDEKINLD-UHFFFAOYSA-N 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 2
- 229910052721 tungsten Inorganic materials 0.000 description 2
- 239000010937 tungsten Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910021417 amorphous silicon Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 150000001638 boron Chemical class 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
- H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B43/00—EEPROM devices comprising charge-trapping gate insulators
- H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
図1は、第1実施形態に係るメモリセルアレイ1の斜視図である。図2は、図1に示すメモリセルアレイ1の平面図である。図3は、図2に示す切断線A-A’に沿った断面図である。各図において、半導体基板10の上面10a(第1面)に平行な方向であって相互に直交する2方向をX方向およびY方向(第2方向)とする。また、上面10aに垂直な方向であって、X方向およびY方向に対して直交する方向をZ方向(第1方向)とする。
図18は、変形例1に係るメモリセルアレイの要部の構造を示す断面図である。上述した第1実施形態と同様の構成要素には同じ符号を付し、詳細な説明を省略する。
図19は、変形例2に係るメモリセルアレイの要部の構造を示す断面図である。上述した第1実施形態と同様の構成要素には同じ符号を付し、詳細な説明を省略する。
Claims (1)
- 半導体基板の第1面上に、絶縁層と犠牲層とが前記第1面に垂直な第1方向に交互に積層された積層体を形成し、
前記積層体を前記第1方向に貫通し、前記第1面よりも深い位置まで到達するホールを形成し、
前記第1面よりも下方の前記ホールの第1部分を異方性エッチングすることによって、前記第1部分の前記第1面に平行な第2方向の長さを、前記ホールの前記第1面よりも上方の第2部分の前記第2方向の長さよりも長くし、
前記第1部分で前記半導体基板と同じ半導体材料を結晶成長させた第1コンタクト部と、前記第2部分で前記半導体材料を結晶成長させた第2コンタクト部と、を形成し、
前記ホール内の前記第2コンタクト部上に半導体膜を形成する、
半導体装置の製造方法であって、
前記第1コンタクト部は、ボロンを含み、
前記第2コンタクト部は、前記ボロンを含むドープ層と、前記ドープ層上に設けられ、前記ボロンを含まないアンドープ層と、を有し、
前記ホールの第1部分の異方性エッチングと、前記第1コンタクト部及び前記第2コンタクト部の形成と、は装置内で連続して行われる、半導体装置の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2019162305A JP7417387B2 (ja) | 2019-09-05 | 2019-09-05 | 半導体装置の製造方法 |
TW109103262A TWI786367B (zh) | 2019-09-05 | 2020-02-03 | 半導體裝置及其製造方法 |
CN202010091190.8A CN112447755B (zh) | 2019-09-05 | 2020-02-13 | 半导体装置及其制造方法 |
US16/811,065 US11075122B2 (en) | 2019-09-05 | 2020-03-06 | Semiconductor device and manufacturing method thereof |
Applications Claiming Priority (1)
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JP2019162305A JP7417387B2 (ja) | 2019-09-05 | 2019-09-05 | 半導体装置の製造方法 |
Publications (2)
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JP2021040108A JP2021040108A (ja) | 2021-03-11 |
JP7417387B2 true JP7417387B2 (ja) | 2024-01-18 |
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JP2019162305A Active JP7417387B2 (ja) | 2019-09-05 | 2019-09-05 | 半導体装置の製造方法 |
Country Status (4)
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US (1) | US11075122B2 (ja) |
JP (1) | JP7417387B2 (ja) |
CN (1) | CN112447755B (ja) |
TW (1) | TWI786367B (ja) |
Families Citing this family (2)
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JP2021150605A (ja) * | 2020-03-23 | 2021-09-27 | キオクシア株式会社 | 半導体記憶装置及びその製造方法 |
JP2023032792A (ja) * | 2021-08-27 | 2023-03-09 | キオクシア株式会社 | 半導体記憶装置、および半導体記憶装置の製造方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20170358597A1 (en) | 2016-05-04 | 2017-12-14 | Byoung Il Lee | Semiconductor device |
US20180122822A1 (en) | 2016-11-01 | 2018-05-03 | Joon-Suk Lee | Vertical memory devices and methods of manufacturing the same |
US10115730B1 (en) | 2017-06-19 | 2018-10-30 | Sandisk Technologies Llc | Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making thereof |
JP2019041056A (ja) | 2017-08-28 | 2019-03-14 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
Family Cites Families (14)
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JP2012074542A (ja) * | 2010-09-29 | 2012-04-12 | Hitachi Ltd | 不揮発性記憶装置およびその製造方法 |
KR101774508B1 (ko) * | 2010-10-18 | 2017-09-04 | 삼성전자주식회사 | 3차원 반도체 메모리 장치 및 그 제조 방법 |
KR102054226B1 (ko) * | 2013-03-14 | 2019-12-10 | 삼성전자주식회사 | 반도체 소자 및 그 제조 방법 |
KR102240024B1 (ko) * | 2014-08-22 | 2021-04-15 | 삼성전자주식회사 | 반도체 장치, 반도체 장치의 제조방법 및 에피택시얼층의 형성방법 |
US20170069653A1 (en) * | 2015-09-09 | 2017-03-09 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing the same |
US20170069657A1 (en) | 2015-09-09 | 2017-03-09 | Kabushiki Kaisha Toshiba | Semiconductor memory device and method for manufacturing the same |
US9887273B2 (en) | 2016-03-31 | 2018-02-06 | Toshiba Memory Corporation | Semiconductor memory device |
KR102532201B1 (ko) * | 2016-07-22 | 2023-05-12 | 삼성전자 주식회사 | 메모리 소자 |
US9842849B1 (en) * | 2016-09-16 | 2017-12-12 | Toshiba Memory Corporation | Semiconductor memory device and method for manufacturing the same |
JP2018160612A (ja) | 2017-03-23 | 2018-10-11 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
US10290645B2 (en) * | 2017-06-30 | 2019-05-14 | Sandisk Technologies Llc | Three-dimensional memory device containing hydrogen diffusion barrier layer for CMOS under array architecture and method of making thereof |
US10453855B2 (en) * | 2017-08-11 | 2019-10-22 | Micron Technology, Inc. | Void formation in charge trap structures |
US10103169B1 (en) * | 2017-08-21 | 2018-10-16 | Sandisk Technologies Llc | Method of making a three-dimensional memory device using a multi-step hot phosphoric acid wet etch process |
US10269820B1 (en) * | 2018-04-03 | 2019-04-23 | Sandisk Technologies Llc | Three-dimensional memory device containing different pedestal width support pillar structures and method of making the same |
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2019
- 2019-09-05 JP JP2019162305A patent/JP7417387B2/ja active Active
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2020
- 2020-02-03 TW TW109103262A patent/TWI786367B/zh active
- 2020-02-13 CN CN202010091190.8A patent/CN112447755B/zh active Active
- 2020-03-06 US US16/811,065 patent/US11075122B2/en active Active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US20170358597A1 (en) | 2016-05-04 | 2017-12-14 | Byoung Il Lee | Semiconductor device |
US20180122822A1 (en) | 2016-11-01 | 2018-05-03 | Joon-Suk Lee | Vertical memory devices and methods of manufacturing the same |
US10115730B1 (en) | 2017-06-19 | 2018-10-30 | Sandisk Technologies Llc | Three-dimensional memory device containing structurally reinforced pedestal channel portions and method of making thereof |
JP2019041056A (ja) | 2017-08-28 | 2019-03-14 | 東芝メモリ株式会社 | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
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JP2021040108A (ja) | 2021-03-11 |
CN112447755B (zh) | 2024-02-02 |
TWI786367B (zh) | 2022-12-11 |
CN112447755A (zh) | 2021-03-05 |
TW202111931A (zh) | 2021-03-16 |
US20210074592A1 (en) | 2021-03-11 |
US11075122B2 (en) | 2021-07-27 |
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