JP2018507563A - 3D FinFET構造体を有するスプリットゲート不揮発性メモリセル及びその製造方法 - Google Patents
3D FinFET構造体を有するスプリットゲート不揮発性メモリセル及びその製造方法 Download PDFInfo
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Abstract
Description
本出願は、2015年3月17日に出願された米国仮出願第62/134,489号の利益を主張する。上記仮出願は、参照により本明細書に組み込まれる。
Claims (15)
- 不揮発性メモリセルであって、
上面及び2つの側面を有するフィン形上面部分を有する第1の導電型の半導体基板と、
前記フィン形上面部分内にある前記第1の導電型とは異なる第2の導電型の離間配置された第1の領域及び第2の領域であって、前記第1の領域と前記第2の領域との間に延在するチャネル領域を有し、
前記チャネル領域が、前記上面の第1の部分及び前記2つの側面の第1の部分を含む第1の部分を有し、かつ前記上面の第2の部分及び前記2つの側面の第2の部分を含む第2の部分を有する、第1の領域及び第2の領域と、
導電性浮遊ゲートであって、
前記上面の前記第1の部分に沿って延在し、それから絶縁された第1の部分、
前記2つの側面の一方の前記第1の部分に沿って延在し、それから絶縁された第2の部分、及び
前記2つの側面の他方の前記第1の部分に沿って延在し、それから絶縁された第3の部分を含む、導電性浮遊ゲートと、
導電性制御ゲートであって、
前記上面の前記第2の部分に沿って延在し、それから絶縁された第1の部分、
前記2つの側面の一方の前記第2の部分に沿って延在し、それから絶縁された第2の部分、
前記2つの側面の他方の前記第2の部分に沿って延在し、それから絶縁された第3の部分、
前記浮遊ゲートの第1の部分の少なくとも一部の上方かつそれ上に延在し、それから絶縁された第4の部分、
前記浮遊ゲートの第2の部分の少なくとも一部の外側かつそれ上に延在し、それから絶縁された第5の部分、及び
前記浮遊ゲートの第3の部分の少なくとも一部の外側かつそれ上に延在し、それから絶縁された第6の部分を含む、導電性制御ゲートと、を備えた、不揮発性メモリセル。 - 前記浮遊ゲートが、前記制御ゲートに面し、それから絶縁された鋭角縁部で終端する傾斜状の上面を含む、請求項1に記載の不揮発性メモリセル。
- 前記チャネル領域の第1の部分が、前記第1の領域に隣接し、前記チャネル領域の第2の部分が、前記第2の領域に隣接している、請求項1に記載の不揮発性メモリセル。
- 前記浮遊ゲートが、部分的に前記第1の領域の上に延在する、請求項3に記載の不揮発性メモリセル。
- 不揮発性メモリアレイであって、
第1の方向に延在し、各々が上面及び2つの側面を有する複数の平行するフィン形上面部分を有する第1の導電型の半導体基板と、
前記フィン形上面部分の各々上に形成された複数のメモリセルであって、各メモリセルが、
前記1つのフィン形上面部分内にある前記第1の導電型とは異なる第2の導電型の離間配置された第1の領域及び第2の領域であって、前記第1の領域と前記第2の領域との間に延在するチャネル領域を有し、
前記チャネル領域が、前記上面の第1の部分及び前記2つの側面の第1の部分を含む第1の部分を有し、かつ前記上面の第2の部分及び前記2つの側面の第2の部分を含む第2の部分を有する、離間配置された第1の領域及び第2の領域、
導電性浮遊ゲートであって、
前記上面の前記第1の部分に沿って延在し、それから絶縁された第1の部分、
前記2つの側面の一方の前記第1の部分に沿って延在し、それから絶縁された第2の部分、及び
前記2つの側面の他方の前記第1の部分に沿って延在し、それから絶縁された第3の部分を含む、導電性浮遊ゲート、並びに
導電性制御ゲートであって、
前記上面の前記第2の部分に沿って延在し、それから絶縁された第1の部分、
前記2つの側面の一方の前記第2の部分に沿って延在し、それから絶縁された第2の部分、
前記2つの側面の他方の前記第2の部分に沿って延在し、それから絶縁された第3の部分、
前記浮遊ゲートの第1の部分の少なくとも一部の上方かつそれ上に延在し、それから絶縁された第4の部分、
前記浮遊ゲートの第2の部分の少なくとも一部の外側かつそれ上に延在し、それから絶縁された第5の部分、及び
前記浮遊ゲートの第3の部分の少なくとも一部の外側かつそれ上に延在し、それから絶縁された第6の部分を含む、導電性制御ゲートを含む、複数のメモリセルと、
各々が前記第1の方向に対して垂直な第2の方向に延在し、前記フィン形上面部分の各々のための前記制御ゲートの1つに電気的に接続された、複数の制御ゲート線と、を備えた、不揮発性メモリアレイ。 - 前記第2の方向に延在する前記基板内の複数の平行する拡散線であって、各拡散線が、前記フィン形上面部分内の各々の前記第1の領域のうちの2つに電気的に接続された、複数の平行する拡散線を更に備えた、請求項5に記載の不揮発性メモリアレイ。
- 各々が前記第1の領域のうちの2つから延在し、それらに電気的に接続された、複数のコンタクトと、
前記第2の方向に延在し、前記フィン形上面部分の各々のための前記複数のコンタクトのうちの1つに電気的に接続された、複数のソース線と、を更に備えた、請求項5に記載の不揮発性メモリアレイ。 - 前記浮遊ゲートの各々が、前記制御ゲートのうちの1つに面し、それから絶縁された鋭角縁部で終端する傾斜状の上面を含む、請求項5に記載の不揮発性メモリセル。
- 前記チャネル領域の第1の部分の各々が、前記第1の領域のうちの1つに隣接し、前記チャネル領域の第2の部分の各々が、前記第2の領域のうちの1つに隣接している、請求項5に記載の不揮発性メモリセル。
- 前記浮遊ゲートの各々が、前記第1の領域のうちの1つの上に部分的に延在する、請求項9に記載の不揮発性メモリセル。
- 不揮発性メモリセルを形成する方法であって、
第1の導電型の半導体基板の表面内に1対の平行するトレンチを形成し、前記トレンチの間に、上面及び2つの側面を有するフィン形上面部分を生じさせることと、
前記上面及び前記2つの側面に沿って絶縁材料を形成することと、
前記フィン形上面部分内にある前記第1の導電型とは異なる第2の導電型の離間配置された第1の領域及び第2の領域を形成することであって、前記離間配置された第1の領域及び第2の領域が、前記第1の領域と前記第2の領域との間に延在するチャネル領域を有し、
前記チャネル領域が、前記上面の第1の部分及び前記2つの側面の第1の部分を含む第1の部分を有し、かつ前記上面の第2の部分及び前記2つの側面の第2の部分を含む第2の部分を有する、形成することと、
導電性浮遊ゲートを形成することであって、前記導電性浮遊ゲートが、
前記上面の前記第1の部分に沿って延在し、それから絶縁された第1の部分、
前記2つの側面の一方の前記第1の部分に沿って延在し、それから絶縁された第2の部分、及び
前記2つの側面の他方の前記第1の部分に沿って延在し、それから絶縁された第3の部分を含む、形成することと、
導電性制御ゲートを形成することであって、前記導電性制御ゲートが、
前記上面の前記第2の部分に沿って延在し、それから絶縁された第1の部分、
前記2つの側面の一方の前記第2の部分に沿って延在し、それから絶縁された第2の部分、
前記2つの側面の他方の前記第2の部分に沿って延在し、それから絶縁された第3の部分、
前記浮遊ゲートの第1の部分の少なくとも一部の上方かつそれ上に延在し、それから絶縁された第4の部分、
前記浮遊ゲートの第2の部分の少なくとも一部の外側かつそれ上に延在し、それから絶縁された第5の部分、及び
前記浮遊ゲートの第3の部分の少なくとも一部の外側かつそれ上に延在し、それから絶縁された第6の部分を含む、形成することと、を含む方法。 - 前記1対のトレンチの前記形成が、
前記基板の前記表面の上に材料のブロックを形成することと、
前記材料のブロックに隣接する前記基板の部分をエッチングし、前記材料のブロックの下に前記フィン形上面部分を残すことと、を含む、請求項11に記載の方法。 - 前記材料のブロックの前記形成が、
前記基板の前記表面の上に材料の層を形成することと、
前記材料の層の上に第2の材料のブロックを形成することと、
前記材料の層の上に、かつ前記第2の材料のブロックの側面に沿って、材料のスペーサを形成することと、
前記第2の材料のブロックを除去することと、
前記材料のスペーサに隣接する前記材料の層の部分をエッチングし、前記材料のスペーサの下に前記材料のブロックを残すことと、を含む、請求項12に記載の方法。 - 前記材料のブロックの前記形成が、
前記基板の前記表面の上に材料の層を形成することと、
前記材料の層の上にフォトレジストを形成することと、
フォトリソグラフィ露光及びエッチングを行って前記フォトレジストの部分を選択的に除去し、前記材料の層の上に前記フォトレジストのブロックを残すことと、
前記フォトレジストのブロックに隣接する前記材料の層の部分をエッチングし、前記フォトレジストのブロックの下に前記材料のブロックを残すことと、を含む、請求項12に記載の方法。 - 前記浮遊ゲートの上面が傾斜状になり、前記制御ゲートに面し、それから絶縁された鋭角縁部で終端するように、前記浮遊ゲートの前記上面を酸化させ、酸化ポリシリコンを形成することを更に含む、請求項11に記載の方法。
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