JP2018506897A - より良い信号品質に関する新規な高速信号ルーティングトポロジ - Google Patents

より良い信号品質に関する新規な高速信号ルーティングトポロジ Download PDF

Info

Publication number
JP2018506897A
JP2018506897A JP2017536590A JP2017536590A JP2018506897A JP 2018506897 A JP2018506897 A JP 2018506897A JP 2017536590 A JP2017536590 A JP 2017536590A JP 2017536590 A JP2017536590 A JP 2017536590A JP 2018506897 A JP2018506897 A JP 2018506897A
Authority
JP
Japan
Prior art keywords
signal
transmission line
length
chip
pcb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
JP2017536590A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018506897A5 (enExample
Inventor
スブラマニアン、ヨケシュ
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of JP2018506897A publication Critical patent/JP2018506897A/ja
Publication of JP2018506897A5 publication Critical patent/JP2018506897A5/ja
Ceased legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0243—Printed circuits associated with mounted high frequency components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0246—Termination of transmission lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/0248—Skew reduction or using delay lines
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09227—Layout details of a plurality of traces, e.g. escape layout for Ball Grid Array [BGA] mounting
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09218—Conductive traces
    • H05K2201/09254—Branched layout

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Logic Circuits (AREA)
  • Dc Digital Transmission (AREA)
  • Structure Of Printed Boards (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
JP2017536590A 2015-01-12 2016-01-11 より良い信号品質に関する新規な高速信号ルーティングトポロジ Ceased JP2018506897A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/595,175 US9980366B2 (en) 2015-01-12 2015-01-12 High speed signal routing topology for better signal quality
US14/595,175 2015-01-12
PCT/US2016/012912 WO2016115056A2 (en) 2015-01-12 2016-01-11 A novel high speed signal routing topology for better signal quality

Publications (2)

Publication Number Publication Date
JP2018506897A true JP2018506897A (ja) 2018-03-08
JP2018506897A5 JP2018506897A5 (enExample) 2018-07-19

Family

ID=55361943

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017536590A Ceased JP2018506897A (ja) 2015-01-12 2016-01-11 より良い信号品質に関する新規な高速信号ルーティングトポロジ

Country Status (6)

Country Link
US (2) US9980366B2 (enExample)
EP (1) EP3245853B1 (enExample)
JP (1) JP2018506897A (enExample)
KR (1) KR20170105493A (enExample)
CN (1) CN107112040B (enExample)
WO (1) WO2016115056A2 (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9980366B2 (en) 2015-01-12 2018-05-22 Qualcomm Incorporated High speed signal routing topology for better signal quality
US10718851B2 (en) * 2016-02-02 2020-07-21 Qualcomm Incorporated Displacement and rotation measurement for unmanned aerial vehicles
KR102640968B1 (ko) 2018-05-29 2024-02-27 삼성전자주식회사 인쇄 회로 기판, 스토리지 장치, 및 인쇄 회로 기판을 포함하는 스토리지 장치
KR20220066445A (ko) 2020-11-16 2022-05-24 삼성전자주식회사 모듈 보드 및 이를 포함하는 메모리 모듈
CN113316319B (zh) * 2021-05-08 2022-11-11 珠海全志科技股份有限公司 智能设备、可读存储介质、印刷电路板及其使用方法
KR20230000483A (ko) * 2021-06-24 2023-01-03 삼성전자주식회사 전자 장치, 및 인쇄 회로 기판을 포함하는 전자 장치
KR20230009732A (ko) 2021-07-09 2023-01-17 삼성전자주식회사 균형 배선 구조를 갖는 반도체 패키지

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001084070A (ja) * 1999-09-10 2001-03-30 Toshiba Corp プリント配線基板及び電子機器のプリント配線基板
JP2004062530A (ja) * 2002-07-29 2004-02-26 Elpida Memory Inc メモリモジュール及びメモリシステム
US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US20100060318A1 (en) * 2008-09-04 2010-03-11 Peter Flamm Printed circuit board having a termination of a T-shaped signal line
US20110176345A1 (en) * 2010-01-15 2011-07-21 Mediatek Inc. Electronic apparatus

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2631169B1 (fr) 1988-05-04 1990-07-13 Cit Alcatel Dispositif de distribution de signaux numeriques a tres hauts debits
JP3957237B2 (ja) 1998-01-19 2007-08-15 富士通株式会社 集積回路装置モジュール
US6545875B1 (en) * 2000-05-10 2003-04-08 Rambus, Inc. Multiple channel modules and bus systems using same
US6573757B1 (en) 2000-09-11 2003-06-03 Cypress Semiconductor Corp. Signal line matching technique for ICS/PCBS
JP3808335B2 (ja) 2001-07-26 2006-08-09 エルピーダメモリ株式会社 メモリモジュール
JP4094370B2 (ja) 2002-07-31 2008-06-04 エルピーダメモリ株式会社 メモリモジュール及びメモリシステム
JP2004254155A (ja) * 2003-02-21 2004-09-09 Kanji Otsuka 信号伝送装置および配線構造
US6947304B1 (en) 2003-05-12 2005-09-20 Pericon Semiconductor Corp. DDR memory modules with input buffers driving split traces with trace-impedance matching at trace junctions
US7535321B1 (en) 2006-01-17 2009-05-19 Xilinx, Inc. Method and apparatus for a printed circuit board (PCB) embedded filter
KR100689967B1 (ko) 2006-02-03 2007-03-08 삼성전자주식회사 개선된 멀티 모듈 메모리 버스 구조를 가진 메모리 시스템
JP5696301B2 (ja) 2007-09-28 2015-04-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． アドレス線配線構造及びこれを有するプリント配線基板
US8933718B2 (en) * 2008-09-19 2015-01-13 Advantest (Singapore) Pte Ltd Signal distribution structure and method for distributing a signal
CN103812497B (zh) * 2012-11-06 2017-02-15 珠海全志科技股份有限公司 驱动器及低抖动串行信号的输出方法
CN103093064A (zh) * 2013-02-19 2013-05-08 浪潮电子信息产业股份有限公司 一种pcb高速信号线轨迹控制方法
US9253875B2 (en) * 2013-05-15 2016-02-02 Intel IP Corporation Isolating differential transmission lines
US9980366B2 (en) 2015-01-12 2018-05-22 Qualcomm Incorporated High speed signal routing topology for better signal quality

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001084070A (ja) * 1999-09-10 2001-03-30 Toshiba Corp プリント配線基板及び電子機器のプリント配線基板
JP2004062530A (ja) * 2002-07-29 2004-02-26 Elpida Memory Inc メモリモジュール及びメモリシステム
US7245145B2 (en) * 2003-06-11 2007-07-17 Micron Technology, Inc. Memory module and method having improved signal routing topology
US20100060318A1 (en) * 2008-09-04 2010-03-11 Peter Flamm Printed circuit board having a termination of a T-shaped signal line
US20110176345A1 (en) * 2010-01-15 2011-07-21 Mediatek Inc. Electronic apparatus

Also Published As

Publication number Publication date
EP3245853B1 (en) 2018-09-26
KR20170105493A (ko) 2017-09-19
WO2016115056A2 (en) 2016-07-21
WO2016115056A3 (en) 2016-09-09
CN107112040A (zh) 2017-08-29
EP3245853A2 (en) 2017-11-22
US20180220524A1 (en) 2018-08-02
US9980366B2 (en) 2018-05-22
US20160205767A1 (en) 2016-07-14
US10039183B1 (en) 2018-07-31
CN107112040B (zh) 2020-10-30

Similar Documents

Publication Publication Date Title
JP2018506897A (ja) より良い信号品質に関する新規な高速信号ルーティングトポロジ
US8134239B2 (en) Address line wiring structure and printed wiring board having same
JP5703206B2 (ja) 半導体装置、信号伝送システム及び信号伝送方法
US20110187399A1 (en) Signal distribution structure and method for distributing a signal
WO2022110950A1 (zh) 显示面板和显示装置
US6104629A (en) High frequency memory module
JP2016005155A (ja) プリント回路板及びプリント配線板
JP2004062530A (ja) メモリモジュール及びメモリシステム
US7746195B2 (en) Circuit topology for multiple loads
US20090146759A1 (en) Circuit topology for multiple loads
US20080116994A1 (en) Circuit topology for multiple loads
US20130048352A1 (en) Printed circuit board
US6417688B1 (en) Method and apparatus for implementing a highly robust, fast, and economical five load bus topology based on bit mirroring and a well terminated transmission environment
JP3546613B2 (ja) 回路基板
JP2002297274A (ja) コンピュータシステム、このシステムにおいて使用される拡張ボード及びコネクタ
JP5305717B2 (ja) マルチポイント接続信号伝送回路
US9536604B1 (en) Impedance matching system for DDR memory
JP4522056B2 (ja) 整合のとれた応答を生じる４ドロップ・バス
US20060132577A1 (en) Circuit topology for high-speed printed circuit board
CN107037902B (zh) 线路布局结构
CN118234129B (zh) Ddr拓扑结构及pcb板
US9160048B2 (en) Electronic device with terminal circuits
JP2016031627A (ja) メモリシステムの終端回路
TWI358974B (en) Topology layout structure of multiple loads
JP2002312087A (ja) バスシステム、プリント配線基板および電子装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20170915

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20180606

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20180606

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20180606

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20180618

A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20180904

A045 Written measure of dismissal of application [lapsed due to lack of payment]

Free format text: JAPANESE INTERMEDIATE CODE: A045

Effective date: 20190129