WO2022110950A1 - 显示面板和显示装置 - Google Patents

显示面板和显示装置 Download PDF

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Publication number
WO2022110950A1
WO2022110950A1 PCT/CN2021/115583 CN2021115583W WO2022110950A1 WO 2022110950 A1 WO2022110950 A1 WO 2022110950A1 CN 2021115583 W CN2021115583 W CN 2021115583W WO 2022110950 A1 WO2022110950 A1 WO 2022110950A1
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WIPO (PCT)
Prior art keywords
display panel
controlled
path
module
signal
Prior art date
Application number
PCT/CN2021/115583
Other languages
English (en)
French (fr)
Inventor
鲁建军
盖翠丽
Original Assignee
云谷(固安)科技有限公司
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Application filed by 云谷(固安)科技有限公司 filed Critical 云谷(固安)科技有限公司
Priority to KR1020237011110A priority Critical patent/KR20230060525A/ko
Publication of WO2022110950A1 publication Critical patent/WO2022110950A1/zh
Priority to US18/170,180 priority patent/US20230196993A1/en

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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
    • G09G3/3208Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
    • G09G3/3266Details of drivers for scan electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611Control of matrices with row and column drivers
    • G09G3/3674Details of drivers for scan electrodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10KORGANIC ELECTRIC SOLID-STATE DEVICES
    • H10K59/00Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
    • H10K59/10OLED displays
    • H10K59/12Active-matrix OLED [AMOLED] displays
    • H10K59/131Interconnections, e.g. wiring lines or terminals
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00Aspects of the constitution of display devices
    • G09G2300/08Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809Several active elements per pixel in active matrix panels
    • G09G2300/0819Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0202Addressing of scan or signal lines
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0267Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00Command of the display device
    • G09G2310/02Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264Details of driving circuits
    • G09G2310/0286Details of a shift registers arranged for use in a driving circuit
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0223Compensation for problems related to R-C delay and attenuation in electrodes of matrix panels, e.g. in gate electrodes or on-substrate video signal electrodes
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00Control of display operating conditions
    • G09G2320/02Improving the quality of display appearance
    • G09G2320/0233Improving the luminance or brightness uniformity across the screen

Definitions

  • the embodiments of the present application relate to the field of display technologies, for example, to a display panel and a display device.
  • the display quality of the display panel is always one of the important indicators for consumers and panel manufacturers to measure the quality of the display panel.
  • the display panel may have uneven display, which affects the improvement of the display quality of the display panel.
  • Embodiments of the present application provide a display panel and a display device, so as to improve the working condition of uneven display and improve the display image quality.
  • Embodiments of the present application provide a display panel, including:
  • a controlled module
  • the signal wiring includes a first path wiring part and a second path wiring part; the first end of the first path wiring part and the first end of the second path wiring part are configured to be connected to each other. input the same driving signal;
  • the first path routing part is set to transmit the driving signal to the at least two controlled modules in a first preset order; the second path routing part is set to sequentially follow a second preset order.
  • the at least two controlled modules transmit the drive signal; the first preset sequence and the second preset sequence are different.
  • the present application also provides a display device, including: the display panel according to any embodiment of the present application.
  • the signal wiring connecting the controlled module and the driving module includes a first path wiring part and a second path wiring part; the first path wiring part is directed to the at least two controlled The module transmits the drive signal, and the second path routing portion transmits the drive signal in the same order as the first preset sequence to the at least two controlled modules in a second preset sequence, and the first preset sequence is different from the second preset sequence.
  • the RC delay of the driving signal received by the controlled module located at the far end is reduced by arranging the second path routing portion, thereby reducing the reception of the controlled module located at the far end and the controlled module located at the near end.
  • the difference in characteristics such as Tr/Tf of the resulting driving signal, thereby reducing the difference in the charging time of the pixel circuit and improving the display uniformity.
  • FIG. 1 is a schematic structural diagram of a display panel in the related art
  • FIG. 2 is a schematic structural diagram of an area A1 in the display panel shown in FIG. 1;
  • FIG. 3 is a schematic structural diagram of a display panel according to an embodiment of the present application.
  • FIG. 4 is a schematic structural diagram of the area A2 in the display panel shown in FIG. 3;
  • FIG. 5 is another schematic structural diagram of the area A2 in the display panel shown in FIG. 3;
  • FIG. 6 is another structural schematic diagram of the area A2 in the display panel shown in FIG. 3;
  • FIG. 7 is another schematic structural diagram of the area A2 in the display panel shown in FIG. 3;
  • FIG. 8 is another structural schematic diagram of the area A2 in the display panel shown in FIG. 3;
  • FIG. 9 is another structural schematic diagram of the area A2 in the display panel shown in FIG. 3;
  • FIG. 10 is another structural schematic diagram of the area A2 in the display panel shown in FIG. 3;
  • FIG. 11 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • FIG. 12 is a schematic structural diagram of another display panel provided by an embodiment of the present application.
  • FIG. 13 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • the display panel in the related art may exhibit uneven display.
  • the applicant has found that the reason for the uneven display is that there is RC delay (RC loading) in the transmission process of the signal line. analyse as below:
  • FIG. 1 is a schematic structural diagram of a display panel in the related art
  • FIG. 2 is a structural schematic diagram of an area A1 in the display panel shown in FIG. 1 . 1 and 2
  • the display panel includes a display area 110 and a non-display area 120
  • pixel units 111 arranged in an array are arranged in the display area 110
  • the pixel units 111 include pixel circuits and light-emitting elements.
  • Cascaded shift registers are provided in the non-display area 120 , and the circuit formed by the shift registers is called a GIP (Gate In Panel) circuit 121 .
  • the GIP circuit 121 is electrically connected to a driving IC (integrated circuit, integrated circuit) 122 through a signal wire 130
  • the GIP circuit 121 is electrically connected to the pixel unit 111 through a signal wire 140 .
  • the display panel is an Organic Light-Emitting Diode (OLED) display panel based on Low Temperature Polysilicon (LTPS).
  • OLED Organic Light-Emitting Diode
  • LTPS Low Temperature Polysilicon
  • the process of displaying on the OLED display panel is the process of scanning the pixel units 111 line by line with the signal output by the GIP circuit 121 , and the signal output by the GIP circuit 121 is actually a copied clock signal.
  • GIP circuits 121 There are many types of GIP circuits 121, and according to the type of output signals, they can be divided into Scan circuits that output Scan signals, EM circuits that output emissive (EM) signals, and GIPs that can output both Scan signals and EM signals circuit.
  • the GIP circuit 121 is taken as an example of a Scan circuit for illustration.
  • the GIP circuit 121 includes a plurality of shift registers, and every four shift registers is a group, which includes n groups in total.
  • the shift register Scan n-4 and the shift register Scan are arranged in sequence.
  • the clock signals include a first clock signal SCK1, a second clock signal SCK2, a third clock signal SCK3 and a fourth clock signal SCK4.
  • the X direction may be recorded as the first direction.
  • the clock signal is transmitted along the X direction by the side where the driver IC 122 is located.
  • the shift register located on the opposite side of the driver IC 122 is affected by the load of the shift register.
  • the RC delay is greater than the RC delay of the shift register on the side where the driver IC 122 is located. Therefore, the rise time (Rise Time, Tr) and the fall time (Fall Time, Tf) of the signal output by the shift register on the side of the drive IC 122 and the shift register on the opposite side of the drive IC 122 are quite different.
  • the Tr/Tf difference between the signal output by the shift register Scan n-2 and the signal output by the shift register Scan1-1 is relatively large, and the pixel unit provided by the shift register Scan n-2 is different from that provided by the shift register Scan1. -1
  • the display effect of the pixel units that provide the signal varies greatly, thus affecting the display uniformity of the display panel.
  • an embodiment of the present application provides a display panel that can improve this situation.
  • FIG. 3 is a schematic structural diagram of a display panel provided by an embodiment of the present application, and the display panel further includes a first side 2201 and a second side 2202 that are oppositely arranged in a first direction.
  • FIG. 4 is a schematic structural diagram of an area A2 in the display panel shown in FIG. 3 .
  • the display panel includes: a display area 210 and a non-display area 220 , and pixel units 211 arranged in an array are arranged in the display area 210 .
  • the display panel further includes at least two controlled modules 221 and signal wires 230 respectively connected to the at least two controlled modules 221 .
  • the signal wiring 230 is configured to receive the driving signal sent by the driving module 222 and transmit the driving signal to the controlled module 221 .
  • the controlled module 221 and the driving module 222 correspond to each other, the driving module 222 sends a driving signal to the controlled module 221, and the controlled module 221 receives the driving signal.
  • the controlled module 221 is a shift register, and the driving module 222 is a driving IC; for another example, the controlled module 221 is a pixel circuit, and the driving module 222 is a shift register; for another example, the controlled module 221 is a pixel circuit, and the driving module 222 is a data driving module and the like.
  • the number of controlled modules 221 is large, and the signals received by the controlled modules 221 farther from the driving module 222 and the controlled modules 221 nearer to the driving module 222 are different.
  • the embodiment of the present application reduces this difference by improving the wiring connection manner of the signal wiring 230 between the controlled module 221 and the driving module 222 .
  • the following description will be given by taking the controlled module 221 as a shift register as an example.
  • the signal wiring 230 connecting the controlled module 221 and the driving module 222 includes a first path wiring part 231 and a second path wiring part 232 ; the first end of the first path wiring part 231 2311 and the first end 2321 of the second path wiring portion 232 are configured to be connected to the same driving signal, such as the clock signal SCK3.
  • the first path routing portion 231 sequentially transmits driving signals to the at least two controlled modules 221 according to the first preset order
  • the second path routing portion 232 sequentially transmits the driving signals to the at least two controlled modules 221 according to the second preset order signals, the first preset order and the second preset order are different. That is to say, the wiring connections of the first path wiring portion 231 and the second path wiring portion 232 are different, so that there are two paths for the driving signal to be transmitted to each controlled module 221 .
  • the first path routing portion 231 is connected to the controlled module 221 at a position close to the first end 2311 of the first path routing portion 231 , and is gradually connected to the first path routing portion.
  • the second path routing portion 232 starts wiring at a position close to the first end 2321 of the second path routing portion 232, and starts to connect to the controlled module 221 when the routing reaches the middle position of the second path routing portion 232.
  • the first The two-path wiring portion 232 is connected to the controlled module 221 , that is, the shift register Scan1 - 1 , which is close to the second end 2322 of the second-path wiring portion 232 .
  • the second-path wiring portion 232 is connected step by step. To the controlled module 221 close to the third end 2323 of the second path wiring portion 232, that is, the shift register Scan n-4.
  • the first path corresponding to the first path routing portion 231 is that the clock signal SCK3 passes through the shift register Scan n-2, shift register Bit register Scan n-1,..., shift register Scan n/2-1 is the shift register located in the middle,..., shift register Scan 1-2, and then transfer to shift register Scan1-1.
  • the second path corresponding to the second path routing portion 232 is that the clock signal SCK3 sequentially passes through the shift register Scan n/2-1 (that is, the shift register located in the middle), ... and the shift register Scan 1-2, and then transmits the to the shift register Scan1-1.
  • the number of shift registers that the driving signal in the second path passes through before being transmitted to the shift register Scan1-1 is smaller, and the RC delay caused by the RC load of the multi-stage shift register is smaller,
  • the clock signal SCK3 is transmitted to the shift register Scan1-1 earlier in the second path.
  • the second path routing portion 232 is provided, and the second path routing portion 232 is closest to the controlled module 221 .
  • connection node close to the first side 2201 is farther from the first side 2201 than the connection node between the first path routing portion 231 and the controlled module 221 closest to the first side 2201, and the two path routing portions transmit
  • the superposition of the SCK signals increases the time to reach the active level, reduces the RC delay of the drive signal received by the controlled module 221 located in the X direction close to the second side 2202, and reduces the X direction close to the second side
  • the difference in characteristics such as Tr/Tf of the driving signal received by the controlled module 221 of 2202 and the controlled module 221 located near the first side 2201 in the X direction reduces the difference in pixel circuit charging time and improves display uniformity.
  • the display panel further includes at least two controlled modules 221, and one of the at least two controlled modules 221 is close to the first side 2201, for example, selected from Scan n-1, Scan n-2, Scan n- 3.
  • Scan n-4 another controlled module is close to the second side 2202, for example selected from Scan 1-1, Scan 1-2, Scan 1-3, Scan1-4, and the middle position is located near the first side 2201. Between one controlled module and another controlled module near the second side 2202.
  • the first preset sequence is: the drive signal first passes through the controlled module close to the first side 2201, and then is transmitted to the controlled module close to the second side 2202, that is, the drive signal passes through the at least two controlled modules first.
  • the controlled module of the controlled modules that is closer to the first side 2201 is then transmitted to the other controlled module of the at least two controlled modules.
  • the second preset sequence is as follows: the driving signal directly passes over the controlled module closer to the first side 2201 through the intermediate position and is transmitted to the controlled module closer to the second side 2202 .
  • the second preset sequence is that the driving signal is first input to the controlled module located between the second side 2202 and the middle position, which is closer to the middle position module, and then transferred to the controlled module closer to the second side 2202.
  • the uniformity of the display panel can be improved by changing the first preset order and the second preset order.
  • FIG. 5 is another schematic structural diagram of the area A2 in the display panel shown in FIG. 3 .
  • the first end 2311 of the first path wiring portion 231 and the first end 2321 of the second path wiring portion 232 are respectively connected to driving signals.
  • the first preset sequence is: the controlled module 221 closer to the first side 2201 receives the driving signal first than the other controlled module 221 , that is, the driving signal is first input to the controlled module 221 near the first side 2201 among the plurality of controlled modules 221 .
  • the control module 221, for example, the shift register Scan n-2 receives the signal before Scan1-2; the second preset sequence is: the controlled module 221 farther away from the first side 2201 receives the drive first than the other controlled module 221
  • the signal, that is, the driving signal is first input to the controlled module 221 far from the first side 2201 among the plurality of controlled modules 221.
  • the shift register Scan1-2 receives the signal before Scann-2. That is, the first preset order and the second preset order are completely opposite.
  • the first path routing portion 231 extends to the second side 2202 along the X direction, and the first path routing portion 231 is connected to the shift register Scan n-2 at a position closer to the first side 2201, and goes up step by step. Connect to shift register Scan1-1.
  • the second path routing portion 232 is routed from the position of the first end 2321 of the second path routing portion 232 toward the second side 2202, and is connected to the shift register Scan1-1 close to the second side 2202 by the shifting Register Scan1-1 is cascaded down to shift register Scann-2. That is, the driving signal is output from the first side 2201 and the second side 2202 to the middle between the first side 2201 and the second side 2202 .
  • the first path is that the clock signal SCK3 sequentially passes through the shift register Scan n-2, the shift register Scan n-1, ..., shift register After register Scan 1-2, it is transferred to shift register Scan1-1.
  • the second path is that the clock signal SCK3 is directly transmitted to the shift register Scan1-1.
  • the second path wiring portion 232 and the controlled module 221 are closest to the connection node of the first side 2201 , and are closer to the connection node of the first side 2201 than the first path wiring portion 231 and the controlled module 221 Further away from the first side 2201 .
  • the shift register group Scan 1 includes Scan 1-1 , Scan 1-2, Scan 1-3 and Scan 1-4
  • the shift register group Scan n includes Scan n-1, Scan n-2, Scan n-3 and Scan n-4
  • the resistance borne by the clock signal SCK3 and capacitance data as shown in Table 1.
  • R is the resistance added by each additional stage of the shift register
  • Ro is the resistance of the wiring part (which can also be recorded as the winding part)
  • C is the added capacitance of each additional stage of the shift register.
  • Table 1 that in FIG. 5 , the difference in RC delay of the clock signal SCK3 corresponding to the shift register close to the second side 2202 and the shift register close to the first side 2201 is small and can be approximately equal. Accordingly, characteristics such as Tr/Tf of the clock signal SCK3 can be considered to be equal. Therefore, the embodiment of the present application reduces the difference in the charging time of the pixel circuits and improves the display uniformity.
  • FIG. 6 is another schematic structural diagram of the area A2 in the display panel shown in FIG. 3 .
  • the second path routing part 232 includes a transmission subsection 2324 and a winding subsection 2325 , the transmission subsection 2324 is connected to the controlled module 221 , and the first The path routing portion 231 is multiplexed into the transmission subsection 2324 .
  • the winding section 2325 extends from the first end 2325A of the winding section 2325 to the second end 2325B of the winding section 2325; and the first end 2325A of the winding section 2325 is connected to the driving signal, and the winding section 2325
  • the second end 2325B of the first path wiring portion 231 is connected to one end 2324A of the first path wiring portion 231 close to the second side 2202 .
  • the embodiment of the present application is arranged in this way, on the basis of improving the display uniformity, the space occupied by the second path wiring portion 232 is simplified, thereby reducing the wiring design difficulty of the display panel.
  • the signal wiring 230 only includes the first path wiring part 231 and the second path wiring part 232 .
  • the signal wiring 230 may also include a third path wiring portion 233 and the like, that is, the driving signal is transmitted to the controlled module 221 through at least three paths to improve display uniformity.
  • FIG. 7 is another structural schematic diagram of the area A2 in the display panel shown in FIG. 3 .
  • the first end 2331 of the third path routing portion 233 is configured to be connected to a clock signal, the same as the first path routing portion 231 and the second path routing portion 232 .
  • SCK3; the third path routing part 233 sequentially transmits the driving signals to the at least two controlled modules 221 according to the third preset sequence; the first preset sequence, the second preset sequence and the third preset sequence are different.
  • the third preset sequence is: the driving signal is transmitted to the controlled module close to the second side 2202 through the intermediate position, and does not pass through the controlled module close to the first side 2201 on the way, that is, the driving signal does not pass through the at least one controlled module.
  • the one of the two controlled modules that is closer to the first side 2201 is transmitted to the other of the at least two controlled modules.
  • the third preset sequence is that the driving signal is firstly transmitted to the controlled module located between the second side 2202 and the middle position, which is closer to the middle position.
  • the control module is then transmitted to the controlled module close to the second side 2202 .
  • the first path routing portion 231 extends from the first side 2201 toward the second side 2202, is connected to the shift register Scan n-2 at a position close to the first side 2201, and is connected to the shift register Scan1 step by step upward. -1.
  • the second path routing part 232 starts routing at a position close to the first end 2321 of the first side 2201, and is routed to the shift register Scan1-1 close to the second side 2202, from which the shift register Scan1-1 goes down step by step Connect to shift register Scan n-2.
  • the second path routing portion 232 includes a transmission subsection 2324 and a routing subsection 2325 .
  • the transmission subsection 2324 is connected to the controlled module 221 , and the first path routing portion 231 is multiplexed into the transmission subsection 2324 .
  • the third path routing portion 233 extends from the middle of the third path routing portion 233 toward the first side 2201 , and extends from the middle of the third path routing portion 233 toward the second side 2202 .
  • the third path routing portion 233 includes a transmission subsection 2334 and a routing subsection 2335 .
  • the transmission subsection 2324 is connected to the controlled module 221 , and the first path routing portion 231 is multiplexed into the transmission subsection 2334 .
  • the configuration of the embodiment of the present application is not only beneficial to reduce the difference between the driving signals received by the controlled module 221 close to the second side 2202 and the controlled module 221 close to the first side 2201, but also helps to reduce the difference in the driving signals received by the controlled module 221 located on the first side 2201 and the second side 2202 in the middle of the controlled module 221 and the difference in the driving signal received by the controlled module 221 close to the first side 2201, thereby reducing the difference in the driving signal received by each controlled module 221. Therefore, the difference in the charging time of the pixel circuit is smaller, and the uniformity of the display is improved.
  • connection relationship between the signal wiring 230 and the multiple controlled modules 221 is exemplarily described.
  • the embodiment of the present application limits the setting position of the second path wiring portion 232 .
  • the following describes various arrangement positions of the signal traces 230 .
  • FIG. 8 is another schematic structural diagram of the area A2 in the display panel shown in FIG. 3 . 4 to 6 and 8, in an embodiment of the present application, the display panel further includes: a first side area 2203 and a second side area respectively disposed on both sides of the at least two controlled modules 221 2204.
  • the first path routing portion 231 and the second path routing portion 232 are both disposed in the first side region 2203 .
  • the plurality of second path routing parts 232 are all routed through the left area of the first path routing part 231 , bypass some of the controlled modules 221 and then connect to the remaining part of the controlled modules 221 .
  • FIG. 4 the plurality of second path routing parts 232 are all routed through the left area of the first path routing part 231 , bypass some of the controlled modules 221 and then connect to the remaining part of the controlled modules 221 .
  • the plurality of second path routing portions 232 are all routed through the left region of the first path routing portion 231 and routed to the controlled module 221 close to the second side 2202 to connect with the first routing portion 231 .
  • 231 provides drive signals to the controlled module 221 in reverse order.
  • FIG. 6 and FIG. 5 The difference between FIG. 6 and FIG. 5 is that the first path routing part 231 in FIG. 6 is multiplexed into the transmission subsection 2324 of the second path routing part 232 .
  • the plurality of second path routing portions 232 are respectively routed through the right region of the corresponding first path routing portion 231 .
  • first path routing portion 231 and the second path routing portion 232 are both disposed in the first side region 2203
  • first path routing portion 231 and the second path routing portion 231 are arranged in the first side region 2203 .
  • the line portions 232 are all disposed in the second side region 2204, and details are not described herein again.
  • FIG. 9 is another schematic structural diagram of the area A2 in the display panel shown in FIG. 3
  • FIG. 10 is another structural schematic diagram of the area A2 in the display panel shown in FIG. 3 . 7 , 9 and 10
  • the first routing portion 231 is disposed in the first side region 2203
  • the second routing portion 232 is disposed in the first side In the area 2203 and the second side area 2204 , and in the second side area 2204 , the second path routing portion 232 extends from the first side 2201 toward the second side 2202 .
  • the second path routing portion 232 is routed from the second side region 2204 to the first side region 2203 , and the second path routing portion 232 is first connected to a controlled
  • the modules 221 are connected to provide driving signals to each of the controlled modules 221 in the reverse order of the first path wiring portion 231 .
  • FIG. 10 and FIG. 9 is that the first path routing part 231 in FIG. 10 is multiplexed into the transmission subsection 2324 of the second path routing part 232 .
  • the signal wiring 230 further includes a third path wiring part 233 , and the third path wiring part 233 is all wound through the left area of the first path wiring part 231 , and the bypass part is The controlled module 221 is then connected to the remaining part of the controlled modules 221 .
  • the controlled module 221 includes a shift register
  • the signal line 230 includes a clock signal line as an example for description, so as to reduce the difference in shifting the clock signal by the shift register.
  • the signal trace 230 connected to the shift register may also be set to include a power signal line or a reference voltage signal line, etc., so as to reduce the difference of the corresponding signals and improve the uniformity of the display.
  • FIG. 11 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • the controlled module 221 is located in the display area 210 of the display panel, the controlled module 221 includes a pixel circuit, the driving module 222 is a data driving module, and the signal lines 230 are data lines.
  • the signal wiring 230 includes a first path wiring part 231 and a second path wiring part 232; the first end 2311 of the first path wiring part 231 and the first end 2321 of the second path wiring part 232 are set to be connected to the same data signal.
  • the first path routing portion 231 sequentially transmits driving signals to the at least two controlled modules 221 according to the first preset order
  • the second path routing portion 232 sequentially transmits the driving signals to the at least two controlled modules 221 according to the second preset order signals, the first preset order and the second preset order are different.
  • the signal trace 230 is set as a data line, which reduces the difference between the signals received by the pixel circuit close to the second side 2202 and the pixel circuit close to the first side 2201, thereby making the difference in the charging time of the pixel circuit smaller, Improved display uniformity.
  • FIG. 12 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • the controlled module 221 includes a pixel circuit
  • the driving module 222 is a shift register
  • the signal line 230 is a scan line or an initialization signal line.
  • the signal wiring 230 includes a first path wiring part 231 and a second path wiring part 232; the first end 2311 of the first path wiring part 231 and the first end 2321 of the second path wiring part 232 are set to be connected to The same scan signal or initialization signal.
  • the first path routing portion 231 sequentially transmits driving signals to the at least two controlled modules 221 according to the first preset order
  • the second path routing portion 232 sequentially transmits the driving signals to the at least two controlled modules 221 according to the second preset order signals, the first preset order and the second preset order are different.
  • the signal trace 230 is set as a scan line or an initialization signal line, which reduces the difference between the signals received by the pixel circuit close to the second side 2202 and the pixel circuit close to the first side 2201 , thereby reducing the charging time of the pixel circuit. The difference is small, improving the uniformity of the display.
  • the first path wiring portion 231 and the second path wiring portion 232 are arranged at the same layer or different layers.
  • the film layer where the first path wiring portion 231 is located has sufficient wiring space
  • the second path wiring portion 232 and the first path wiring portion 231 can be arranged on the same layer, so as to facilitate the thinning of the display panel.
  • the wiring space of the film layer where the first path wiring portion 231 is located is limited, at least part of the second path wiring portion 232 can be arranged on the same layer as other film layers in the display panel, so as to facilitate the thinning of the display panel.
  • the driving module 222 is disposed on the display panel, the first end 2311 of the first path wiring portion 231 and the first end 2311 of the second path wiring portion 232
  • the terminals 2321 are all connected to the same port of the driver module 222 .
  • the controlled module 221 is a shift register
  • the driving module 222 is a driving IC.
  • One end of the driving module 222 may be located below the display area 210, or may be bent to the back of the display panel. In practical applications, it can be set as required.
  • the controlled module 221 is a pixel circuit
  • the driving module 222 is a data driving module.
  • One end of the driving module 222 may be located below the display area 210 or bent to the back of the display panel. In practical applications Can be set as required.
  • the controlled module 221 is a pixel circuit
  • the driving module 222 is a shift register
  • one end of the driving module 222 may be located on the left side of the display area 210 .
  • FIG. 13 is a schematic structural diagram of another display panel according to an embodiment of the present application.
  • the display panel includes a bonding area 223, the bonding area 223 is provided with at least two pads, and the driving module provides a driving signal to the display panel through the bonding area 223; the first The first end of the routing portion 231 and the first end of the second routing portion 232 are both connected to the same pad of the bonding area 223 .
  • the flexible circuit board of the driving module is bonded on the bonding area 223 to transmit driving signals.
  • the signal wiring 230 connecting the controlled module 221 and the driving module 222 includes a first path wiring part 231 and a second path wiring part 232 ;
  • the first path wiring part 231 is arranged according to the A preset sequence transmits the driving signals to the at least two controlled modules 221 in sequence
  • the second path routing portion 232 sequentially transmits the driving signals to the at least two controlled modules 221 according to the second preset sequence and the driving signals transmitted through the first preset sequence
  • the first preset sequence and the second preset sequence are different.
  • the embodiment of the present application reduces the RC delay of the driving signal received by the controlled module 221 located close to the second side 2202, and reduces the controlled module 221 located close to the second side 2202 and the controlled module 221 located close to the first side 2202.
  • the difference in characteristics such as Tr/Tf of the driving signal received by the controlled module 221 on the side 2201 reduces the difference in the charging time of the pixel circuits and improves the display uniformity.
  • the embodiment of the present application also provides a display device.
  • the display device may be, for example, a mobile phone, a computer, a tablet computer, a wearable device, a smart home, a smart home appliance, an electronic book, an information inquiry machine, and other products.
  • the display device includes the display panel provided in any of the embodiments of the present application, and the effects produced by the display device and the display panel are similar, and details are not described herein again.

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Abstract

本申请实施例公开了一种显示面板和显示装置。显示面板包括:至少两个受控模块,以及与所述至少两个受控模块连接的信号走线;所述信号走线设置为接收驱动模块发出的驱动信号,并将所述驱动信号传输至所述至少两个受控模块;其中,所述信号走线包括第一路径走线部和第二路径走线部;所述第一路径走线部的第一端和所述第二路径走线部的第一端设置为接入相同的驱动信号;所述第一路径走线部设置为按照第一预设顺序依次向所述至少两个受控模块传输所述驱动信号;所述第二路径走线部设置为按照第二预设顺序依次向所述至少两个受控模块传输所述驱动信号;所述第一预设顺序和所述第二预设顺序不同。

Description

显示面板和显示装置
本申请要求在2020年11月27日提交中国专利局、申请号为202011360409.6的中国专利申请的优先权,以上申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及显示技术领域,例如涉及一种显示面板和显示装置。
背景技术
随着显示技术的不断发展,显示面板的应用越来越广泛,消费者对显示面板的要求也越来越高。尤其是显示面板的显示画质,始终是消费者和面板生产厂商对显示面板的品质衡量的重要指标之一。然而,显示面板可能存在着显示不均匀的情况,影响了显示面板显示画质的提升。
申请内容
本申请实施例提供一种显示面板和显示装置,以改善显示不均的工况,提升显示画质。
本申请实施例提供一种显示面板,包括:
至少两个受控模块,以及与所述至少两个受控模块连接的信号走线;所述信号走线设置为接收驱动模块发出的驱动信号,并将所述驱动信号传输至所述至少两个受控模块;
其中,所述信号走线包括第一路径走线部和第二路径走线部;所述第一路径走线部的第一端和所述第二路径走线部的第一端设置为接入相同的驱动信号;
所述第一路径走线部设置为按照第一预设顺序依次向所述至少两个受控模块传输所述驱动信号;所述第二路径走线部设置为按照第二预设顺序依次向所述至少两个受控模块传输所述驱动信号;所述第一预设顺序和所述第二预设顺序不同。
本申请还提供了一种显示装置,包括:如本申请任意实施例所述的显示面板。
本申请实施例设置连接受控模块和驱动模块的信号走线包括第一路径走线部和第二路径走线部;第一路径走线部按照第一预设顺序依次向至少两个受控模块传输驱动信号,第二路径走线部按照第二预设顺序依次向至少两个受控模 块传输与第一预设顺序相同的驱动信号,第一预设顺序和第二预设顺序不同。本申请实施例通过设置第二路径走线部来减少位于远端的受控模块接收到的驱动信号的RC延迟,从而减小了位于远端的受控模块和位于近端的受控模块接收到的驱动信号的Tr/Tf等特性差异,进而使得像素电路充电时间差异减小,改善了显示均一性。
附图说明
图1为相关技术中的一种显示面板的结构示意图;
图2为图1所示的显示面板中区域A1的结构示意图;
图3为本申请实施例提供的一种显示面板的结构示意图;
图4为图3所示的显示面板中区域A2的一种结构示意图;
图5为图3所示的显示面板中区域A2的另一种结构示意图;
图6为图3所示的显示面板中区域A2的又一种结构示意图;
图7为图3所示的显示面板中区域A2的又一种结构示意图;
图8为图3所示的显示面板中区域A2的又一种结构示意图;
图9为图3所示的显示面板中区域A2的又一种结构示意图;
图10为图3所示的显示面板中区域A2的又一种结构示意图;
图11为本申请实施例提供的另一种显示面板的结构示意图;
图12为本申请实施例提供的又一种显示面板的结构示意图;
图13为本申请实施例提供的又一种显示面板的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是,此处所描述的具体实施例仅仅用于解释本申请,而非对本申请的限定。另外还需要说明的是,为了便于描述,附图中仅示出了与本申请相关的部分而非全部结构。
相关技术中的显示面板可能出现显示不均的状况,经申请人研究发现,出现显示不均的状况的原因在于,信号线在传输过程中存在RC延迟(RC loading)。分析如下:
图1为相关技术中的一种显示面板的结构示意图,图2为图1所示的显示面板中区域A1的结构示意图。参见图1和图2,显示面板包括显示区110和非显示区120,在显示区110内设置有呈阵列排布的像素单元111,像素单元111 包括像素电路和发光元件。在非显示区120内设置有级联的移位寄存器,由移位寄存器构成的电路称为GIP(Gate In Panel)电路121。GIP电路121通过信号走线130与驱动IC(integrated circuit,集成电路)122电连接,以及GIP电路121通过信号走线140与像素单元111电连接。
示例性地,显示面板为基于低温多晶硅(Low Temperature Poly-Silicon,LTPS)的有机发光二极管(Organic Light-Emitting Diode,OLED)显示面板。OLED显示面板进行显示的过程就是GIP电路121输出的信号逐行扫描像素单元111的过程,GIP电路121输出的信号实际是复制的时钟信号。GIP电路121的种类较多,根据输出信号类型可以分为输出扫描(Scan)信号的Scan电路、输出发光(Emitting,EM)信号的EM电路、以及既能够输出Scan信号又能够输出EM信号的GIP电路。
图2中以GIP电路121为Scan电路为例进行说明,GIP电路121包括多个移位寄存器,每四个移位寄存器为一组,共包括n组。GIP电路121中沿X方向,即从显示面板的驱动IC 122所在一侧指向显示面板的与驱动IC 122相对的一侧的方向上,依次排列有移位寄存器Scan n-4、移位寄存器Scan n-3、移位寄存器Scan n-2、移位寄存器Scan n-1、……、移位寄存器Scan1-4、移位寄存器Scan1-3、移位寄存器Scan1-2和移位寄存器Scan1-1,n为正整数。即移位寄存器组Scan n靠近驱动IC 122所在一侧,移位寄存器组Scan 1靠近与驱动IC 122相对的一侧。时钟信号包括第一时钟信号SCK1、第二时钟信号SCK2、第三时钟信号SCK3和第四时钟信号SCK4。
其中,X方向可记为第一方向。
其中,时钟信号由驱动IC 122所在一侧沿X方向上传输,然而,由于时钟信号在传输过程中,受到每个移位寄存器的负载影响,位于与驱动IC 122相对一侧的移位寄存器的RC延迟大于位于驱动IC 122所在一侧的移位寄存器的RC延迟。因此,驱动IC 122所在一侧的移位寄存器与驱动IC 122相对一侧的移位寄存器输出的信号的上升时间(Rise Time,Tr)和下降时间(Fall Time,Tf)差异较大。例如,移位寄存器Scan n-2输出的信号与移位寄存器Scan1-1输出的信号的Tr/Tf差异较大,以及由移位寄存器Scan n-2提供信号的像素单元与由移位寄存器Scan1-1提供信号的像素单元的显示效果差异较大,从而影响了显示面板的显示均一性。
鉴于此状况,本申请实施例提供了一种显示面板,可改善此状况。
图3为本申请实施例提供的一种显示面板的结构示意图,显示面板还包括 在第一方向上相对设置的第一侧2201和第二侧2202。图4为图3所示的显示面板中区域A2的一种结构示意图。参见图3和图4,显示面板包括:显示区210和非显示区220,在显示区210内设置有呈阵列排布的像素单元211。
显示面板还包括至少两个受控模块221,以及分别与至少两个受控模块221连接的信号走线230。信号走线230设置为接收驱动模块222发出的驱动信号,并将驱动信号传输至受控模块221。其中,受控模块221和驱动模块222相互对应,驱动模块222向受控模块221发送驱动信号,受控模块221接收所述驱动信号。在显示面板中,存在多种受控模块221和驱动模块222的组合,例如,受控模块221是移位寄存器,驱动模块222是驱动IC;又如,受控模块221是像素电路,驱动模块222是移位寄存器;又如,受控模块221是像素电路,驱动模块222是数据驱动模块等。然而,对于显示面板而言,受控模块221的数量较多,距离驱动模块222较远的受控模块221和距离驱动模块222较近的受控模块221接收到的信号存在差异。
本申请实施例通过改进受控模块221和驱动模块222之间的信号走线230的走线连接方式来减弱这种差异。下面以受控模块221是移位寄存器为例进行说明。
继续参见图3和图4,连接受控模块221和驱动模块222的信号走线230包括第一路径走线部231和第二路径走线部232;第一路径走线部231的第一端2311和第二路径走线部232的第一端2321设置为接入相同的驱动信号,例如时钟信号SCK3。第一路径走线部231按照第一预设顺序依次向至少两个受控模块221传输驱动信号,第二路径走线部232按照第二预设顺序依次向至少两个受控模块221传输驱动信号,第一预设顺序和第二预设顺序不同。也就是说,第一路径走线部231和第二路径走线部232的走线连接方式不同,使得驱动信号传输到每个受控模块221有两条路径。
示例性地,如图4所示,第一路径走线部231在靠近第一路径走线部231的第一端2311的位置连接受控模块221,并逐级连接至靠近第一路径走线部231的第二端2312的受控模块221。第二路径走线部232在靠近第二路径走线部232的第一端2321的位置开始布线,在布线至第二路径走线部232的中部位置时开始连接受控模块221,一方面第二路径走线部232向上逐级连接至靠近第二路径走线部232的第二端2322的受控模块221即移位寄存器Scan1-1,另一方面第二路径走线部232逐级连接至靠近第二路径走线部232的第三端2323的受控模块221即移位寄存器Scan n-4。
例如,对于位于靠近驱动模块222相对一侧的移位寄存器Scan 1-1而言,第一路径走线部231对应的第一路径为,时钟信号SCK3依次经过移位寄存器Scan n-2、移位寄存器Scan n-1、……、移位寄存器Scan n/2-1即位于中部的移位寄存器、……、移位寄存器Scan 1-2后,传输至移位寄存器Scan1-1。第二路径走线部232对应的第二路径为,时钟信号SCK3依次经过移位寄存器Scan n/2-1即位于中部的移位寄存器)、……、移位寄存器Scan 1-2后,传输至移位寄存器Scan1-1。与第一路径相比,第二路径中的驱动信号在传输至移位寄存器Scan1-1之前经过的移位寄存器的数量较少,多级移位寄存器的RC负载带来的RC延迟较小,时钟信号SCK3在第二路径中更先传输至移位寄存器Scan1-1。
由此可见,图3、图4描述的本申请实施例与相关技术相比,本申请实施例通过设置第二路径走线部232,第二路径走线部232与所述受控模块221最靠近第一侧2201的连接结点,比第一路径走线部231与所述受控模块221最靠近第一侧2201的连接结点更远离第一侧2201,两个路径走线部传输的SCK信号叠加,使得能达到有效电平的时间增长,减少了位于X方向上靠近第二侧2202的受控模块221接收到的驱动信号的RC延迟,减小了位于X方向上靠近第二侧2202的受控模块221和位于X方向上靠近第一侧2201的受控模块221接收到的驱动信号的Tr/Tf等特性差异,进而使得像素电路充电时间差异减小,改善了显示均一性。
在图4中示例性地示出了第一预设顺序和第二预设顺序的一种实施方式。所述显示面板还包括至少两个受控模块221,至少两个受控模块221中的其中一个受控模块靠近第一侧2201,例如选自Scan n-1、Scan n-2、Scan n-3、Scan n-4,另一个受控模块靠近第二侧2202,例如选自Scan 1-1、Scan 1-2、Scan 1-3、Scan1-4,中间位置位于靠近第一侧2201的其中一个受控模块与靠近第二侧2202的另一个受控模块之间。
第一预设顺序为:所述驱动信号先经过靠近第一侧2201的受控模块,再传输至靠近第二侧2202的受控模块,即,所述驱动信号先经过所述至少两个受控模块中的更靠近所述第一侧2201的所述受控模块,再传输至所述至少两个受控模块中的另一所述受控模块。
第二预设顺序为:所述驱动信号经过中间位置直接越过更靠近第一侧2201的受控模块而传输至更靠近第二侧2202的受控模块。当所述至少两个受控模块为大于两个受控模块时,第二预设顺序为,所述驱动信号先输入位于第二侧2202和中间位置之间更靠近中间位置的所述受控模块,再传输至更靠近第二侧2202 的所述受控模块。
在其他实施例中,通过改变第一预设顺序和第二预设顺序,可以改善显示面板的均一性。
图5为图3所示的显示面板中区域A2的另一种结构示意图。参见图3和图5,在本申请的一种实施方式中,第一路径走线部231的第一端2311和第二路径走线部232的第一端2321分别接入驱动信号。第一预设顺序为:更靠近第一侧2201的受控模块221比另一受控模块221先接收到驱动信号,即驱动信号先输入多个受控模块221中靠近第一侧2201的受控模块221,例如,移位寄存器Scan n-2先于Scan1-2接收信号;第二预设顺序为:更远离第一侧2201的受控模块221比另一受控模块221先接收到驱动信号,即驱动信号先输入多个受控模块221中远离第一侧2201的受控模块221,例如,移位寄存器Scan1-2先于Scan n-2接收信号。即,第一预设顺序和第二预设顺序完全相反。
示例性地,第一路径走线部231沿X方向延伸至第二侧2202,第一路径走线部231在更靠近第一侧2201的位置连接移位寄存器Scan n-2,并向上逐级连接至移位寄存器Scan1-1。第二路径走线部232从第二路径走线部232的第一端2321的位置开始朝向第二侧2202布线,并布线连接至靠近第二侧2202的移位寄存器Scan1-1,由移位寄存器Scan1-1向下逐级连接至移位寄存器Scan n-2。也就是说,驱动信号从第一侧2201和第二侧2202向第一侧2201和第二侧2202之间的中间输出。
其中,对于靠近第二侧2202的移位寄存器Scan 1-1而言,第一路径为,时钟信号SCK3依次经过移位寄存器Scan n-2、移位寄存器Scan n-1、……、移位寄存器Scan 1-2后,传输至移位寄存器Scan1-1。第二路径为,时钟信号SCK3直接传输至移位寄存器Scan1-1。第二路径走线部232与所述受控模块221最靠近第一侧2201的连接结点,比第一路径走线部231与所述受控模块221最靠近第一侧2201的连接结点更远离第一侧2201。
比较相关技术和图5中的实施例,以靠近第二侧2202的移位寄存器组Scan1和靠近第一侧2201的移位寄存器组Scan n为例,移位寄存器组Scan 1包括Scan 1-1、Scan 1-2、Scan 1-3及Scan 1-4,移位寄存器组Scan n包括Scan n-1、Scan n-2、Scan n-3及Scan n-4,时钟信号SCK3所承担的电阻和电容数据,如表1所示。其中,R为每增加一级移位寄存器所增加的电阻;Ro为布线部分(也可记为绕线部分)的电阻;C为每加一级移位寄存器所增加的电容。
表1
Figure PCTCN2021115583-appb-000001
其中图5描述的实施例中Scan 1的电阻为Ro*4nR/(Ro+4nR),将Ro=4nR带入,得到Scan 1的电阻为2nR。由表1可以看出,在图5中,靠近第二侧2202的移位寄存器和靠近第一侧2201的移位寄存器对应的时钟信号SCK3所承负载RC延迟差别很小,可近似为相等。相应地,时钟信号SCK3的Tr/Tf等特性可以认为是相等的。因此,本申请实施例减小了像素电路充电时间的差异,改善了显示均一性。
图6为图3所示的显示面板中区域A2的又一种结构示意图。参见图3和图6,在本申请的一种实施方式中,第二路径走线部232包括传输分部2324和绕线分部2325,传输分部2324与受控模块221连接,且第一路径走线部231复用为传输分部2324。绕线分部2325由绕线分部2325的第一端2325A延伸至绕线分部2325的第二端2325B;且绕线分部2325的第一端2325A接入驱动信号,绕线分部2325的第二端2325B与第一路径走线部231靠近第二侧2202的一端2324A连接。本申请实施例这样设置,在改善显示均一性的基础上,简化了第二路径走线部232所占用的空间,从而降低了显示面板的走线设计难度。
在上述实施例中示例性地,信号走线230仅包括第一路径走线部231和第二路径走线部232。在其他实施例中,如图7所示,还可以设置信号走线230包括第三路径走线部233等,即驱动信号通过至少三条路径传输至受控模块221,以改善显示的均一性。
图7为图3所示的显示面板中区域A2的又一种结构示意图。参见图7,在本申请的一种实施方式中,与第一路径走线部231和第二路径走线部232相同,第三路径走线部233的第一端2331设置为接入时钟信号SCK3;第三路径走线部233按照第三预设顺序依次向至少两个受控模块221传输驱动信号;第一预设顺序、第二预设顺序和第三预设顺序均不同。
第三预设顺序为:所述驱动信号经过中间位置传输至靠近第二侧2202的受 控模块,中途不经过靠近第一侧2201的受控模块,即,所述驱动信号不经过所述至少两个受控模块中的更靠近所述第一侧2201的所述受控模块而传输至所述至少两个受控模块中的另一所述受控模块。当所述至少两个受控模块为大于两个受控模块时,第三预设顺序为,所述驱动信号先传输至位于第二侧2202和中间位置之间更靠近中间位置的所述受控模块,再传输至靠近第二侧2202的所述受控模块。
示例性地,第一路径走线部231由第一侧2201朝向第二侧2202延伸,在靠近第一侧2201的位置连接移位寄存器Scan n-2,并向上逐级连接至移位寄存器Scan1-1。第二路径走线部232在靠近第一侧2201的第一端2321的位置开始布线,并布线至靠近第二侧2202的移位寄存器Scan1-1,由移位寄存器Scan1-1向下逐级连接至移位寄存器Scan n-2。第二路径走线部232包括传输分部2324和绕线分部2325,传输分部2324与受控模块221连接,且第一路径走线部231复用为传输分部2324。第三路径走线部233由第三路径走线部233的中间朝向第一侧2201延伸,以及由第三路径走线部233的中间朝向第二侧2202延伸。第三路径走线部233包括传输分部2334和绕线分部2335,传输分部2324与受控模块221连接,且第一路径走线部231复用为传输分部2334。
本申请实施例这样设置,不仅有利于减小靠近第二侧2202的受控模块221与靠近第一侧2201的受控模块221接收到的驱动信号的差异,而且有利于减小位于第一侧2201和第二侧2202之间的中部的受控模块221与靠近第一侧2201的受控模块221接收到的驱动信号的差异,从而减小了每个受控模块221接收到的驱动信号的差异,进而使得像素电路充电时间差异更小,改善了显示的均一性。
在上述实施例中示例性地对信号走线230与多个受控模块221的连接关系进行了说明。在上述实施例的基础上,本申请实施例对第二路径走线部232的设置位置进行限定。下面就信号走线230的多种设置位置进行说明。
图8为图3所示的显示面板中区域A2的又一种结构示意图。结合图4-图6、图8,在本申请的一种实施方式中,显示面板还包括:分别设置于至少两个受控模块221两侧的第一侧边区域2203和第二侧边区域2204。第一路径走线部231和第二路径走线部232均设置于第一侧边区域2203内。示例性地,在图4中,多条第二路径走线部232全部通过第一路径走线部231的左侧区域布线,绕过部分受控模块221后连接至剩余部分受控模块221。在图5中,多条第二路径走线部232全部通过第一路径走线部231的左侧区域布线,布线至靠近第二侧2202 的受控模块221,以与第一路径走线部231相反的顺序向受控模块221提供驱动信号。图6与图5的不同点在于,图6中的第一路径走线部231复用为第二路径走线部232的传输分部2324。在图8中,多条第二路径走线部232分别通过对应的第一路径走线部231的右侧区域布线。
在本申请的一种实施方式中,与第一路径走线部231和第二路径走线部232均设置于第一侧边区域2203内类似,第一路径走线部231和第二路径走线部232均设置于第二侧边区域2204内,这里不再赘述。
图9为图3所示的显示面板中区域A2的又一种结构示意图,图10为图3所示的显示面板中区域A2的又一种结构示意图。结合图7、图9和图10,在本申请的一种实施方式中,第一路径走线部231设置于第一侧边区域2203内;第二路径走线部232设置于第一侧边区域2203和第二侧边区域2204内,且在第二侧边区域2204内,第二路径走线部232由第一侧2201朝向第二侧2202延伸。示例性地,在图9中,第二路径走线部232由第二侧边区域2204绕线至第一侧边区域2203,第二路径走线部232先与靠近第二侧2202的受控模块221连接,以与第一路径走线部231相反的顺序向每个受控模块221提供驱动信号。图10与图9的不同点在于,图10中的第一路径走线部231复用为第二路径走线部232的传输分部2324。图7与图10的不同点在于,信号走线230还包括第三路径走线部233,第三路径走线部233全部通过第一路径走线部231的左侧区域绕线,绕过部分受控模块221后连接至剩余部分受控模块221。
在上述实施例中,以受控模块221包括移位寄存器,信号走线230包括时钟信号线为例进行说明,以减小移位寄存器对时钟信号移位的差异。在其他实施例中,还可以设置与移位寄存器相连的信号走线230包括电源信号线或参考电压信号线等,以减小对应信号的差异,提升显示的均一性。
图11为本申请实施例提供的另一种显示面板的结构示意图。参见图11,在本申请的一种实施方式中,受控模块221位于显示面板的显示区210,受控模块221包括像素电路,驱动模块222为数据驱动模块,信号走线230为数据线。信号走线230包括第一路径走线部231和第二路径走线部232;第一路径走线部231的第一端2311和第二路径走线部232的第一端2321设置为接入相同的数据信号。第一路径走线部231按照第一预设顺序依次向至少两个受控模块221传输驱动信号,第二路径走线部232按照第二预设顺序依次向至少两个受控模块221传输驱动信号,第一预设顺序和第二预设顺序不同。连接像素电路的第一路径走线部231和第二路径走线部232的设置方式可以参考上述实施例。本申请 实施例设置信号走线230为数据线,减小了靠近第二侧2202的像素电路和靠近第一侧2201的像素电路接收到的信号的差异,进而使得像素电路充电时间差异较小,改善了显示的均一性。
图12为本申请实施例提供的又一种显示面板的结构示意图。参见图12,在本申请的一种实施方式中,受控模块221包括像素电路,驱动模块222为移位寄存器,信号走线230为扫描线或初始化信号线。信号走线230包括第一路径走线部231和第二路径走线部232;第一路径走线部231的第一端2311和第二路径走线部232的第一端2321设置为接入相同的扫描信号或初始化信号。第一路径走线部231按照第一预设顺序依次向至少两个受控模块221传输驱动信号,第二路径走线部232按照第二预设顺序依次向至少两个受控模块221传输驱动信号,第一预设顺序和第二预设顺序不同。本申请实施例设置信号走线230为扫描线或初始化信号线,减小了靠近第二侧2202的像素电路和靠近第一侧2201的像素电路接收到的信号的差异,进而使得像素电路充电时间差异较小,改善了显示的均一性。
在上述实施例的基础上,第一路径走线部231和第二路径走线部232同层设置或异层设置。示例性地,若第一路径走线部231所在的膜层走线空间充裕,可以设置第二路径走线部232与第一路径走线部231同层设置,以有利于显示面板的轻薄化。若第一路径走线部231所在的膜层走线空间有限,可以设置至少部分的第二路径走线部232与显示面板中的其他膜层同层设置,以有利于显示面板的轻薄化。
结合图3、图11和图12,在上述实施例的基础上,驱动模块222设置于显示面板上,第一路径走线部231的第一端2311和第二路径走线部232的第一端2321均连接至驱动模块222的同一端口。示例性地,在图3中,受控模块221为移位寄存器,驱动模块222为驱动IC,驱动模块222的一端可以位于显示区210的下方,也可以是弯折至显示面板的背面,在实际应用中可以根据需要进行设定。在图11中,受控模块221为像素电路,驱动模块222为数据驱动模块,驱动模块222的一端可以是位于显示区210的下方,也可以是弯折至显示面板的背面,在实际应用中可以根据需要进行设定。在图12中,受控模块221为像素电路,驱动模块222为移位寄存器,驱动模块222的一端可以是位于显示区210的左侧。
图13为本申请实施例提供的又一种显示面板的结构示意图。参见图13,在本申请的一种实施方式中,显示面板包括邦定区223,邦定区223设置有至少两 个焊盘,驱动模块通过邦定区223向显示面板提供驱动信号;第一路径走线部231的第一端和第二路径走线部232的第一端均连接至邦定区223的同一焊盘。驱动模块的柔性电路板邦定于邦定区223上,以进行驱动信号的传输。
综上所述,本申请实施例设置连接受控模块221和驱动模块222的信号走线230包括第一路径走线部231和第二路径走线部232;第一路径走线部231按照第一预设顺序依次向至少两个受控模块221传输驱动信号,第二路径走线部232按照第二预设顺序依次向至少两个受控模块221传输与通过第一预设顺序传输的驱动信号相同的驱动信号,第一预设顺序和第二预设顺序不同。与相关技术相比,本申请实施例减少了位于靠近第二侧2202的受控模块221接收到的驱动信号的RC延迟,减小了位于靠近第二侧2202的受控模块221和靠近第一侧2201的受控模块221接收到的驱动信号的Tr/Tf等特性差异,进而使得像素电路充电时间差异减小,改善了显示均一性。
本申请实施例还提供了一种显示装置。显示装置例如可以是手机、电脑、平板电脑、可穿戴设备、智能家居、智能家电、电子书和信息查询机等产品。显示装置包括本申请任意实施例所提供的显示面板,显示装置与显示面板产生的效果类似,不再赘述。
注意,上述仅为本申请的较佳实施例及所运用技术原理。本领域技术人员会理解,本申请不限于这里所述的特定实施例,对本领域技术人员来说能够进行各种明显的变化、重新调整和替代而不会脱离本申请的保护范围。因此,虽然通过以上实施例对本申请进行了较为详细的说明,但是本申请不仅仅限于以上实施例,在不脱离本发明构思的情况下,还可以包括更多其他等效实施例,而本申请的范围由所附的权利要求范围决定。

Claims (17)

  1. 一种显示面板,包括:
    至少两个受控模块,以及
    与所述至少两个受控模块连接的信号走线,所述信号走线设置为接收驱动模块发出的驱动信号,并将所述驱动信号传输至所述至少两个受控模块;
    其中,所述信号走线包括第一路径走线部和第二路径走线部;所述第一路径走线部的第一端和所述第二路径走线部的第一端设置为接入相同的驱动信号;
    所述第一路径走线部设置为按照第一预设顺序依次向所述至少两个受控模块传输所述驱动信号;所述第二路径走线部设置为按照第二预设顺序依次向所述至少两个受控模块传输所述驱动信号;所述第一预设顺序和所述第二预设顺序不同。
  2. 根据权利要求1所述的显示面板,其中,所述显示面板还包括在第一方向上相对设置的第一侧和第二侧;
    所述第一预设顺序为所述驱动信号先经过所述至少两个受控模块中的更靠近所述第一侧的所述受控模块,再传输至所述至少两个受控模块中的另一所述受控模块;
    所述第二预设顺序为所述驱动信号不经过所述至少两个受控模块中的更靠近所述第一侧的所述受控模块而传输至所述至少两个受控模块中的另一所述受控模块。
  3. 根据权利要求2所述的显示面板,其中,
    所述第二预设顺序为所述至少两个受控模块中更远离第一侧的所述受控模块比另一所述受控模块先接收到所述驱动信号。
  4. 根据权利要求3所述的显示面板,其中,所述第二路径走线部包括传输分部和绕线分部;
    其中,所述传输分部与所述受控模块连接,且所述第一路径走线部复用为所述传输分部;所述绕线分部由所述绕线分部的第一端延伸至所述绕线分部的第二端,所述绕线分部的第一端接入所述驱动信号,所述绕线分部的第二端与所述第一路径走线部靠近所述第二侧的一端连接。
  5. 根据权利要求3所述的显示面板,其中,所述显示面板还包括:分别设置于所述至少两个受控模块两侧的第一侧边区域和第二侧边区域;
    所述第一路径走线部和所述第二路径走线部均设置于所述第一侧边区域内或者所述第二侧边区域内。
  6. 根据权利要求3所述的显示面板,其中,所述显示面板还包括:分别设置于所述至少两个受控模块两侧的第一侧边区域和第二侧边区域;
    所述第一路径走线部设置于所述第一侧边区域内;所述第二路径走线部设置于所述第一侧边区域或所述第二侧边区域内,且在所述第二侧边区域内的所述第二路径走线部由所述第一侧朝向所述第二侧延伸。
  7. 根据权利要求3所述的显示面板,其中,所述信号走线还包括第三路径走线部;所述第三路径走线部的第一端和所述第一路径走线部的第一端设置为接入相同的驱动信号;
    所述第三路径走线部按照第三预设顺序依次向所述至少两个受控模块传输所述驱动信号;所述第一预设顺序、所述第二预设顺序和所述第三预设顺序均不同。
  8. 根据权利要求7所述的显示面板,其中,所述第三预设顺序为所述驱动信号不经过所述至少两个受控模块中的更靠近所述第一侧的所述受控模块而传输至所述至少两个受控模块中的另一所述受控模块。
  9. 根据权利要求1-8任一项所述的显示面板,其中,所述受控模块位于所述显示面板的非显示区;
    所述受控模块包括移位寄存器;所述信号走线包括时钟信号线、电源信号线和参考电压信号线中的至少一种。
  10. 根据权利要求1-8任一项所述的显示面板,其中,所述受控模块位于所述显示面板的显示区;
    所述受控模块包括像素电路;所述信号走线包括数据线、扫描线和初始化信号线中的至少一种。
  11. 根据权利要求1所述的显示面板,其中,所述第一路径走线部和所述第二路径走线部同层设置或异层设置。
  12. 根据权利要求2所述的显示面板,其中,所述显示面板还包括中间位置,所述中间位置位于所述至少两个受控模块中最靠近所述第一侧的所述受控模块与最靠近所述第二侧的另一所述受控模块之间,
    第一预设顺序为:所述驱动信号先传输至所述至少两个受控模块中的更靠近所述第一侧的所述受控模块,再传输至所述至少两个受控模块中的另一所述受控模块;
    第二预设顺序为:所述驱动信号不经过靠近所述第一侧的所述受控模块,而经过中间位置传输至另一所述受控模块。
  13. 根据权利要求9所述的显示面板,其中,所述驱动模块包括驱动集成电路。
  14. 根据权利要求10所述的显示面板,其中,所述驱动模块包括移位寄存器。
  15. 根据权利要求1所述的显示面板,其中,所述显示面板包括邦定区,所述驱动模块设置为通过所述邦定区向所述显示面板提供驱动信号。
  16. 根据权利要求15所述的显示面板,其中,所述邦定区设置有至少两个焊盘;
    所述第一路径走线部的第一端和所述第二路径走线部的第一端分别连接至所述邦定区中的同一焊盘。
  17. 一种显示装置,包括:如权利要求1-16任一项所述的显示面板。
PCT/CN2021/115583 2020-11-27 2021-08-31 显示面板和显示装置 WO2022110950A1 (zh)

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