JP2018133568A5 - - Google Patents

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Publication number
JP2018133568A5
JP2018133568A5 JP2018023873A JP2018023873A JP2018133568A5 JP 2018133568 A5 JP2018133568 A5 JP 2018133568A5 JP 2018023873 A JP2018023873 A JP 2018023873A JP 2018023873 A JP2018023873 A JP 2018023873A JP 2018133568 A5 JP2018133568 A5 JP 2018133568A5
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Japan
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layer
metal
sio
substrate
silanol
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JP2018023873A
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Japanese (ja)
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JP7097713B2 (ja
JP2018133568A (ja
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Publication of JP2018133568A5 publication Critical patent/JP2018133568A5/ja
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JP2018023873A 2017-02-14 2018-02-14 選択的なＳｉＯ２堆積を用いた自己整合コンタクトの形成方法 Active JP7097713B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201762458858P 2017-02-14 2017-02-14
US62/458,858 2017-02-14

Publications (3)

Publication Number Publication Date
JP2018133568A JP2018133568A (ja) 2018-08-23
JP2018133568A5 true JP2018133568A5 (enExample) 2021-04-01
JP7097713B2 JP7097713B2 (ja) 2022-07-08

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JP2018023873A Active JP7097713B2 (ja) 2017-02-14 2018-02-14 選択的なＳｉＯ２堆積を用いた自己整合コンタクトの形成方法

Country Status (4)

Country Link
US (1) US10453749B2 (enExample)
JP (1) JP7097713B2 (enExample)
KR (1) KR102445015B1 (enExample)
TW (1) TWI764986B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10847363B2 (en) 2017-11-20 2020-11-24 Tokyo Electron Limited Method of selective deposition for forming fully self-aligned vias
US10957579B2 (en) 2018-11-06 2021-03-23 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same
CN110010460B (zh) * 2019-03-26 2021-03-16 贵阳学院 一种低维材料形成方法
TWI801614B (zh) * 2019-06-21 2023-05-11 聯華電子股份有限公司 半導體元件及其製作方法
KR102833589B1 (ko) 2019-08-23 2025-07-15 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11227792B2 (en) * 2019-09-19 2022-01-18 International Business Machines Corporation Interconnect structures including self aligned vias
US11361989B2 (en) * 2020-02-11 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing interconnect structures including air gaps
US20220254630A1 (en) * 2021-02-08 2022-08-11 Tokyo Electron Limited Liquid phase conformal silicon oxide spin-on deposition
US11482454B2 (en) 2021-02-17 2022-10-25 Tokyo Electron Limited Methods for forming self-aligned contacts using spin-on silicon carbide
US11756790B2 (en) 2021-03-09 2023-09-12 Tokyo Electron Limited Method for patterning a dielectric layer

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0362571A3 (en) * 1988-10-07 1990-11-28 International Business Machines Corporation Method for forming semiconductor components
JP3469251B2 (ja) * 1990-02-14 2003-11-25 株式会社東芝 半導体装置の製造方法
JP4063619B2 (ja) * 2002-03-13 2008-03-19 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法
US7294593B2 (en) 2002-11-21 2007-11-13 Kimberly-Clark Worldwide, Inc. Absorbent article material with elastomeric borders
US6867152B1 (en) 2003-09-26 2005-03-15 Novellus Systems, Inc. Properties of a silica thin film produced by a rapid vapor deposition (RVD) process
US8158488B2 (en) 2004-08-31 2012-04-17 Micron Technology, Inc. Method of increasing deposition rate of silicon dioxide on a catalyst
US7271112B1 (en) * 2004-12-30 2007-09-18 Novellus Systems, Inc. Methods for forming high density, conformal, silica nanolaminate films via pulsed deposition layer in structures of confined geometry
US7625820B1 (en) 2006-06-21 2009-12-01 Novellus Systems, Inc. Method of selective coverage of high aspect ratio structures with a conformal film
US7569475B2 (en) * 2006-11-15 2009-08-04 International Business Machines Corporation Interconnect structure having enhanced electromigration reliability and a method of fabricating same
JP2010225899A (ja) * 2009-03-24 2010-10-07 Elpida Memory Inc 半導体装置の製造方法
JP2013080861A (ja) * 2011-10-05 2013-05-02 Toshiba Corp 半導体装置
US9419097B2 (en) * 2014-11-24 2016-08-16 International Business Machines Corporation Replacement metal gate dielectric cap
US20170092533A1 (en) 2015-09-29 2017-03-30 Applied Materials, Inc. Selective silicon dioxide deposition using phosphonic acid self assembled monolayers as nucleation inhibitor
US10049913B2 (en) 2016-04-12 2018-08-14 Tokyo Electron Limited Methods for SiO2 filling of fine recessed features and selective SiO2 deposition on catalytic surfaces
KR20170135115A (ko) * 2016-05-30 2017-12-08 삼성전자주식회사 반도체 장치 및 그 제조 방법

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