KR102445015B1 - 선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법 - Google Patents

선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법 Download PDF

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KR102445015B1
KR102445015B1 KR1020180018268A KR20180018268A KR102445015B1 KR 102445015 B1 KR102445015 B1 KR 102445015B1 KR 1020180018268 A KR1020180018268 A KR 1020180018268A KR 20180018268 A KR20180018268 A KR 20180018268A KR 102445015 B1 KR102445015 B1 KR 102445015B1
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metal
layer
sio
dielectric layer
substrate
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KR20180093833A (ko
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칸다바라 엔 타필리
상철 한
수 두 채
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도쿄엘렉트론가부시키가이샤
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    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
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    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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KR1020180018268A 2017-02-14 2018-02-14 선택적 SiO2 퇴적을 사용하여 자기 정렬된 콘택을 형성하는 방법 Active KR102445015B1 (ko)

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US201762458858P 2017-02-14 2017-02-14
US62/458,858 2017-02-14

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KR20180093833A KR20180093833A (ko) 2018-08-22
KR102445015B1 true KR102445015B1 (ko) 2022-09-19

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US10847363B2 (en) 2017-11-20 2020-11-24 Tokyo Electron Limited Method of selective deposition for forming fully self-aligned vias
US10957579B2 (en) 2018-11-06 2021-03-23 Samsung Electronics Co., Ltd. Integrated circuit devices including a via and methods of forming the same
CN110010460B (zh) * 2019-03-26 2021-03-16 贵阳学院 一种低维材料形成方法
TWI801614B (zh) * 2019-06-21 2023-05-11 聯華電子股份有限公司 半導體元件及其製作方法
KR102833589B1 (ko) 2019-08-23 2025-07-15 삼성전자주식회사 반도체 소자 및 이의 제조 방법
US11227792B2 (en) * 2019-09-19 2022-01-18 International Business Machines Corporation Interconnect structures including self aligned vias
US11361989B2 (en) * 2020-02-11 2022-06-14 Taiwan Semiconductor Manufacturing Co., Ltd. Method for manufacturing interconnect structures including air gaps
US20220254630A1 (en) * 2021-02-08 2022-08-11 Tokyo Electron Limited Liquid phase conformal silicon oxide spin-on deposition
US11482454B2 (en) 2021-02-17 2022-10-25 Tokyo Electron Limited Methods for forming self-aligned contacts using spin-on silicon carbide
US11756790B2 (en) 2021-03-09 2023-09-12 Tokyo Electron Limited Method for patterning a dielectric layer

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JP2010225899A (ja) 2009-03-24 2010-10-07 Elpida Memory Inc 半導体装置の製造方法
JP2013080861A (ja) 2011-10-05 2013-05-02 Toshiba Corp 半導体装置
US20160293731A1 (en) 2014-11-24 2016-10-06 International Business Machines Corporation Replacement metal gate dielectric cap

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JP7097713B2 (ja) 2022-07-08
TW201841215A (zh) 2018-11-16
KR20180093833A (ko) 2018-08-22
US10453749B2 (en) 2019-10-22
TWI764986B (zh) 2022-05-21
US20180233407A1 (en) 2018-08-16
JP2018133568A (ja) 2018-08-23

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