TWI478281B - 互連結構及鑲嵌結構之製造方法 - Google Patents
互連結構及鑲嵌結構之製造方法 Download PDFInfo
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- TWI478281B TWI478281B TW096148103A TW96148103A TWI478281B TW I478281 B TWI478281 B TW I478281B TW 096148103 A TW096148103 A TW 096148103A TW 96148103 A TW96148103 A TW 96148103A TW I478281 B TWI478281 B TW I478281B
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- germanium
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28556—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
- H01L21/28562—Selective deposition
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76843—Barrier, adhesion or liner layers formed in openings in a dielectric
- H01L21/76846—Layer combinations
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
- H01L21/76855—After-treatment introducing at least one additional element into the layer
- H01L21/76856—After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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Description
例如電晶體之半導體器件一般係在一單晶矽晶圓之表面上形成,且可包括多層圖案化及互連層。在主動器件的製造已完成後,其係藉由形成多層互連線、接點、通道及介電層而連線成為所需電路組態。
在一具體實施例中,提供一種互連結構。一層介電材料具有至少一開口及一在定義該開口之側壁上的第一阻障層。一含釕及氧之第二阻障層覆蓋該第一阻障層,該第二阻障層具有一釕區、一氧化釕區,及一富含釕區。該釕區係插入於該第一阻障層與該氧化釕區之間。該氧化釕區係插入於該釕區與該富含釕區之間。
在一具體實施例中,提供一種互連結構。一層介電材料具有至少一開口及一在定義該開口之側壁上的含鉭及氮的第一阻障層。該第一阻障層具有一富含鉭區及一氮化鉭區,該鉭氮化物區之氮含量係大於該富含鉭區之氮含量。該氮化鉭區係插入於該介電材料與該富含鉭區之間。一含釕及氧之第二阻障層覆蓋該第一阻障層,該第二阻障層具有一釕區、一氧化釕區,及一富含釕區。該釕區係插入於該富含鉭區與該氧化釕區之間。該氧化釕區係插入於該釕區與該富含釕區之間。
本發明提供一種製造一鑲嵌結構的方法。在一具體實施例中,至少一開口係形成在一介電材料中。定義該開口之
側壁係用一含鉭及氮之第一阻障層塗布。該第一阻障層經處理以形成一富含鉭區及一氮化鉭區。該氮化鉭區之氮含量大於該富含鉭區的氮含量。該氮化鉭區係插入於該介電材料與該富含鉭區之間。第一阻障層係用一含釕之第二阻障層塗布。該第二阻障層經處理以形成一氧化釕區及一釕區,該釕區插入於該富含鉭區與該氧化釕區之間。該氧化釕區經處理以形成一富含釕區,該氧化釕區插入於該釕區與該富含釕區之間。
隨著微電子器件之尺寸持續減少,在多個電晶體間之信號傳播的時間延遲(傳播延遲)已日漸成為決定器件性能的重要參數。傳播延遲係與金屬互連線之電阻(R)及層間介電絕緣材料的電容(C)之乘積(亦稱為RC延遲)成比例。因此,為了使傳播延遲減至最小,有利的是併入一具有一低介電常數材料之絕緣材料結合一高導電率金屬(或低電阻率金屬)。由於銅(Cu)之低電阻值(R<2 μΩ-cm),其作為互連線之一金屬已獲得相當大關注,其係成為更常用鋁(Al)互連金屬(R=3.0至5.0 μΩ-cm)的替代。同樣地,其他例如有機矽酸玻璃(OSG)、四乙氧基矽(TEOS)、氟化矽玻璃(FSG)及碳摻雜氧化物之介電材料,亦獲得成為替代氧化矽(k4.0)之關注。
然而,在銅成為一互連材料的成功實施前,必須克服若干障礙。首先,因為銅不易於形成揮發性副產物,習知或減去式蝕刻技術係不適當。因此,鑲嵌製程係需用於形成
圖案化銅互連線,其涉及在先前經圖案化開口(如溝渠、接點或通道)中沈積導電材料。其次,因為銅在矽中易於擴散且許多介電材料圍繞金屬互連,短路或電性質之退化可能發生。因此,任何涉及銅之鑲嵌程序包括一擴散阻障層的形成以囊封銅互連線。
圖1係一鑲嵌製程的範例性具體實施例。在步驟10中,一開口係在介電層中形成。此典型係藉由在一遮罩層(例如光阻)中、在溝渠、接點或通道形狀中之介電層上圖案化開口,接著藉由溼式或乾式蝕刻來執行。較佳係,該介電材料係低k介電質(k<3.0),如k小於2.5、小於2.0或小於1.5。在步驟20中,係沈積一阻障材料以在定義該介電層中之開口的至少側壁上形成一層。一或多個阻障層可形成以保護與銅互連相鄰之介電材料,防止其受到從銅互連擴散進入相鄰介電材料內的銅原子毒害。例如,銅原子進入介電層內之擴散可造成短路或介電常數中不符合需要的增加。
在沈積至少一阻障層後,在步驟30中,一晶種層係沈積於阻障材料上以加襯該開口(如溝渠、接點或通道)之內部壁。例如,對於一銅互連材料,一銅晶種層係有利於增進良好黏著及在互連線間建立良好電接觸。銅晶種層可藉由任何適合沈積技術形成,例如化學汽相沈積(CVD)或類似者。在步驟40中,開口係用一主體金屬填充。對於一銅互連結構,可將一無電極或電鍍銅程序用於間隙填充。
在步驟50中,該結構係藉由如化學機械平坦化(CMP)或
回蝕程序的任何適合技術,移除導電材料之過量部分來平坦化。
鑲嵌製程可為一單一或雙倍(雙重)鑲嵌程序。對於後一程序,可使用通道先方法或溝渠先方法。
理想中,擴散阻障材料可防止銅原子遷移進入圍繞之介電材料內,以及具有與銅之低溶解度,而不形成任何金屬間化合物。範例性阻障材料包括鉭(Ta)、氮化鉭(TaN)、釕(Ru)、氧化釕(RuOx)及其合金。用於擴散阻障之其他候選材料亦可包括鉻(Cr)、鉬(Mo)、鎢(W)及錸(Re)。例如,阻障材料可藉由物理汽相沈積(PVD)、原子層沈積(ALD)或類似者塗布。
物理汽相沈積(PVD)係一塗布技術,其特徵係來自低壓下的一來源之原子或分子的蒸鍍。原子或分子之產生可藉由從一來源蒸鍍或在一來源(或目標)處導引高能氣體離子以噴濺該等原子或分子。此等原子或分子撞擊及凝結在一基板表面上以形成薄膜。若PVD係在一反應氣體之出現時執行,一化合物會在基板上沈積(如在氮大氣中鉭的沈積會形成TaN)。此沈積技術提供以較低深寬比(小於2)等形地及均勻地塗布開口之能力。
隨著電晶體器件尺寸持續縮小,用於互連線之開口(如溝渠、接點或通道)的深寬比持續增加(如大於2)。當使用PVD以一用更高深寬比塗布開口時,可能在達到均勻薄膜厚度方面產生困難。因此,以高深寬比開口來沈積阻障層時餘留的挑戰之一係在此等開口中塗布一等形阻障層的能
力。
原子層沈積(ALD)係一提供以更高深寬比(大於2)等形地塗布開口之能力的解決技術。ALD係一其中反應物被引入一沈積室(一次一單一前驅物)以反應及形成薄膜的自限制塗布技術。一第一前驅物被脈衝進入該室,使基板表面飽和,之後透過滌洗氣之引入來移除任何過量前驅物。一第二前驅物係接著脈衝進入該室,與第一前驅物反應,形成該薄膜之一單一單層。過量之第二前驅物及任何反應產物係透過一滌洗氣之引入移除。該程序可重複所需次數直至達成一所需膜厚度。
雖然鉭、氮化鉭、釕及氧化釕係極佳阻障材料,但若不正確地控制阻障層表面以在晶種層沈積前與期間防止氧化,則結構可能脫層,不管所使用之沈積技術為何。例如,鉭對氧化鉭之形成敏感。雖然銅係良好地黏著至鉭,但若形成在氧化鉭上銅層常會脫層,導致互連的退化。一旦形成氧化鉭,將難以使其還原至其金屬狀態。因此,在整個沈積程序中極需要仔細地控制至一氧氣環境之曝露。
此外,由於不良之黏著特性,不同材料之阻障層可能與作為晶種層之銅不相容。例如,氮化鉭及氧化釕作為用於銅覆蓋沈積之黏著層傾向於作用不佳。在氮化鉭之情況下,必須施加一黏著至氮化鉭及銅兩者之覆蓋鉭層。同樣地,在氧化釕之情況下,一黏著至氧化釕及銅兩者之覆蓋釕層可在此氧化釕層上形成。
圖2係一其中介電層70沈積在一基板60上之互連結構的
範例性具體實施例。例如,可藉由CVD沈積或使用旋塗技術來沈積介電層70。基板60可為一單晶矽晶圓。較佳係,介電層70係低k介電質(k<3.0),如k小於2.5、小於2.0或小於1.5。適合之低k介電材料的範例包括SiO2
/矽氧烷衍生物,如與F-及C-摻雜之有機矽酸玻璃(OSG)氧化物,如FLOWFILL(由Trikon製造)、BLACK DIAMOND(由Applied Materials製造)、CORAL(由Novellus製造)、AURORA(由ASMI製造),有機聚合物,例如JSR(由JSR製造)及SiLK(由Dow Chemical製造),或中孔玻璃,其係設計具有成孔劑(Porogen)以增強低k特性。亦可將更高介電常數材料(k=3.8至4.0)用作接觸層,包括硼磷矽酸玻璃(BPSG)及四乙氧基矽(TEOS)。可在介電層70上沈積及圖案化一例如光阻層(未顯示)之掩膜層,之後藉由蝕刻以形成開口80。在一範例性具體實施例中,開口80可為通道、接點或溝渠。
如圖3中所見,第一阻障層90係沈積在至少介電質70中之開口80壁表面側上。若開口80具有一相對較高深寬比(如大於2),較佳係使用ALD技術沈積第一阻障層90。藉由一次沈積第一阻障層材料90之一單層,ALD提供沈積幾乎完美等形膜的能力。對於銅互連,範例性適合之阻障材料包括鉭(Ta)、氮化鉭(TaN)或其任何結合。在一具體實施例中,TaN初始藉由ALD沈積成為厚度在約20及40間之第一阻障層90。
為了藉由ALD沈積氮化鉭,鉭前驅物係脈衝進入反應
室,其係維持在一約100 mTorr至約3 Torr的壓力。基板被加熱至一約150℃至約300℃的溫度。脈衝時間之範圍可從約100毫秒至約3秒,使得開口80之至少側壁表面係用一鉭前驅物的單層飽和。反應室係用氬氣沖洗,(例如)之後藉由引入一含氮氣體,以如同用於鉭前驅物之類似脈衝時間。鉭前驅物及含氮氣體反應以形成氮化鉭之一極微薄、等形層。當用一惰性氣體(如氬)沖洗反應室時係移除過量氣體及反應產物。可重複循環直至達成氮化鉭之適當厚度。ALD沈積技術可包括熱ALD、電漿增強ALD或熱絲ALD。電漿增強ALD可包括直接及遠端電漿兩者。
鉭前驅物之範例可包括五(乙甲胺)鉭(PEMAT)、五(二乙胺)鉭(PDEAT)、五(二甲胺)鉭(PDMAT)、三級丁亞胺參(二乙胺)鉭(TBTDET)、三級丁亞胺三(乙甲胺)鉭(TBTEMT)、鹵化鉭(即五氟化鉭、五氯化鉭、五溴化鉭)及其衍生物。含氮氣體之範例可包括氨或N,N二甲聯胺。
如圖4中顯示,含鉭及氮之第一阻障層90係進行氫還原以產生一富含鉭區90B(即Tax
Ny
,其中x>y)及氮化鉭區90A。如圖4中說明,富含鉭區90B覆蓋氮化鉭區90A,氮化鉭區90A係插入於介電材料70與富含鉭區90B之間。氮化鉭區90A之氮含量大於富含鉭區90B的氮含量。富含鉭區90B例如改進第一阻障層90至任何覆蓋金屬(例如釕或銅)的黏著。氫還原可藉由熱氫還原或藉由曝露至一含氫電漿執行,如以下描述。
在一範例性具體實施例中,含鉭及氮之第一阻障層90可
經電漿處理,如在一感應耦合或遠端來源(下游)電漿裝置中,以在氮化鉭中形成一富含鉭區(例如富含鉭區90A)。用於電漿處理之程序氣體可包括氫(H2
)、氨(NH3
)及惰性載體氣體,例如氬(Ar)或氦(He),其中總氣體流率從約100 sccm至約500 sccm。氫之流率範圍可從約100 sccm至200 sccm。氨之流率範圍可高達約100 sccm。惰性氣體之流率可高達約500 sccm。室壓可在一從約5 mTorr至約50 mTorr之範圍中,其中晶圓溫度在從約10℃至約200℃之範圍中。處理時間之範圍可從約15秒至約150秒,較佳係約75秒。為了產生該電漿,一在約200 W至約2000 W間之射頻(RF)功率,可在約2 MHz至約27.3 MHz之範圍的頻率處施加。
對於在一感應耦合電漿裝置中產生之氫或氫/氦電漿,可藉由一底部電極以400 kHz至約27.3 MHz之RF頻率施加一RF偏壓功率(高達約100 W)至晶圓。對於200 mm直徑晶圓,可施加高達50 W之偏壓功率。然而,當施加一RF偏壓功率時,較重之惰性氣體(如氬)應從程序氣體中排除,因為濺鍍效應可損及較薄的氮化鉭層。
在一替代具體實施例中,氮化鉭可在一電容耦合平行板電漿裝置中處理。程序氣體可包括具有範圍從約100 sccm至約1000 sccm之總氣體流的氫(H2
)、氨(NH3
)及氦(He)。室壓可在自約100 mTorr至約500 mTorr之範圍中,其中晶圓溫度範圍從約10℃至約200℃。為了產生該電漿,一在約100 W至約1000 W間之RF功率可在約13.56 MHz至約60
MHz之頻率處施加。可施加一高達約200 W且頻率在約400 kHz至約2 MHz間的RF偏壓功率。然而,當施加RF偏壓功率時,較重之惰性氣體(如氬)應從程序氣體中排除,因為濺鍍效應可損及較薄的氮化鉭層。
在另一具體實施例中,氮化鉭可在下游或遠端電漿處理裝置中處理。對於此等處理,程序氣體包括具有從約100 sccm至約2000 sccm之總氣體流的氫(H2
)、氨(NH3
)、氦(He)及氬(Ar)。程序壓力可在從約5 Torr至約2 Torr之範圍中,其中程序溫度範圍從約20℃至約200℃。一在約500 W至約2500 W間之RF功率可在約400 kHz至約2.56 MHz之頻率處施加。由於該遠端電漿來源,較薄氮化鉭層將不受到較重元素(例如氬)噴濺。
一旦富含鉭區90B已在阻障層90內產生,一覆蓋層係立即沈積以防止氧化鉭的形成。為了防止氧化鉭形成,富含鉭區90B較佳係於沈積任何覆蓋膜前保持在受控制大氣(即低氧環境,例如真空大氣)中。
如圖5中說明,第二阻障層100可沈積在第一阻障層90上以進一步增強阻障性質。例如,第二阻障層100可為一氧擴散減少材料,例如釕。若開口80具有一相對較高深寬比(如大於2),第二阻障層100較佳係使用ALD技術沈積。在一具體實施例中,釕係以在約20至約40間之厚度藉由ALD初始沈積成為第二阻障層100。
為了藉由ALD沈積釕,釕前驅物被脈衝進入一反應室,其係維持在約100 mTorr至約3 Torr的壓力下。基板被加熱
至一約150℃至約300℃的溫度。脈衝時間範圍可從約100毫秒至約3秒,使得基板表面係用一釕前驅物的單層飽和。反應室係用惰性氣體(例如氬)沖洗,之後藉由引入氫(H2
)氣體,以如同用於釕前驅物之類似脈衝時間。釕前驅物及氫氣體反應以形成釕之一極微薄、等形層。當用性氣體(如氬)沖洗反應室時會移除過量氣體及反應產物。可重複該循環直至達到釕之適當厚度。ALD沈積技術可包括熱ALD、電漿增強ALD或熱絲ALD。電漿增強ALD可包括直接及遠端電漿兩者。或者是,可將氨(NH3
)用作氫來源以與釕前驅物反應。
釕前驅物的範例包括雙(環戊二烯)釕(RuCp2
)、雙(乙環戊二烯)釕(Ru(CpEt)2
)或其衍生物。
如以上描述,氧化釕係用於任何後續無電極銅電鍍之不良催化表面。然而,與釕比較,氧化釕可提供對於銅遷移的增強擴散阻障性質。此阻障效應係由於沿氧化釕中晶粒邊界之銅擴散的減少。因此,其一方法係形成一Ru/RuOx/Ru複合物作為第二阻障層100。此複合第二阻障層100提供:(i)保護下方鉭或TaN層,防止氧化;(ii)改進氧化釕之阻障性質;及(iii)後續無電極銅電鍍之適當催化表面。
含釕之第二阻障層100係進行氧化以產生氧化釕區100B及釕區100A。如圖6中說明,氧化釕100B覆蓋釕區100A,釕區100A係插入於第一阻障層90與氧化釕區100B之間。例如,氧化釕區100B厚度範圍可從約10至約15。氧化
釕區100B改進對於銅遷移之擴散阻障性質,如以上描述。
在一範例性具體實施例中,氧化技術包括以氧氣(O2
)、一氧化碳(CO)或二氧化碳(CO2
)程序氣體(個別或其結合)之電漿處理。視需要,一或多種稀釋氣體(如氦或氬)可增加至程序氣體。可在一感應耦合電漿裝置、電容耦合電漿裝置、下游電漿裝置或類似者中執行電漿處理。
參考圖7,氧化釕區100B係其次進行氫還原以產生富含釕區100C。由於氫還原,氧化釕區100B之氧含量係大於富含釕區100C的氧含量。在一具體實施例中,富含釕區100C可為釕金屬。如圖示,富含釕區100C覆蓋氧化釕區100B,氧化釕區100B插入於釕區100A與富含釕區100C之間。例如,富含釕區100C的厚度可為約一單層之厚度。在另一具體實施例中,富含釕區100C之厚度範圍可從約5Å至約10Å。富含釕區100C提供用於後續無電極銅電鍍之適當催化表面,如以上描述。
氧化釕的氫還原可藉由熱還原或藉由曝露至一含氫電漿執行,類似以上針對還原氮化鉭描述之方法。在一範例性具體實施例中,氫還原技術包括具有氫(H2
)、氨(NH3
)、氦(He)或氬(Ar)程序氣體(個別或其結合)之電漿處理。可在一感應耦合電漿裝置、電容耦合電漿裝置、下游電漿裝置或類似者中執行電漿處理。
如圖8中說明,一銅晶種層110係沈積在富含釕區100C上。例如,銅晶種層110可使用PVD或無電極電鍍技術沈積。在銅晶種層110之沈積後,開口80係用一主體金屬120
填充以形成互連結構,如圖9中說明。例如,開口可使用銅無電極或電鍍程序以銅主體金屬120填充。無電極銅電鍍程序之細節係描述於共同受讓之美國專利申請案第11/461,415號中,其標題為"透過無電極銅電鍍形成圖案化銅線之系統及方法(System and Method for Forming Patterned Copper Lines Through Electroless Copper Plating)",其內容藉由引用全數併入本文。
如圖10中說明,任何過量主體金屬120可藉由平坦化技術移除,例如化學機械拋光(CMP)或回蝕。
如以上描述,對於介面性質之控制(包括對於氧化的控制)允許形成一高品質介面。控制介面品質之一方法係減少剛沈積或剛處理層對於含氧環境的曝露。其一方法係在一大氣經控制之模組化程序工具內執行所有程序步驟(如ALD、電漿處理),以使氧氣曝露減至最少。此模組化程序工具亦描述於共同受讓之美國專利申請案第11/461,415號,及共同受讓之美國專利申請案第11/514,038號,其標題為"工程設計用於銅沈積之阻障表面的程序與系統(Process and System for Engineering a Barrier Surface for Copper Deposition)",其內容藉由引用全數併入本文。
圖11說明具有連接至處理室220至270之轉移室210的模組化程序工具200的簡化示意圖。轉移室210具有一經控制大氣及可維持在低壓力下或以一惰性氣體(如氦、氮或氬)填充。轉移室210亦可配有機器人以在處理室220至270之各室間轉移晶圓。在一範例性組態中,處理室220至270可
為:(i)一ALD反應器220,用於氮化鉭的沈積;(ii)氫還原室230(即熱還原室或含氫電漿處理裝置);(iii)一ALD反應器240,用於釕沈積;(iv)氧化室250(即含氧電漿處理裝置);(v)一銅晶種層沈積室260(即PVD)及/或(vi)無電極銅電鍍系統270。藉由原地使用模組化程序工具200實施圖2至9中的程序步驟,可使剛沈積或剛處理之金屬的氧化減至最少。因此,在一真空環境中保持半導體基板時執行所有塗布及處理。
如以上描述,含鉭阻障層之氧化可能由於覆蓋金屬之不良黏著而受害。此外,氧化鉭係難以還原至其金屬狀態。例如,當在一ALD反應器220中形成含鉭及氮的第一阻障層90後,可使用轉移室210中之機器人系統轉移晶圓至一用於氫還原之分離室。同樣地,在含鉭及氮的第一阻障層90於氫還原室230進行氫還原以產生富含鉭區90B後,可將晶圓轉移至ALD反應器240以用於沈積一覆蓋釕阻障層100。因為基板係透過轉移室210予以轉移,所以在經控制大氣(即低氧含量)下,可使含鉭及氮的第一阻障層90及富含鉭區90B的氧化減至最少。
儘管已相對於本發明特定具體實施例詳述本發明,熟習此項技術人士將會瞭解可在不脫離隨附申請專利範圍之範疇下進行各種改變及修改及使用等效者。
60‧‧‧基板
70‧‧‧介電層
80‧‧‧開口
90‧‧‧第一阻障層
90A‧‧‧氮化鉭區
90B‧‧‧富含鉭區
100‧‧‧第二阻障層
100A‧‧‧釕區
100B‧‧‧氧化釕區
100C‧‧‧富含釕區
110‧‧‧銅晶種層
120‧‧‧主體金屬
200‧‧‧模組化程序工具
210‧‧‧轉移室
220‧‧‧處理室/ALD反應器
230‧‧‧處理室/氫還原室
240‧‧‧處理室/ALD反應器
250‧‧‧處理室/氧化室/含氧電漿處理裝置
260‧‧‧處理室/銅晶種層沈積室
270‧‧‧處理室/無電極銅電鍍系統
圖1係一說明製造一鑲嵌結構之方法的範例性具體實施例之流程圖。
圖2至9係製造一鑲嵌結構之方法的範例性具體實施例之斷面圖,該鑲嵌結構包括一形成在一介電材料中之開口且包括塗布及處理步驟。
圖10係一具有受控制大氣之模組化程序工具的簡化示意圖。
圖11係一具有一連接至複數個處理室的轉移室之模組化程序工具之簡化示意圖。
(無元件符號說明)
Claims (20)
- 一種互連結構,其包含:一層介電材料,其具有至少一開口;一第一阻障層,其位於定義該開口之側壁上;及一含釕及氧之第二阻障層,其覆蓋該第一阻障層,該第二阻障層具有由釕組成之一釕區、一氧化釕區,及一富含釕區,該釕區係插入於該第一阻障層與該氧化釕區之間,且該氧化釕區係插入於該釕區與該富含釕區之間。
- 如請求項1之互連結構,其進一步包含一晶種層,該晶種層係在該第二阻障層上;及一主體金屬,其填充整個開口,其中該晶種層及主體金屬係由銅或一銅合金組成。
- 如請求項1之互連結構,其中:(i)該富含釕區由釕組成;(ii)該開口係一溝渠、接點或通道;(iii)該介電材料係一低k介電質或一較高k介電質;(iv)該結構係一雙重鑲嵌結構或一接點結構;及/或(v)第一阻障材料係鉻、鉬、鎢、鉭或錸。
- 一種互連結構,其包含:一層介電材料,其具有至少一開口;一含鉭及氮的第一阻障層,其位於定義該開口之側壁上,該第一阻障層具有一富含鉭區及一氮化鉭區,其中該鉭氮化物區之氮含量係大於該富含鉭區之氮含量,該 氮化鉭區係插入於該介電材料與該富含鉭區之間;及一含釕及氧之第二阻障層,其覆蓋該第一阻障層,該第二阻障層具有由釕組成之一釕區、一氧化釕區,及一富含釕區,該釕區係插入於該富含鉭區與該氧化釕區之間,且該氧化釕區係插入於該釕區與該富含釕區之間。
- 如請求項4之互連結構,其進一步包含:一晶種層,該晶種層係在該第二阻障層上;及一主體金屬,其填充該整個開口,其中該晶種層及主體金屬係由銅或一銅合金組成。
- 如請求項4之互連結構,其中:(i)該開口係一溝渠、接點或通道;及/或(ii)該介電材料係一低k介電質或一較高k介電質。
- 如請求項6之互連結構,其中該低k介電質材料係一有機矽酸玻璃(OSG)、一氟化矽玻璃(FSG)、一碳摻雜氧化物、一中孔玻璃或一有機聚合物。
- 如請求項6之互連結構,其中較高k介電質材料係硼磷矽酸玻璃(BPSG)或四乙氧基矽(TEOS)。
- 如請求項6之互連結構,其中:(i)該富含釕區由釕組成;(ii)該第一阻障層具有一範圍從約20Å至約40Å之厚度;(iii)該富含鉭區具有一範圍從約5Å至約15Å之厚度;(iv)該第二阻障層具有一範圍從約20Å至約40Å之厚度; (v)該氧化釕區具有一範圍從約5Å至約15Å之厚度;(vi)該富含釕區具有一約一單層之厚度或一範圍從約5Å至約10Å之厚度;及/或(vii)該結構係一雙重鑲嵌結構。
- 一種於一半導體基板上製造一鑲嵌結構的方法,其包含:在一介電材料中形成至少一開口;用一含鉭及氮之第一阻障層塗布定義該開口之側壁;處理該第一阻障層以形成一富含鉭區及一氮化鉭區,其中該氮化鉭區之氮含量係大於該富含鉭區的氮含量,該氮化鉭區係插入於該介電材料與該富含鉭區之間;用一含釕之第二阻障層塗布該第一阻障層;處理該第二阻障層以形成一氧化釕區及由釕組成之一釕區,該釕區係插入於該富含鉭區與該氧化釕區之間;及處理該氧化釕區以形成一富含釕區,該氧化釕區係插入於該釕區與該富含釕區之間。
- 如請求項10之方法,其進一步包含:在該第二阻障層上塗布一銅晶種層;用銅填充該開口;及平坦化該介電質材料之一頂部表面。
- 如請求項10之方法,其中該第一阻障層之該等側壁係藉由原子層沈積(ALD)、熱ALD、電漿增強ALD或熱絲ALD予以塗布。
- 如請求項12之方法,其中該ALD係以由五(乙甲胺)鉭 (PEMAT)、五(二乙胺)鉭(PDEAT)、五(二甲胺)鉭(PDMAT)、三級丁亞胺參(二乙胺)鉭(TBTDET)、三級丁亞胺三(乙甲胺)鉭(TBTEMT)及鹵化鉭組成之群組中選出之一鉭前驅物予以執行。
- 如請求項10之方法,其中該第一阻障層之該處理係藉由氫還原或藉由熱氫還原或藉由曝露至一含氫電漿予以執行。
- 如請求項14之方法,其中該含氫電漿係在一感應耦合電漿裝置、一電容耦合電漿裝置或一下游電漿處理裝置中予以產生。
- 如請求項10之方法,其中該第二阻障層係藉由原子層沈積(ALD)、熱ALD、電漿增強ALD或熱絲ALD予以形成。
- 如請求項16之方法,其中該ALD係用一雙(環戊二烯)釕(RuCp2 )或一雙(乙環戊二烯)釕(Ru(CpEt)2 )前驅物予以執行。
- 如請求項10之方法,其中處理該第二阻障層以形成該氧化釕區係藉由曝露至一含氧電漿予以執行。
- 如請求項10之方法,其中該氧化釕區之該處理以形成該富含釕區係藉由氫還原或藉由熱氫還原或藉由曝露至一含氫電漿予以執行。
- 如請求項10之方法,其中所有塗布及處理係在原地分離室中執行,而維持該半導體基板在一真空環境中。
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Also Published As
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CN101558476B (zh) | 2014-08-20 |
US20080142971A1 (en) | 2008-06-19 |
KR101468241B1 (ko) | 2014-12-03 |
SG177215A1 (en) | 2012-01-30 |
CN101558476A (zh) | 2009-10-14 |
KR20090094369A (ko) | 2009-09-04 |
WO2008073245A1 (en) | 2008-06-19 |
TW200834815A (en) | 2008-08-16 |
US20110306203A1 (en) | 2011-12-15 |
US8026605B2 (en) | 2011-09-27 |
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