JP5726693B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- PXHVJJICTQNCMI-UHFFFAOYSA-N nickel Substances [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Description
Claims (19)
- 基板上に、前記基板上の下側誘電体層、前記下側誘電体層上の金属層、前記金属層上の上側誘電体層、前記上側誘電体層上の平坦化層、前記平坦化層上のフォトレジスト材料の層を有する構造を形成することと、
マスク・パターンに従って前記フォトレジスト材料を現像することと、
前記マスク・パターンに従って前記平坦化層および前記上側誘電体層をエッチングする
ことと、
前記平坦化層および前記上側誘電体層のエッチングの後に前記フォトレジスト材料および前記平坦化層を除去することと、
前記上側誘電体層のエッチングに続いて前記金属層の各露出した部分に選択的金属成長を適用して前記選択的金属成長からなる反転されたマスク・パターンを得ることと、
前記反転されたマスク・パターンに従って少なくとも前記金属層および前記下側誘電体層をエッチングすることと、
を具備する装置を製造する方法。 - 前記金属層および前記下側誘電体層をエッチングする前に前記上側誘電体層を除去することをさらに具備する、
請求項1の方法。 - 前記適用することが、無電解めっき、エピタキシャル成長、CVD、PVD、またはALDの少なくとも1つによって前記選択的金属成長を適用することを具備する、
請求項1の方法。 - 前記上側誘電体層が、約10nmおよび約100nmの間の厚さを有し、
前記金属層が、約5nmおよび約20nmの間の厚さを有する、
請求項1の方法。 - 前記適用することが、Co、Ni、Cu、Fe、Ru、Rh、Pd、Ag、Os、Ir、Sn、Pb、Pt、およびAuからなる群から選択された少なくとも1つの元素からな
る選択的金属成長を適用することを具備する、
請求項1の方法。 - 前記適用することが、少なくとも1つの主要金属および少なくとも1つの共に堆積される金属を具備する選択的金属成長を適用すること具備する、
請求項1の方法。 - 少なくとも1つの主要金属が、Co、Ni、Cu、Fe、Ru、Rh、Pd、Ag、Os、lr、Sn、Pb、Pt、およびAuからなる群から選択された少なくとも1つの元素からなり、
前記少なくとも1つの共に堆積される金属が、V、Cr、Mn、Mo、Tc、W、Rc、In、Ti、Zn、Si、Ge、およびBからなる群から選択された少なくとも1つの元素からなる、
請求項6の方法。 - 前記金属層および前記下側誘電体層のエッチングに続いて前記選択的金属成長および前記金属層を除去することと、
前記下側誘電体層の前記下側誘電体層のエッチングの結果除去された部分を金属化することと、
前記金属化の完了後に前記下側誘電体層上にキャップ層を形成することと、
をさらに具備する、請求項1の方法。 - 基板上に、前記基板上の下側誘電体層、前記下側誘電体層上の金属層、前記金属層上の上側誘電体層、前記上側誘電体層上の平坦化層、前記平坦化層上のフォトレジスト材料の層を有する構造を形成することと、
マスク・パターンに従って前記フォトレジスト材料を現像することと、
前記マスク・パターンに従って前記平坦化層および前記上側誘電体層をエッチングすることと、
前記平坦化層および前記上側誘電体層のエッチングの後に前記フォトレジスト材料および前記平坦化層を除去することと、
前記上側誘電体層のエッチングに続いて前記上側誘電体層上および前記金属層の各露出した部分上に金属または有機膜を堆積することと、
前記金属または有機膜の前記上側誘電体層上の部分を除去して前記金属または有機膜からなる反転されたマスク・パターンを得ることと、
前記反転されたマスク・パターンに従って少なくとも前記金属層および前記下側誘電体層をエッチングすることと、
を具備する装置を製造する方法。 - 前記金属層および前記下側誘電体層をエッチングする前に前記上側誘電体層を除去することをさらに具備する、
請求項9の方法。 - 前記堆積することが、無電解めっき、エピタキシャル成長、CVD、PVD、またはALDの少なくとも1つによって前記金属または有機膜を堆積することを具備する、請求項9の方法。
- 前記上側誘電体層が、約10nmおよび約100nmの間の厚さを有し、
前記金属層が、約5nmおよび約20nmの間の厚さを有する、
請求項9の方法。 - 前記金属または有機膜が、W、Cu、Ti、TiN、Ru、Ta、TaN、Co、Ni、およびSiからなる群から選択された材料、W、Cu、Ti、TiN、Ru、Ta、TaN、Co、Ni、およびSiからなる群から選択された材料と結合した炭素、またはW、Cu、Ti、TiN、Ru、Ta、TaN、Co、Ni、およびSiからなる群から選択された材料と結合した合金、の少なくとも1つからなる金属膜である、
請求項9の方法。 - 前記金属または有機膜がアモルファス炭素からなる有機膜である、
請求項9の方法。 - 前記金属または有機膜が約10nmおよび約300nmの間の厚さを有する、
請求項9の方法。 - 前記堆積することが、
上側誘電体層のエッチングに続いて、前記上側誘電体層上および前記金属層の露出した部分上に金属または有機膜の初期層を堆積することと、
前記金属または有機膜の初期層上に金属または有機膜の主要層を堆積することと、
を具備する、請求項9の方法。 - 前記金属または有機膜の初期層が、Ti、TiN、Ta、またはTaNの少なくとも1つからなる、
請求項16の方法。 - 前記金属または有機膜の初期層が約1nmおよび約10nmの間の厚さを有する、
請求項16の方法。 - 前記金属層および前記下側誘電体層のエッチングに続いて前記金属または有機膜および前記金属層を除去することと、
前記下側誘電体層の前記下側誘電体層のエッチングの結果除去された部分を金属化することと、
前記金属化の完了後に前記下側誘電体層上にキャップ層を形成することと、
をさらに具備する、請求項9の方法。
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US12/886,106 | 2010-09-20 | ||
US12/886,106 US8138097B1 (en) | 2010-09-20 | 2010-09-20 | Method for processing semiconductor structure and device based on the same |
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JP2012064945A JP2012064945A (ja) | 2012-03-29 |
JP5726693B2 true JP5726693B2 (ja) | 2015-06-03 |
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JP (1) | JP5726693B2 (ja) |
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US8497210B2 (en) * | 2010-10-04 | 2013-07-30 | International Business Machines Corporation | Shallow trench isolation chemical mechanical planarization |
US8470711B2 (en) * | 2010-11-23 | 2013-06-25 | International Business Machines Corporation | Tone inversion with partial underlayer etch for semiconductor device formation |
TWI549234B (zh) * | 2014-01-17 | 2016-09-11 | 矽品精密工業股份有限公司 | 用於接置半導體裝置之層結構及其製法 |
US9778561B2 (en) | 2014-01-31 | 2017-10-03 | Lam Research Corporation | Vacuum-integrated hardmask processes and apparatus |
US9385030B2 (en) * | 2014-04-30 | 2016-07-05 | Globalfoundries Inc. | Spacer to prevent source-drain contact encroachment |
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JP6489951B2 (ja) | 2015-06-12 | 2019-03-27 | 東芝メモリ株式会社 | 半導体装置の製造方法 |
US9368350B1 (en) | 2015-06-23 | 2016-06-14 | International Business Machines Corporation | Tone inverted directed self-assembly (DSA) fin patterning |
US9705077B2 (en) | 2015-08-31 | 2017-07-11 | International Business Machines Corporation | Spin torque MRAM fabrication using negative tone lithography and ion beam etching |
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JP6559046B2 (ja) * | 2015-11-04 | 2019-08-14 | 東京エレクトロン株式会社 | パターン形成方法 |
US10453701B2 (en) * | 2016-06-01 | 2019-10-22 | Asm Ip Holding B.V. | Deposition of organic films |
US9916986B2 (en) | 2016-06-27 | 2018-03-13 | International Business Machines Corporation | Single or mutli block mask management for spacer height and defect reduction for BEOL |
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JP5086283B2 (ja) * | 2008-02-15 | 2012-11-28 | 東京エレクトロン株式会社 | パターン形成方法及び半導体装置の製造方法 |
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