TWI550812B - 用於積體電路的結構與積體電路的製作方法 - Google Patents

用於積體電路的結構與積體電路的製作方法 Download PDF

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TWI550812B
TWI550812B TW104101436A TW104101436A TWI550812B TW I550812 B TWI550812 B TW I550812B TW 104101436 A TW104101436 A TW 104101436A TW 104101436 A TW104101436 A TW 104101436A TW I550812 B TWI550812 B TW I550812B
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layer
trench
tan
pvd
barrier
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TW201545302A (zh
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李亞蓮
蘇鴻文
林瑀宏
李魁斌
張育民
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台灣積體電路製造股份有限公司
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Description

用於積體電路的結構與積體電路的製作方法
本發明關於半導體積體電路，更特別關於其阻障層之組成與形成方法。
半導體積體電路(IC)產業快速成長。IC材料與設計的技術進步，使IC更小且其電路更複雜。新一代的IC具有較大的功能密度(比如固定晶片面積中的內連線元件數目)，與較小的尺寸(比如製程形成的最小構件或連線)。製程尺寸縮小往往有利於增加製程效率並降低相關成本，但亦增加製程複雜度。然而製程尺寸縮小的優點顯而易見，因此需要發展更小的IC製程。
舉例來說，當裝置的關鍵尺寸(CD)下降，關鍵尺寸的任何偏差值都會變得更具有關聯性，比如造成IC裝置中的金屬結構之接觸電阻之偏差值。綜上所述，目前亟需新的方法以進一步縮小IC裝置的尺寸。
本發明一實施例提供之用於積體電路的結構，包括：基板；蓋層，沉積於基板上；介電層，沉積於蓋層上，以及溝槽，嵌入介電層中，其中溝槽包括：TaN層形成於溝槽的側壁上，其中TaN層之氮濃度高於鉭濃度；Ta層形成於TaN層 上；以及含銅層形成於Ta層上，其中TaN層與Ta層的總碳濃度小於約0.2%。
本發明一實施例提供之用於積體電路的結構，包括：基板；第一蓋層，形成於基板上；第一介電層，形成於第一蓋層上；第一溝槽，嵌入第一介電層中，其中第一溝槽包括：第一TaN層，沉積於第一溝槽的底部與側壁上，其中第一TaN層之氮濃度高於鉭濃度；第一Ta層，沉積於第一TaN層上；以及第一含銅層，形成於第一Ta層上；第二蓋層，形成於第一介電層上；第二介電層，形成於第一介電層上；第二溝槽，嵌入第二介電層中，其中第二溝槽包括：第二TaN層，沉積於第二溝槽的底部與側壁上，其中第二TaN層之氮濃度高於鉭濃度；第二Ta層，沉積於第二TaN層上；以及第二含銅層，形成於第二鉭層上；以及通孔，位於第一溝槽與第二溝槽之間，其中通孔整合至第一溝槽的頂部中，並整合至第二溝槽的底部中。
本發明一實施例提供之積體電路的製作方法，包括：沉積蓋層於基板上；沉積介電層於蓋層上；形成溝槽於介電層中；以及填滿溝槽，包括：沉積第一阻障層於溝槽之底部與側壁上，且第一阻障層係以至少20sccm之氮氣流物理氣相沉積的TaN；沉積第二阻障層於第一阻障層上，且第二阻障層係物理氣相沉積的Ta；以及沉積金屬層於第二阻障層上。
M1、112、318‧‧‧第一溝槽金屬
M2、128、340‧‧‧第二溝槽金屬
100‧‧‧第一裝置
102、302‧‧‧基板
104、304‧‧‧第一蓋層
106、306‧‧‧第一介電層
108、312‧‧‧第一溝槽
110‧‧‧第一溝槽金屬阻障層
114、320‧‧‧第二蓋層
116、322‧‧‧第二介電層
118、332‧‧‧通孔
120‧‧‧通孔金屬阻障層
124、334‧‧‧第二溝槽
126‧‧‧第二溝槽金屬阻障層
200‧‧‧方法
202、206、208、210、212、214、216、218、220、222、224、226‧‧‧步驟
300‧‧‧第二裝置
308‧‧‧第一硬遮罩層
310‧‧‧第一光阻圖案
314‧‧‧第一阻障層
316‧‧‧第二阻障層
324‧‧‧第二硬遮罩層
326‧‧‧第二光阻圖案
328‧‧‧溝槽
330‧‧‧第三光阻圖案
336‧‧‧第三阻障層
338‧‧‧第四阻障層
400‧‧‧比較圖
402、404‧‧‧接觸電阻
500、510、722、724、726、732、734、736、742、744、746‧‧‧圖
520、530、712、714、716‧‧‧譜線
600‧‧‧第三裝置
614、616、636、638‧‧‧阻障層
第1圖係本發明一或多個實施例中，裝置的剖視圖。
第2圖係本發明一或多個實施例中，裝置之製作方法的流 程圖。
第3至14圖係本發明一或多個實施例中，裝置於製程階段中的剖視圖。
第15圖係第1圖與第3至14圖之裝置的接觸電阻。
第16圖係第1圖與第3至14圖之裝置的不同元素比例。
第17圖係第1圖與第3至14圖之裝置的TaN化合物之X光繞射(XRD)分析。
第18圖係本發明一或多個實施例中，裝置的剖視圖。
第19圖係某些實施例中，第18圖之裝置的TaN/Ta化合物之X光繞射(XRD)分析。
第20圖係某些實施例中，第14圖與第18圖之裝置的片電阻。
第21與22圖係某些實施例中，第14圖與第18圖之裝置的接觸電阻。
下述揭露內容提供的不同實施例或實例可實施本發明的不同結構。下述特定構件與排列的實施例係用以簡化本發明而非侷限本發明。舉例來說，形成第一構件於第二構件上的敘述包含兩者直接接觸，或兩者之間隔有其他額外構件而非直接接觸。此外，本發明的多個實例中將採用重複標號及/或符號使說明簡化及明確，但這些重複不代表多種實施例中相同標號的元件之間具有相同的對應關係。
另一方面，空間性的相對用語如「下方」、「其下」、「較下方」、「上方」、「較上方」、或類似用語可用 於簡化說明某一元件與另一元件在圖示中的相對關係。空間性的相對用語可延伸至以其他方向使用之元件，而非侷限於圖示方向。元件亦可轉動90°或其他角度，因此方向性用語僅用以說明圖示中的方向。
為了方便比較，下述內容描述三種不同裝置。第一裝置100如第1圖所示，其形成方法採用物理氣相沉積(PVD)以沉積阻障層如鉭(Ta)與氮化鉭(TaN)於一或多個溝槽中。第二裝置300如第2至14圖所示，其形成方法採用不同的沉積技術如PVD、原子層沉積(ALD)、及/或化學氣相沉積(CVD)以沉積阻障層於一或多個溝槽中。第三裝置600如第18圖所示，其形成方法採用PVD以沉積阻障層如Ta與TaN於一或多個溝槽中。上述裝置差異將比較如下。
如第1圖所示，第一裝置100包含基板102、第一蓋層104沉積於基板102上、第一介電層106沉積於第一蓋層104上、第一溝槽108嵌入第一介電層106中、第二蓋層114沉積於第一溝槽108與第一介電層106上、第二介電層116沉積於第二蓋層114上、通孔118形成於第一溝槽108上並埋置於第二介電層116中、以及第二溝槽124形成於通孔118上並埋置於第二介電層116中。
第一溝槽108嵌入第一介電層106中。第一溝槽108包含第一溝槽金屬阻障層110沉積於第一溝槽108之底部與側壁上，以及第一溝槽金屬112填入第一溝槽108中的第一溝槽金屬阻障層110上。上述溝槽金屬亦可稱作金屬，而溝槽金屬阻障層亦可稱作金屬阻障層。
第一溝槽金屬阻障層110、通孔金屬阻障層120、與第二溝槽金屬阻障層126包含PVD之TaN層與PVD之Ta層。採用PVD之TaN層與PVD之Ta層作為金屬阻障層的第一溝槽金屬112或第二溝槽金屬128，其接觸電阻(Rc)取決於第一溝槽金屬112及/或第二溝槽金屬128之關鍵尺寸(CD)。當對應的溝槽金屬之關鍵尺寸增加時，其接觸電阻亦隨之增加。綜上所述，IC中的的溝槽金屬其接觸電阻變化，將明顯地影響IC效能。
第2至14圖關於如何形成第二裝置300，其接觸電阻低於第1圖之第一裝置100。上述製程僅稍微或完全不影響金屬線電阻率與後段製程可信度。
第2圖係本發明一或多個實施例中，形成第二裝置300之方法200。第3至14圖係採用方法200形成第二裝置300的剖視圖。
首先進行方法200之步驟202，形成層狀物的堆疊於基板302上，如第3圖所示。步驟202包含沉積第一蓋層304於基板302上、沉積第一介電層306於第一蓋層302上、與沉積第一硬遮罩層308於第一介電層306上。
在此實施例中，基板302包含晶圓，其可具有或不具有一或多個導電或非導電薄膜。晶圓為包含矽的半導體基板(換言之，其為矽晶圓)。在另一實施例中，晶圓可包含另一半導體元素如鍺；半導體化合物如碳化矽、砷化鎵、磷化鎵、磷化銦、砷化銦、及/或銻化銦；半導體合金如矽鍺合金、鎵砷磷合金、鋁銦砷合金、鋁鎵砷合金、鎵銦砷合金、鎵銦磷合金、及/或鎵銦砷磷合金。在又一實施例中，晶圓可為絕緣層上半 導體(SOI)。導電或非導電薄膜可包含絕緣材料或導電材料。舉例來說，導電材料包含金屬如鋁、銅、鎢、鎳、鈦、金、鉑、或上述之合金。絕緣材料可包含氧化矽或氮化矽。
基板302可包含多種掺雜結構如n型源極/汲極、p型源極/汲極、n型井區、及/或p型井區，其形成方法可為離子佈植或擴散。基板302可包含多種隔離結構如淺溝槽隔離(STI)，其形成方法包含蝕刻形成多種溝槽，再沉積介電材料以填入溝槽。基板302更包含用於製作半導體IC裝置的前段製程所形成的閘極與接觸孔。
在某些實施例中，第一蓋層304包含氮化矽(SixNy)。第一蓋層304用以避免金屬(如銅)擴散。第一介電層306包含介電材料，其可為有機物或無機物。在此實施例中，介電材料包含有機矽酮膠(OSG)，其介電常數介於約2.6至約2.65之間。低介電常數材料OSG的形成方法為前驅物之間的化學反應，比如二乙氧甲基矽烷(DEMS)與致孔劑如α-松油烯(ATRP)於氧電漿下反應後以紫外線硬化。第一介電層306可包含矽、碳、氧、與氫。第一硬遮罩層308包含氮化矽或金屬硬遮罩如Ti或TiN。其他合適材料亦可作為第一蓋層304、第一介電層306、與第一硬遮罩層308。
接著進行方法200之步驟206，形成第一光阻圖案310。如第4圖所示，第一光阻圖案310係形成於第一硬遮罩層308的頂部上，而第一硬遮罩層308係沉積於第一介電層306上。步驟206包含沉積第一光阻膜於第一硬遮罩層308上，其沉積方法可為旋轉塗佈製程。第一光阻膜亦包含正型光阻或負型 光阻。第一光阻膜亦包含單一光阻膜或多層光阻膜。步驟206亦包含在沉積第一光阻膜於第一硬遮罩層308之前，先進行脫水製程以增加第一光阻膜與第一硬遮罩層308之間的黏著性。脫水製程可包含高溫烘烤一段時間，或施加化學品如六甲基二矽氮烷(HMDS)至第一硬遮罩層308上。步驟206亦包含施加底部抗反射塗層(BARC)製程，以改善光阻圖案的輪廓。步驟206包含軟烘烤，以增加光阻膜的機械強度。
步驟206更包含採用微影曝光機台，對沉積於第一硬遮罩層308上的第一光阻膜進行曝光。微影曝光機台包含紫外光(UV)、深紫外光(DUV)、極紫外光(EUV)、或X光的機台。微影曝光機台亦包含電荷粒子機台如電子束寫入機台。步驟206亦包含採用光罩如二元光罩或相位移光罩(PSM)。相位移光罩可為交錯式相位移光罩(alt.PSM)或衰減型相位移光罩(att.PSM)。
步驟206亦包含以顯影液顯影曝光後之第一光阻膜，而顯影液可為氫氧化四甲基銨(TMAH)。顯影液亦為有機溶劑。步驟206亦包含曝光後烘烤(PEB)、顯影後烘烤(PDB)、或上述之組合。步驟206亦包含沖洗製程，以移除任何顯影殘留物。
接著進行方法200之步驟208，形成第一溝槽312如第5圖所示。步驟208包含蝕刻移除第一光阻圖案310未覆蓋的部份第一硬遮罩層308。步驟208亦包含清潔製程以剝除第一光阻圖案310，並移除任何蝕刻殘留物。步驟208更包含以蝕刻製程形成第一溝槽312。第一溝槽312穿過第一介電層306與第一 蓋層304以延伸至基板302的接點區(比如嵌入基板302中的閘極、源極、汲極、或電容)。
接著進行方法200之步驟210，將導電材料填入第一溝槽312中。步驟210包含沉積金屬阻障於第一溝槽312之底部與側壁上。在此實施例中，金屬阻障包含多個層狀物，其形成方法採用多個沉積製程。如第6圖所示，步驟210包含沉積第一阻障層314於第一溝槽312之底部與側壁上，其形成方法為原子層沉積(ALD)或化學氣相沉積(CVD)。步驟210亦包含沉積第二阻障層316於第一阻障層314上，其形成方法為沉積製程如PVD製程。在一實施例中，第二阻障層316只包含PVD的Ta層而無PVD的TaN層。在另一實施例中，第二阻障層316包含PVD的Ta層與PVD的TaN層。上述兩實施例均包含PVD的Ta層，但視情況採用PVD的TaN層。可以理解的是，可進一步新增更多阻障層。值得注意的是以ALD製程形成的TaN層為「ALD的TaN層」，以CVD製程形成的TaN層為「CVD的TaN層」，而以PVD製程形成的TaN層為「PVD的TaN層」，以此類推。更需要注意的是，PVD的TaN層不同於ALD的TaN層或CVD的TaN層如下述。
如第6圖所示，步驟210更包含將第一溝槽金屬318如銅填入第一溝槽312，其形成方法可為沉積製程如電鍍製程。在一實施例中，步驟210可包含沉積晶種層。
接著進行方法200之步驟212的化學機械研磨(CMP)製程。步驟212包含移除第6至7圖中第一溝槽312之外的第一溝槽金屬318、第二阻障層316、與第一阻障層314。步驟212亦包 含蝕刻移除第一硬遮罩層308。步驟212更包含以研磨墊與漿料進行研磨。步驟212亦包含刷磨清潔製程。如第7圖所示，第一溝槽金屬318係嵌入第一介電層306中。
接著進行方法200之步驟214，沉積層狀物的第二堆疊於第一溝槽金屬318上如第8圖所示，且第一溝槽金屬318嵌入第一介電層306中。步驟214包含沉積第二蓋層320於第一溝槽金屬318上、沉積第二介電層322於第二蓋層320上、以及沉積第二硬遮罩層324於第二介電層322上。
如第8圖所示，此實施例中的第二蓋層320包含氮化矽(SixNy)。第二蓋層320用以避免金屬(如銅)擴散於金屬層之間。第二介電層322可包含有機或無機的介電材料。在此實施例中，介電材料包含有機矽酮膠(OSG)，其介電常數介於約2.6至約2.65之間。低介電常數材料OSG的形成方法為前驅物之間的化學反應，比如二乙氧甲基矽烷(DEMS)與致孔劑如α-松油烯(ATRP)於氧電漿下反應後以紫外線硬化。第二介電層322可包含矽、碳、氧、及/或氫。第二介電層322與第一介電層306可為相同或類似材料。第二硬遮罩層324可與第包含氮化矽或金屬硬遮罩如Ti或TiN。其他合適材料亦可作為第二蓋層320、第二介電層322、與第二硬遮罩層324。
接著進行方法200之步驟216，形成第二光阻圖案326如第9圖所示。第二光阻圖案326係形成於第二硬遮罩層324的頂部上，而第二硬遮罩層324係沉積於第二介電層322上。步驟216與第4圖中形成第一光阻圖案310之步驟206相同或類似。
接著進行方法200之步驟218，形成溝槽328如第10 圖所示。步驟218包含蝕刻移除第二光阻圖案326未覆蓋的部份第二硬遮罩層324。步驟218亦包含蝕刻至第二介電層中，如第10圖所示。步驟218更包含以清潔製程剝除第二光阻圖案326與移除蝕刻殘留物。
接著進行方法200之步驟220，形成第三光阻圖案330如第11圖所示。第三光阻圖案330係形成於溝槽328與第二硬遮罩層324的頂部上。步驟220與第4圖中形成第一光阻圖案310之步驟206相同或類似。
接著進行方法200之步驟222，形成通孔332與第二溝槽334如第12圖所示。步驟222包含蝕刻穿過第二介電層322與第二蓋層320至第一溝槽金屬318，其蝕刻製程搭配第三光阻圖案330。步驟222亦包含以清潔製程剝除第三光阻圖案330。步驟222更包含蝕刻第二介電層322，其蝕刻製程搭配第二硬遮罩層324。
接著進行方法200之步驟224，填滿通孔332與第二溝槽334如第13圖所示。步驟224包含以ALD或CVD沉積第三阻障層336於通孔332及第二溝槽334的底部與側壁上。在此實施例中，第三阻障層336接觸第一溝槽金屬318。步驟224亦包含沉積第四阻障層338於第三阻障層336上，其沉積製程可為PVD。步驟224更包含沉積第二溝槽金屬340於第四阻障層338上，且第二溝槽金屬340填滿溝槽332及第二溝槽334。上述沉積製程可為電鍍製程。在一實施例中，步驟224亦可包含沉積第二溝槽金屬340之晶種層。
在此實施例中，第三阻障層336包含沉積於通孔 332與第二溝槽334之底部與側壁上的TaN層，其沉積方法為ALD製程或CVD製程(ALD的TaN層或CVD的TaN層)。在一實施例中，第四阻障層338只包含PVD的Ta層，而無PVD的TaN層。在另一實施例中，第四阻障層338包含PVD的Ta層與PVD的TaN層。在此實施例中，第二溝槽金屬340包含電鍍製程形成的銅。第二溝槽金屬340可包含其他金屬或合金。
接著進行方法200之步驟226如化學機械研磨(CMP)製程。步驟226包含移除第二溝槽332之外的第三阻障層336、第四阻障層338、與第二溝槽金屬340，如第13至14圖所示。步驟226包含以研磨墊與漿料進行研磨。步驟226亦包含刷磨清潔製程。步驟226更包含蝕刻移除第二硬遮罩層324。在方法200之前、之中、或之後可進行其他步驟。在其他實施例中，可取代、省略、或移動方法200中的某些上述步驟。在此實施例中，可採用方法200形成更多的溝槽金屬層。
如第14圖所示，以方法200形成之第三裝置300包含基板302、第一蓋層304沉積於基板302上、第一介電層306沉積於第一蓋層304上、第一溝槽312嵌入第一蓋層304與第一介電層306中、第二蓋層320沉積於第一介電層306上、第二介電層322沉積於第二蓋層320上、通孔332整合於第一溝槽312之頂部上嵌入第二介電層322中。然而上述裝置可能具有其他組態。
如第14圖所示，第一溝槽312包含第一阻障層314沉積於第一溝槽312之底部與側壁上、第二阻障層316沉積於第一阻障層314上、與第一溝槽金屬318沉積於第二阻障層316上並填滿第一溝槽312。通孔332包含第三阻障層336沉積於第一 溝槽金屬318之頂部上及通孔332之側壁上、第四阻障層338沉積於第三阻障層336上、以及第二溝槽金屬340沉積於第四阻障層338上並填滿通孔332。第二溝槽334包含第三阻障層336沉積於第二溝槽334之側壁上、第四阻障層338沉積於第三阻障層336上、與第二溝槽金屬318沉積於第四阻障層338上並填滿第二溝槽334。通孔332與第二溝槽334整合。通孔332與第二溝槽334共用第三阻障層336與第四阻障層338。通孔332與第二溝槽334均填有第二溝槽金屬340。
第15圖為第1圖之第一裝置100之接觸電阻402，與第2至14圖之第二裝置300之接觸電阻404的比較圖400。當第一溝槽金屬M1與第二溝槽金屬M2沉積於PVD的Ta/TaN層上時，其接觸電阻402隨著第一溝槽金屬M1與第二溝槽金屬M2之關鍵尺寸變化。當第一溝槽金屬M1與第二溝槽金屬M2沉積於ALD的TaN層/PVD的Ta層上時，其接觸電阻404隨著第一溝槽金屬M1與第二溝槽金屬M2之關鍵尺寸變化。
除了第一溝槽金屬M1/第二溝槽金屬M2之關鍵尺寸為0.05μm/0.05μm以外(接觸電阻404與402幾乎相同)，不同第一溝槽金屬M1/第二溝槽金屬M2之關鍵尺寸對應的接觸電阻404均低於接觸電阻402。如圖所示，接觸電阻402由6Ω增加至14Ω，而接觸電阻404由6Ω增加至11Ω。值得注意的是，在不同的第一溝槽金屬M1/第二溝槽金屬M2之關鍵尺寸處，接觸電阻404的偏差值亦小於接觸電阻402的偏差值。更值得注意的是，接觸電阻404之斜率變化亦較接觸電阻402之斜率變化平緩。如此一來，採用第二裝置300之IC裝置，將比採用第一裝置100之 IC裝置具有更好的效能。
如第16與17圖所示，與PVD的TaN層相較，ALD的TaN層(與CVD的TaN層)具有差異。第16圖之圖500對應第1圖的第一裝置100，而圖510對應第2至14圖之第二裝置300。圖510顯示ALD的TaN層其N/Ta原子比為約2.3至2.6，PVD的TaN層其N/Ta原子比為約0.3至0.6，而ALD的TaN層/PVD的Ta層(或ALD的Ta層/PVD的TaN/Ta層)其N/Ta原子比為約0.6至1.0之間。圖500之PVD的TaN/Ta層中的碳含量低於約0.2%，而圖510之ALD的TaN層/PVD的Ta層(或ALD的TaN層/PVD的TaN/Ta層)中的碳含量介於約0.2%至1%之間。
第17圖係第一裝置100與第二裝置300之X光繞射(XRD)分析比較圖。譜線520對應第二裝置300，而譜線530對應第一裝置100。譜線520與530類似，除了圖式中特別標示的部份。此圖顯示PVD的TaN/Ta層(第一裝置100)中的β-Ta，以及ALD的TaN層/PVD的Ta層(或ALD的TaN層/PVD的TaN/Ta層)的α-Ta。
第18圖係依本發明多種方法形成之第三裝置600，其許多層裝物與組成與第14圖之第二裝置300類似。相同標號將用以標示類似的層狀物與組成以簡化說明。然而第三裝置600包含一對金屬阻障層如TaN層上的Ta層，此與第二裝置300不同。在一實施例中，阻障層636係PVD的TaN層，其厚度介於約10Å至20Å之間。阻障層638係PVD的Ta層，其厚度介於約50Å至約100Å之間。阻障層638位於阻障層636上。在另一實施例中，阻障層614係PVD的TaN層，其厚度介於約10Å至約20Å 之間。阻障層616係PVD的Ta層，其厚度介於約50Å至100Å之間。阻障層616位於阻障層614上。在多種實施例中，成對的阻障層636/638之組成可與成對的阻障層614/616具有相同組成或不同組成。舉例來說，當一實施例中的阻障層636與638分別與第14圖中的第三阻障層336與第四阻障層338實質上相同時，阻障層614/616為PVD的TaN層與PVD的Ta層。在另一實施例中，當阻障層614與616分別與第14圖中的第一阻障層314與第二阻障層316實質上相同時，阻障層636/638為PVD的TaN層/PVD的Ta層。在又一實施例中，阻障層614/616為PVD的TaN層/PVD的Ta層，而阻障層636/638亦為PVD的TaN層/PVD的Ta層。在多種實施例中，第三裝置600之成對的PVD的TaN層/PVD的Ta層(如阻障層614/616或636/638)，其N/Ta濃度比與第二裝置300之圖510(見第16圖)的N/Ta濃度比類似。舉例來說，第三裝置600之PVD的TaN層其N/Ta原子比為約2.3至2.6，而PVD的TaN層/PVD的Ta層其N/Ta原子比為約0.6至1.0。然而第三裝置600中成對之PVD的TaN層/PVD的Ta層其碳濃度，低於第二裝置300之阻障層的碳濃度。在一實施例中，第三裝置中成對之PVD的TaN/Ta層其碳濃度低於約0.2%。
在多種實施例中，第三裝置600亦不同於第1圖之第一裝置100。舉例來說，第三裝置600其PVD的TaN層(如阻障層614及/或阻障層636)之厚度，小於第一裝置100之PVD的TaN層(如第1圖中的第一溝槽金屬阻障層、通孔金屬阻障層120、及/或第二溝槽金屬阻障層126)之厚度。在多種實施例中，第三裝置600之PVD的TaN層其厚度小於30Å，而第一裝置100之PVD 的TaN層其厚度大於30Å。第三裝置600與第一裝置100的另一差異為，PVD的TaN層/PVD的Ta層之阻障層其N/Ta原子比。在多種實施例中，第三裝置600之PVD的TaN層其N/Ta原子比介於約2.3至2.6之間，見第16圖之圖510。第一裝置100之PVD的TaN層其N/Ta原子比介於約0.3至0.6之間，見第16圖之圖500。
如第18圖所示之一實施例中，第三裝置600其第一溝槽312與第二溝槽334各自的關鍵尺寸(CD，比如寬度)介於約0.036μm至約1.0μm之間，而通孔332的關鍵尺寸(如半徑)介於約0.025μm至約0.040μm之間。在另一實施例的第三裝置600中，第一溝槽312與第二溝槽334各自的關鍵尺寸(如寬度)介於約0.045至約1.0μm之間，而通孔332的關鍵尺寸(如半徑)介於約0.040μm至約0.055μm之間。在又一實施例的第三裝置600中，第一溝槽312與第二溝槽334各自的關鍵尺寸(如寬度)介於約0.064至約1.0μm之間，而通孔332的關鍵尺寸(如半徑)介於約0.055μm至約0.070μm之間。
在某些實施例中，第三裝置600之形成方法可為第2圖之方法200。在一實施例中，方法200之步驟210形成阻障層614與616如成對之PVD的TaN層與PVD的Ta層。在此實施例中，步驟210以第一PVD製程沉積阻障層614(包含在控制的氮氣流下以電漿濺鍍Ta靶材)，於第6圖所示之第一溝槽312其底部與側壁上。在第一PVD製程中，氮氣流控制於約20sccm(每分鐘標準立方公分)至40sccm之間。在一實施例中，氮氣流為約30sccm。在另一實施例中，氮氣流為約36sccm。在又一實施例中，氮氣流介於約30sccm至約40sccm之間。在多種實施例 中，第一PVD製程更包含氬氣流(介於約4sccm至約50sccm之間)、DC功率(介於約3KW至約15KW)之間、與AC功率(介於約75W至約250W之間)。在多種實施例中，PVD的TaN層如阻障層614其厚度為約10Å至20Å之間。由於高氮氣流與其他操作條件(比如氬氣流、DC功率、與AC功率)組合，PVD的TaN層如阻障層614其高N/Ta比例介於2.3至約2.6之間。步驟210更包含以第二PVD製程沉積阻障層616於阻障層614上。第二PVD製程包含在沒有氮氣流的情況下電漿濺鍍Ta靶材。在多種實施例中，PVD的Ta層如阻障層616其厚度介於約50Å至100Å之間。在一實施例中，方法200之步驟224以類似前述之PVD製程，形成阻障層636與638如成對之PVD的TaN層與PVD的Ta層。由於PVD的TaN層如阻障層636或614具有高N/Ta原子比，PVD的Ta層如阻障層638或616其Ta純度，比第一裝置100(第1圖)之PVD的Ta層其Ta純度高。綜上所述，第三裝置600之接觸電阻低於第一裝置100之接觸電阻。此外，第三裝置600之特性與第二裝置300之特性類似(甚至更優異)，詳見下述內容。
第19圖為第三裝置600的多個實施例之XRD分析。如第19圖所示，譜線712為成對之PVD的TaN層與PVD的Ta層之Ta組成，其中PVD的TaN層係於約27sccm下之氮氣流下形成。同樣地，譜線714與716為成對之PVD的TaN層與PVD的Ta層之Ta組成，差異在於PVD的TaN層於不同流量之氮氣流下形成。譜線714採用之氮氣流為約30sccm，而譜線716採用之氮氣流為約36sccm。如第19圖所示，譜線712包含β-Ta與α-Ta，而譜線714與716包含增加的α-Ta成份與減少的β-Ta成份。譜線 716包含α-Ta，但實質上不含β-Ta。由於β-Ta之電阻通常大於α-Ta，第19圖至少解釋了為何以較高流量之氮氣流形成PVD的TaN層，有益於降低第三裝置600之接觸電阻。
當設計積體電路內連線如第一裝置100、第二裝置300、與第三裝置600時，內連線電阻為重要考量之一。舉例來說，穿過內連線的傳送延遲t通常以下式表示：t=RC
其中R為內連線電阻，而C為內連線的電容負載。如此一來，低電阻有益於降低傳送延遲，即增加開關速度。內連線的電阻包含片電阻(Rs)與接觸電阻(Rc)等因素。為比較第二裝置300與第三裝置600，分別比較兩者的片電阻與接觸電阻。為達成上述目的，將以模擬與實驗比較第二裝置300的實施例與第三裝置600的兩個實施例，且上述三個實施例均採用五層的含銅金屬線路，其寬度為0.045μm。第二裝置300之實施例採用PVD的Ta層(比如第四阻障層338)於ALD的TaN層(比如第三阻障層336)上，兩者作為通孔332中的金屬阻障層。第三裝置600之第一實施例採用PVD的Ta層(比如阻障層638)於PVD的TaN層(比如阻障層636)上，兩者作為通孔332中的金屬阻障層，其中PVD的TaN層係於約30sccm之氮氣流速下形成。第三裝置600之第二實施例採用PVD的Ta層(比如阻障層638)於PVD的TaN層(比如阻障層636)上，兩者作為通孔332中的金屬阻障層，其中PVD的TaN層係於約36sccm之氮氣流速下形成。第20圖比較三個實施例中對應金屬線路的片電阻。第21圖比較三個實施例之接觸電阻。
如第20圖所示，圖722為第二裝置300之片電阻的統計值，圖724為第三裝置600的第一實施例之片電阻的統計值，而與圖724實質上重疊之圖726為第三裝置600的第二實施例之片電阻的統計值。如第20圖所示，這三個實施例之片電阻幾乎相同。
如第21與22圖所示，圖732與742為第二裝置300之接觸電阻的統計值，圖734與744為第三裝置600之第一實施例其接觸電阻的統計值，而圖736與746為第三裝置600之第二實施例其接觸電阻的統計值。每一圖各自採用約484個樣品進行統計。如第21圖所示，圖732之接觸電阻的平均值與中位數均小於圖734與736。然而圖734與736之接觸電阻的標準差均小於圖732之標準差，較低的標準差有利於預測第三裝置600中的內連線電阻。如第三裝置的兩個實施例如圖734與736所示，接觸電阻的標準差小於約0.4Ω。第22圖與第21圖之資訊類似，但具有不同觀點。此外，與第一裝置100之某些實施例(見第15圖之接觸電阻402)相較，第三裝置600的兩個實施例具有更低的接觸電阻(如同第15圖之接觸電阻404)，其中溝槽的關鍵尺寸介於約0.05μm至約0.5μm之間，且溝槽312至溝槽334之接觸電阻介於約6Ω至11Ω之間。
上述量測與數據僅用以舉例，且只對應本發明中某些而非全部的實施例。綜上所述，除非申請專利範圍明確限定，否則本發明不應侷限於上述量測與數據。
如此一來，本發明提供用於積體電路的結構，包括基板、蓋層沉積於基板上、介電層沉積於蓋層上、以及溝槽 嵌入介電層。溝槽包含ALD的TaN層或CVD的TaN層沉積於其側壁上，且ALD的TaN層或CVD的TaN層其N/Ta原子比介於約2.3至2.6之間。PVD的Ta層(或PVD的Ta層與PVD的TaN層之組合)係沉積於ALD的TaN層或CVD的TaN層上，PVD的TaN層其N/Ta原子比介於約0.3至0.6之間，且PVD的Ta層其N/Ta原子比近似於0。銅沉積於PVD的Ta層(或PVD的Ta層與PVD的TaN層之組合)上。PVD的Ta層(或PVD的Ta層與PVD的TaN層之組合)，與ALD的TaN層(或CVD的TaN層)之N/Ta原子比介於約0.6至1.0之間。上述結構更包括通孔整合至溝槽底部，且通孔延伸至蓋層。ALD的TaN層其厚度介於約5Å至10Å之間。PVD的Ta層或PVD的TaN層其Ta由β-Ta轉變至α-Ta。介電層包含低介電常數材料，其介電常數介於約2.6至2.65之間。介電層更包含Si、C、O、與H。ALD的TaN層與沉積其上之PVD的Ta層(或PVD的Ta層與PVD的TaN層)其碳濃度介於約0.2%至1%之間。PVD的Ta層或PVD的TaN層之碳濃度小於約0.2%。
某些實施例為用於積體電路的結構，包括基板、第一蓋層沉積於基板上、第一介電層沉積於第一蓋層上、第一溝槽嵌入第一介電層中、第二蓋層沉積於第一介電層上、第二介電層沉積於第一介電層上、第二溝槽嵌入第二介電層中、通孔位於第一溝槽與第二溝槽中，並整合至第一溝槽的頂部中與第二溝槽的底部中。第一溝槽或第二溝槽包含ALD的TaN層或CVD的TaN層沉積於第一溝槽的底部與側壁上，其中ALD的TaN層或CVD的TaN層其N/Ta原子比介於約2.3至2.6之間，而PVD的Ta層(或PVD的Ta層與PVD的TaN層之組合)係沉積於 ALD的TaN層或CVD的TaN層上。其中PVD的TaN層其N/Ta原子比介於約0.3至0.6之間，而PVD的Ta層其N/Ta原子比近似於0，且銅沉積於PVD的Ta層(或PVD的Ta層與PVD的TaN層之組合)上。PVD的Ta層(或PVD的Ta層與PVD的TaN層之組合)，與ALD的TaN層(或CVD的TaN層)之N/Ta原子比介於約0.6至1.0之間。
本發明亦提供製作積體電路的方法，包含沉積蓋層於基板上，沉積介電層於蓋層上，沉積硬遮罩層於介電層上，形成溝槽於第一介電層中，以及填滿溝槽。填滿溝槽之步驟包括沉積第一阻障層於溝槽的底部與側壁上，沉積第二阻障層於第一阻障層上，以及沉積金屬於第二阻障層上。上述方法更包括以化學機械研磨(CMP)移除硬遮罩層。沉積第一阻障層之步驟包括以原子層沉積(ALD)或化學氣相沉積(CVD)沉積厚度介於約5Å至10Å之氮化鉭(TaN)層。沉積第二阻障層之步驟包括以物理氣相沉積(PVD)沉積厚度介於約50至100之Ta層於第一阻障層上。沉積第二阻障層之步驟更包括以PVD製程沉積TaN層。沉積金屬之步驟包括沉積銅。沉積金屬的步驟更包括沉積銅晶種層。
在本發明一實施例中，用於積體電路的結構包括：基板；蓋層沉積於基板上；介電層沉積於蓋層上，以及溝槽嵌入介電層中。溝槽包括TaN層形成於溝槽的側壁上，其中TaN層之氮濃度高於鉭濃度。溝槽亦包括Ta層形成於TaN層上，以及含銅層形成於Ta層上。TaN層與Ta層的總碳濃度小於約0.2%。
在本發明另一實施例中，用於積體電路的結構包 括：基板；第一蓋層形成於基板上；第一介電層，形成於第一蓋層上；以及第一溝槽，嵌入第一介電層中。第一溝槽包括第一TaN層沉積於第一溝槽的底部與側壁上，其中第一TaN層之氮濃度高於鉭濃度；第一Ta層沉積於第一TaN層上；以及第一含銅層形成於第一Ta層上。上述結構更包括第二蓋層形成於第一介電層上；第二介電層形成於第一介電層上；以及第二溝槽嵌入第二介電層中。第二溝槽包括第二TaN層，沉積於第二溝槽的底部與側壁上，其中第二TaN層之氮濃度高於鉭濃度；第二Ta層沉積於第二TaN層上；以及第二含銅層形成於第二鉭層上。上述結構更包括通孔位於第一溝槽與第二溝槽之間，其中通孔整合至第一溝槽的頂部中，並整合至第二溝槽的底部中。
在本發明又一實施例中，積體電路的製作方法包括沉積蓋層於基板上；沉積介電層於蓋層上；形成溝槽於介電層中；以及填滿溝槽。填滿溝槽之步驟包括沉積第一阻障層於溝槽之底部與側壁上，且第一阻障層係以至少20sccm之氮氣流物理氣相沉積的TaN；沉積第二阻障層於第一阻障層上，且第二阻障層係物理氣相沉積的Ta；以及沉積金屬層於第二阻障層上。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
302‧‧‧基板
304‧‧‧第一蓋層
306‧‧‧第一介電層
312‧‧‧第一溝槽
318‧‧‧第一溝槽金屬
320‧‧‧第二蓋層
322‧‧‧第二介電層
332‧‧‧通孔
334‧‧‧第二溝槽
340‧‧‧第二溝槽金屬
600‧‧‧第三裝置
614、616、636、638‧‧‧阻障層

Claims (9)

  1. 一種用於積體電路的結構，包括：一基板；一蓋層，沉積於該基板上；一介電層，沉積於該蓋層上；以及一溝槽，嵌入該介電層中，其中該溝槽包括：一TaN層形成於該溝槽的側壁上，其中該TaN層之氮濃度高於鉭濃度；一Ta層形成於該TaN層上；以及一含銅層形成於該Ta層上，其中該TaN層與該Ta層的總碳濃度小於約0.2%，其中該結構之接觸電阻的標準差小於約0.4Ω。
  2. 如申請專利範圍第1項所述之用於積體電路的結構，其中該TaN層與該Ta層之總氮/鉭比介於約0.6至約1.0之間，其中該TaN層之氮/鉭比介於約2.3至約2.6之間。
  3. 如申請專利範圍第1項所述之用於積體電路的結構，更包括一通孔整合至該溝槽的底部中，其中該通孔延伸至該蓋層，其中該溝槽之關鍵尺寸為約0.045μm。
  4. 如申請專利範圍第1項所述之用於積體電路的結構，其中該TaN層之厚度介於約10Å至約20Å之間，其中該Ta層之厚度介於約50Å至100Å之間。
  5. 如申請專利範圍第1項所述之用於積體電路的結構，其中該TaN層與該Ta層包含α-Ta但實質上不含β-Ta。
  6. 一種用於積體電路的結構，包括： 一基板；一第一蓋層，形成於該基板上；一第一介電層，形成於該第一蓋層上；以及一第一溝槽，嵌入該第一介電層中，其中該第一溝槽包括：一第一TaN層，沉積於該第一溝槽的底部與側壁上，其中該第一TaN層之氮濃度高於鉭濃度；一第一Ta層，沉積於該第一TaN層上；一第一含銅層，形成於該第一Ta層上；一第二蓋層，形成於該第一介電層上；一第二介電層，形成於該第一介電層上；以及一第二溝槽，嵌入該第二介電層中，其中該第二溝槽包括：一第二TaN層，沉積於該第二溝槽的底部與側壁上，其中該第二TaN層之氮濃度高於鉭濃度；一第二Ta層，沉積於該第二TaN層上；一第二含銅層，形成於該第二鉭層上；以及一通孔，位於該第一溝槽與該第二溝槽之間，其中該通孔整合至該第一溝槽的頂部中，並整合至該第二溝槽的底部中，其中該第一溝槽至該第二溝槽的接觸電阻其標準差小於約0.4Ω。
  7. 一種積體電路的製作方法，包括：沉積一蓋層於一基板上；沉積一介電層於該蓋層上；形成一溝槽於該介電層中；以及填滿該溝槽，包括： 沉積一第一阻障層於該溝槽之底部與側壁上，且該第一阻障層係以至少20sccm之氮氣流物理氣相沉積的TaN；沉積一第二阻障層於該第一阻障層上，且該第二阻障層係物理氣相沉積的Ta；以及沉積一金屬層於該第二阻障層上。
  8. 如申請專利範圍第7項所述之積體電路的製作方法，其中沉積該第一阻障層之步驟包括在約20sccm至約40sccm之間的氮氣流下電漿濺鍍Ta靶材。
  9. 如申請專利範圍第7項所述之積體電路的製作方法，其中該第一阻障層之沉積厚度介於約10Å至約20Å之間，其中該第二阻障層之沉積厚度介於約50Å至約100Å之間。
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