JP2017228756A - ファン−アウト半導体パッケージ - Google Patents
ファン−アウト半導体パッケージ Download PDFInfo
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- JP2017228756A JP2017228756A JP2016247621A JP2016247621A JP2017228756A JP 2017228756 A JP2017228756 A JP 2017228756A JP 2016247621 A JP2016247621 A JP 2016247621A JP 2016247621 A JP2016247621 A JP 2016247621A JP 2017228756 A JP2017228756 A JP 2017228756A
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- layer
- connection member
- fan
- semiconductor package
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Abstract
Description
図1は電子機器システムの例を概略的に示すブロック図である。
一般に、半導体チップには、数多くの微細電気回路が集積されているが、それ自体が半導体完成品としての役割をすることはできず、外部からの物理的または化学的衝撃により損傷する可能性がある。したがって、半導体チップ自体をそのまま用いるのではなく、半導体チップをパッケージングして、パッケージ状態で電子機器などに用いている。
図3はファン−イン半導体パッケージのパッケージング前後を概略的に示した断面図である。
図7はファン−アウト半導体パッケージの概略的な形態を示した断面図である。
1010 メインボード
1020 チップ関連部品
1030 ネットワーク関連部品
1040 その他の部品
1050 カメラ
1060 アンテナ
1070 ディスプレイ
1080 電池
1090 信号ライン
1100 スマートフォン
1101 本体
1110 メインボード
1120 部品
1130 カメラ
2200 ファン−イン半導体パッケージ
2220 半導体チップ
2221 本体
2222 接続パッド
2223 パッシベーション膜
2240 接続部材
2241 絶縁層
2242 配線パターン
2243 ビア
2250 パッシベーション層
2260 アンダーバンプ金属層
2270 半田ボール
2280 アンダーフィル樹脂
2290 モールディング材
2500 メインボード
2301 インターポーザ基板
2302 インターポーザ基板
2100 ファン−アウト半導体パッケージ
2120 半導体チップ
2121 本体
2122 接続パッド
2140 接続部材
2141 絶縁層
2142 再配線層
2143 ビア
2150 パッシベーション層
2160 アンダーバンプ金属層
2170 半田ボール
100 半導体パッケージ
100A〜100H ファン−アウト半導体パッケージ
110 第1接続部材
111、111a、111b、111c 絶縁層
112a、112b、112c、112d 再配線層
113 ビア
120 半導体チップ
121 本体
122 接続パッド
123 パッシベーション膜
130 封止材
131 開口部
132 バックサイド再配線層
133 バックサイドビア
140 第2接続部材
141 絶縁層
142 再配線層
143 ビア
150 パッシベーション層
160 アンダーバンプ金属層
161a〜161i ビア
162 外部接続パッド
160a、160b 導体層
170 接続端子
181、183、191、192 補強層
182、185 開口部
184 樹脂層
Claims (24)
- 貫通孔を有する第1接続部材と、
前記第1接続部材の貫通孔に配置され、接続パッドが配置された活性面及び前記活性面の反対側に配置された非活性面を有する半導体チップと、
前記第1接続部材及び前記半導体チップの非活性面の少なくとも一部を封止する封止材と、
前記第1接続部材及び前記半導体チップの活性面上に配置された第2接続部材と、
前記第2接続部材上に配置されたパッシベーション層と、を含み、
前記第1接続部材及び前記第2接続部材は、それぞれ前記半導体チップの接続パッドと電気的に接続された再配線層を含み、
前記第2接続部材は、前記第2接続部材の再配線層が配置される絶縁層を含み、
前記パッシベーション層は、前記第2接続部材の絶縁層より弾性係数が大きい、ファン−アウト半導体パッケージ。 - 前記パッシベーション層の厚さが10μm以上である、請求項1に記載のファン−アウト半導体パッケージ。
- 前記パッシベーション層の表面粗さ(Ra)が1nm以上である、請求項1または2に記載のファン−アウト半導体パッケージ。
- 前記パッシベーション層の水分吸収率が1.5%以下である、請求項1から3のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記第2接続部材の絶縁層は感光性絶縁層であり、
前記パッシベーション層は無機フィラーを含む非感光性絶縁層である、請求項1から4のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記第1接続部材は、第1絶縁層と、前記第2接続部材と接して前記第1絶縁層に埋め込まれた第1再配線層と、前記第1絶縁層の前記第1再配線層が埋め込まれた側の反対側上に配置された第2再配線層と、を含み、
前記第1及び第2再配線層は前記接続パッドと電気的に接続されている、請求項1から5のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記第1接続部材は、前記第1絶縁層上に配置されて前記第2再配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3再配線層と、をさらに含み、
前記第3再配線層は前記接続パッドと電気的に接続されている、請求項6に記載のファン−アウト半導体パッケージ。 - 前記第2接続部材の再配線層と前記第1再配線層との間の距離が、前記第2接続部材の再配線層と前記接続パッドとの間の距離より大きい、請求項6または7に記載のファン−アウト半導体パッケージ。
- 前記第1再配線層は前記第2接続部材の再配線層より厚さが厚い、請求項6から8のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記第1再配線層の下面は前記接続パッドの下面より上側に位置する、請求項6から9のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記第2再配線層は前記半導体チップの活性面と非活性面との間に位置する、請求項7に記載のファン−アウト半導体パッケージ。
- 前記第1接続部材は、第1絶縁層と、前記第1絶縁層の両面に配置された第1再配線層及び第2再配線層と、前記第1絶縁層上に配置されて前記第1再配線層を覆う第2絶縁層と、前記第2絶縁層上に配置された第3再配線層と、を含み、
前記第1〜第3再配線層は前記接続パッドと電気的に接続されている、請求項1から11のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記第1接続部材は、前記第1絶縁層上に配置されて前記第2再配線層を覆う第3絶縁層と、前記第3絶縁層上に配置された第4再配線層と、をさらに含み、
前記第4再配線層は前記接続パッドと電気的に接続されている、請求項12に記載のファン−アウト半導体パッケージ。 - 前記第1絶縁層は前記第2絶縁層より厚さが厚い、請求項12または13に記載のファン−アウト半導体パッケージ。
- 前記第3再配線層は前記第2接続部材の再配線層より厚さが厚い、請求項12から14のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記第1再配線層は前記半導体チップの活性面と非活性面との間に位置する、請求項12から15のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記第3再配線層の下面は前記接続パッドの下面より下側に位置する、請求項12から16のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記封止材は無機フィラー及び絶縁樹脂を含む、請求項1から17のいずれか一項に記載のファン−アウト半導体パッケージ。
- 前記封止材上に配置された補強層をさらに含み、
前記補強層は前記封止材より弾性係数が大きい、請求項1から18のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記パッシベーション層を貫通し、前記第2接続部材の再配線層の少なくとも一部を露出させる開口部と、
前記開口部上に形成され、前記第2接続部材の露出した再配線層と接続されたアンダーバンプ金属層と、
前記アンダーバンプ金属層上に形成され、少なくとも一つがファン−アウト領域に配置された接続端子と、をさらに含む、請求項1から19のいずれか一項に記載のファン−アウト半導体パッケージ。 - 前記アンダーバンプ金属層は、前記パッシベーション層上に形成された外部接続パッドと、前記開口部に形成され、前記外部接続パッドと前記第2接続部材の再配線層とを接続する複数のビアと、を含む、請求項20に記載のファン−アウト半導体パッケージ。
- 前記外部接続パッドの表面に、前記複数のビアにそれぞれ対応して複数のディンプルが形成されている、請求項21に記載のファン−アウト半導体パッケージ。
- 貫通孔を有する第1接続部材と、
前記第1接続部材の貫通孔に配置され、接続パッドが配置された活性面及び前記活性面の反対側に配置された非活性面を有する半導体チップと、
前記第1接続部材及び前記半導体チップの非活性面の少なくとも一部を封止する封止材と、
前記第1接続部材及び前記半導体チップの活性面上に配置された第2接続部材と、
前記第2接続部材上に配置されたパッシベーション層と、を含み、
前記第1接続部材及び前記第2接続部材は、それぞれ前記半導体チップの接続パッドと電気的に接続された再配線層を含み、
前記第2接続部材は、前記第2接続部材の再配線層が配置される絶縁層を含み、
前記パッシベーション層及び前記第2接続部材の絶縁層は、それぞれ無機フィラー及び絶縁樹脂を含み、
前記パッシベーション層に含まれた無機フィラーの重量パーセントが、前記第2接続部材の絶縁層に含まれた無機フィラーの重量パーセントより大きい、ファン−アウト半導体パッケージ。 - 貫通孔を有する第1接続部材と、
前記第1接続部材の貫通孔に配置され、接続パッドが配置された活性面及び前記活性面の反対側に配置された非活性面を有する半導体チップと、
前記第1接続部材及び前記半導体チップの非活性面の少なくとも一部を封止する封止材と、
前記第1接続部材及び前記半導体チップの活性面上に配置され、前記半導体の接続パッドと電気的に接続された再配線層を含む第2接続部材と、
前記第2接続部材上に配置され、前記第2接続部材の再配線層の少なくとも一部を露出させる複数の開口部を有するパッシベーション層と、
前記パッシベーション層の複数の開口部上に形成され、前記第2接続部材の露出している再配線層と接続されたアンダーバンプ金属層と、
前記アンダーバンプ金属層上に配置され、前記アンダーバンプ金属層を介して前記第2接続部材の露出している再配線層と電気的に接続された接続端子と、を含み、
前記第1接続部材の再配線層は、前記第2接続部材の再配線層を介して前記半導体チップの接続パッドと電気的に接続される、ファン−アウト半導体パッケージ。
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US20160043047A1 (en) * | 2014-08-07 | 2016-02-11 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Double-Sided Fan-Out Wafer Level Package |
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US10872863B2 (en) | 2018-08-29 | 2020-12-22 | Samsung Electronics Co.. Ltd. | Semiconductor package |
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US10600748B2 (en) | 2020-03-24 |
US20200335460A1 (en) | 2020-10-22 |
US20180190602A1 (en) | 2018-07-05 |
US11011482B2 (en) | 2021-05-18 |
US20170365566A1 (en) | 2017-12-21 |
US10714437B2 (en) | 2020-07-14 |
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