JP2017168586A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2017168586A JP2017168586A JP2016051543A JP2016051543A JP2017168586A JP 2017168586 A JP2017168586 A JP 2017168586A JP 2016051543 A JP2016051543 A JP 2016051543A JP 2016051543 A JP2016051543 A JP 2016051543A JP 2017168586 A JP2017168586 A JP 2017168586A
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- semiconductor chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
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- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Abstract
Description
以下、図を用いて開口部22cの配置や大きさの違いによる、いくつかの変形例を示す。以下、図中において、図1乃至図3と同じ符号は同じものを示す符号であるので、詳しい説明は省略する。
Claims (7)
- 基板と、
前記基板上に設置された、第1半導体チップと、
前記基板上の配線と、前記第1半導体チップ上の接続電極とを接続する、ワイヤと、
前記第1半導体チップの上方に設置された矩形状の第1接着層と、前記第1接着層の四隅の下部に位置する柱状の第2接着層とを有する接着部であって、前記ワイヤの前記接続電極からの最大高さは前記接続電極と前記第1接着層との間隔よりも小さく、前記第2接着層は、矩形状の前記第1接着層における2対の対辺のうち少なくとも1対の対辺のそれぞれの下部に開口部を有する、接着部と、
前記接着部上に設置された、第2半導体チップと、
を備える半導体装置。 - 前記接着部と前記第1半導体チップとの間を含む領域を封止するモールド材をさらに有する、請求項1に記載の半導体装置。
- 前記接着部は、絶縁材料の接着剤である、請求項1又は2に記載の半導体装置。
- 前記接着部は、前記接着部における前記第2接着層の一部において、前記ワイヤと接触している、請求項1乃至3のいずれかに記載の半導体装置。
- 前記接着部は、前記接着部における矩形状の前記第1接着層の2対の対辺のそれぞれの下部に前記開口を有する、請求項1乃至4のいずれかに記載の半導体装置。
- 前記第1接着層における2対の対辺のうち一方の対辺のそれぞれの下部にある前記開口部の幅は、前記第1接着層における2対の対辺のうち他方の対辺のそれぞれの下部にある前記開口部の幅よりも大きい、請求項5に記載の半導体装置。
- 前記接着部は、前記第1接着層における2対の対辺のうち一方の対辺のそれぞれの下部に前記開口部を有し、前記第1接着層における2対の対辺のうち他方の対辺のそれぞれの下部には前記開口部を有しない、請求項1乃至4に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016051543A JP6586036B2 (ja) | 2016-03-15 | 2016-03-15 | 半導体装置の製造方法 |
TW106104226A TWI621232B (zh) | 2016-03-15 | 2017-02-09 | Semiconductor device |
CN201710133212.0A CN107195589B (zh) | 2016-03-15 | 2017-03-08 | 半导体装置 |
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JP2016051543A JP6586036B2 (ja) | 2016-03-15 | 2016-03-15 | 半導体装置の製造方法 |
Publications (2)
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JP2017168586A true JP2017168586A (ja) | 2017-09-21 |
JP6586036B2 JP6586036B2 (ja) | 2019-10-02 |
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JP2016051543A Active JP6586036B2 (ja) | 2016-03-15 | 2016-03-15 | 半導体装置の製造方法 |
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JP (1) | JP6586036B2 (ja) |
CN (1) | CN107195589B (ja) |
TW (1) | TWI621232B (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020096153A (ja) * | 2018-12-13 | 2020-06-18 | 力成科技股▲分▼有限公司 | 半導体パッケージ構造体及びその製造方法 |
WO2020218532A1 (ja) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | ドルメン構造を有する半導体装置の製造方法及び支持片の製造方法 |
WO2020218530A1 (ja) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | ドルメン構造を有する半導体装置の製造方法及び支持片の製造方法 |
US10892251B2 (en) | 2019-03-19 | 2021-01-12 | Toshiba Memory Corporation | Semiconductor device |
US11935872B2 (en) | 2021-01-25 | 2024-03-19 | Kioxia Corporation | Semiconductor device and method of manufacturing semiconductor device |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7042713B2 (ja) * | 2018-07-12 | 2022-03-28 | キオクシア株式会社 | 半導体装置 |
JP2020021908A (ja) | 2018-08-03 | 2020-02-06 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2020038902A (ja) * | 2018-09-04 | 2020-03-12 | キオクシア株式会社 | 半導体装置 |
JP2021015922A (ja) * | 2019-07-16 | 2021-02-12 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2021044362A (ja) * | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2002222889A (ja) * | 2001-01-24 | 2002-08-09 | Nec Kyushu Ltd | 半導体装置及びその製造方法 |
JP2015176906A (ja) * | 2014-03-13 | 2015-10-05 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
Family Cites Families (5)
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JP2002033022A (ja) * | 2000-07-13 | 2002-01-31 | Mitsui Takeda Chemicals Inc | 導電性多層構造樹脂粒子およびそれを用いた異方導電性接着剤 |
TWI326910B (en) * | 2003-03-31 | 2010-07-01 | Sanyo Electric Co | Semiconductor module and method for making same |
JP4160083B2 (ja) * | 2006-04-11 | 2008-10-01 | シャープ株式会社 | 光学装置用モジュール及び光学装置用モジュールの製造方法 |
TWI435419B (zh) * | 2010-02-15 | 2014-04-21 | Toshiba Kk | 半導體記憶裝置及其製造方法 |
JP5857355B2 (ja) * | 2010-09-16 | 2016-02-10 | Shマテリアル株式会社 | 半導体発光素子搭載用基板、及びそれを用いた半導体発光装置 |
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2016
- 2016-03-15 JP JP2016051543A patent/JP6586036B2/ja active Active
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2017
- 2017-02-09 TW TW106104226A patent/TWI621232B/zh active
- 2017-03-08 CN CN201710133212.0A patent/CN107195589B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002222889A (ja) * | 2001-01-24 | 2002-08-09 | Nec Kyushu Ltd | 半導体装置及びその製造方法 |
JP2015176906A (ja) * | 2014-03-13 | 2015-10-05 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020096153A (ja) * | 2018-12-13 | 2020-06-18 | 力成科技股▲分▼有限公司 | 半導体パッケージ構造体及びその製造方法 |
US10892251B2 (en) | 2019-03-19 | 2021-01-12 | Toshiba Memory Corporation | Semiconductor device |
WO2020218532A1 (ja) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | ドルメン構造を有する半導体装置の製造方法及び支持片の製造方法 |
WO2020218530A1 (ja) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | ドルメン構造を有する半導体装置の製造方法及び支持片の製造方法 |
US11935872B2 (en) | 2021-01-25 | 2024-03-19 | Kioxia Corporation | Semiconductor device and method of manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
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TW201803063A (zh) | 2018-01-16 |
CN107195589A (zh) | 2017-09-22 |
TWI621232B (zh) | 2018-04-11 |
CN107195589B (zh) | 2021-03-16 |
JP6586036B2 (ja) | 2019-10-02 |
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