CN107195589B - 半导体装置 - Google Patents
半导体装置 Download PDFInfo
- Publication number
- CN107195589B CN107195589B CN201710133212.0A CN201710133212A CN107195589B CN 107195589 B CN107195589 B CN 107195589B CN 201710133212 A CN201710133212 A CN 201710133212A CN 107195589 B CN107195589 B CN 107195589B
- Authority
- CN
- China
- Prior art keywords
- adhesive
- semiconductor chip
- bonding
- substrate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/02—Containers; Seals
- H01L23/10—Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3192—Multilayer coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/48147—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked with an intermediate bond, e.g. continuous wire daisy chain
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Description
Claims (4)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016051543A JP6586036B2 (ja) | 2016-03-15 | 2016-03-15 | 半導体装置の製造方法 |
JP2016-051543 | 2016-03-15 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN107195589A CN107195589A (zh) | 2017-09-22 |
CN107195589B true CN107195589B (zh) | 2021-03-16 |
Family
ID=59870854
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201710133212.0A Active CN107195589B (zh) | 2016-03-15 | 2017-03-08 | 半导体装置 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP6586036B2 (zh) |
CN (1) | CN107195589B (zh) |
TW (1) | TWI621232B (zh) |
Families Citing this family (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP7042713B2 (ja) * | 2018-07-12 | 2022-03-28 | キオクシア株式会社 | 半導体装置 |
JP2020021908A (ja) * | 2018-08-03 | 2020-02-06 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2020038902A (ja) * | 2018-09-04 | 2020-03-12 | キオクシア株式会社 | 半導体装置 |
TWI665770B (zh) * | 2018-12-13 | 2019-07-11 | 力成科技股份有限公司 | 半導體封裝結構及其製法 |
JP2020155559A (ja) | 2019-03-19 | 2020-09-24 | キオクシア株式会社 | 半導体装置 |
WO2020218530A1 (ja) * | 2019-04-25 | 2020-10-29 | 日立化成株式会社 | ドルメン構造を有する半導体装置の製造方法及び支持片の製造方法 |
JP2022097769A (ja) * | 2019-04-25 | 2022-07-01 | 昭和電工マテリアルズ株式会社 | ドルメン構造を有する半導体装置の製造方法及び支持片の製造方法 |
JP2021015922A (ja) * | 2019-07-16 | 2021-02-12 | キオクシア株式会社 | 半導体装置およびその製造方法 |
JP2021044362A (ja) * | 2019-09-10 | 2021-03-18 | キオクシア株式会社 | 半導体装置 |
JP2022113250A (ja) | 2021-01-25 | 2022-08-04 | キオクシア株式会社 | 半導体装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020096785A1 (en) * | 2001-01-24 | 2002-07-25 | Nec Corporation | Semiconductor device having stacked multi chip module structure |
CN104916645A (zh) * | 2014-03-13 | 2015-09-16 | 株式会社东芝 | 半导体装置及半导体装置的制造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002033022A (ja) * | 2000-07-13 | 2002-01-31 | Mitsui Takeda Chemicals Inc | 導電性多層構造樹脂粒子およびそれを用いた異方導電性接着剤 |
TWI305018B (en) * | 2003-03-31 | 2009-01-01 | Sanyo Electric Co | Semiconductor module and method for making same |
JP4160083B2 (ja) * | 2006-04-11 | 2008-10-01 | シャープ株式会社 | 光学装置用モジュール及び光学装置用モジュールの製造方法 |
TWI435419B (zh) * | 2010-02-15 | 2014-04-21 | Toshiba Kk | 半導體記憶裝置及其製造方法 |
JP5857355B2 (ja) * | 2010-09-16 | 2016-02-10 | Shマテリアル株式会社 | 半導体発光素子搭載用基板、及びそれを用いた半導体発光装置 |
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2016
- 2016-03-15 JP JP2016051543A patent/JP6586036B2/ja active Active
-
2017
- 2017-02-09 TW TW106104226A patent/TWI621232B/zh active
- 2017-03-08 CN CN201710133212.0A patent/CN107195589B/zh active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020096785A1 (en) * | 2001-01-24 | 2002-07-25 | Nec Corporation | Semiconductor device having stacked multi chip module structure |
CN104916645A (zh) * | 2014-03-13 | 2015-09-16 | 株式会社东芝 | 半导体装置及半导体装置的制造方法 |
Also Published As
Publication number | Publication date |
---|---|
TWI621232B (zh) | 2018-04-11 |
JP6586036B2 (ja) | 2019-10-02 |
CN107195589A (zh) | 2017-09-22 |
JP2017168586A (ja) | 2017-09-21 |
TW201803063A (zh) | 2018-01-16 |
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PB01 | Publication | ||
PB01 | Publication | ||
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SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant | ||
CP01 | Change in the name or title of a patent holder |
Address after: Tokyo Patentee after: TOSHIBA MEMORY Corp. Address before: Tokyo Patentee before: Pangea Co.,Ltd. Address after: Tokyo Patentee after: Kaixia Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
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CP01 | Change in the name or title of a patent holder | ||
TR01 | Transfer of patent right |
Effective date of registration: 20220128 Address after: Tokyo Patentee after: Pangea Co.,Ltd. Address before: Tokyo Patentee before: TOSHIBA MEMORY Corp. |
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TR01 | Transfer of patent right |