JP2017135397A - Electronic component mounting method and electronic component mounting system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a mounting technique capable of achieving to mount multiple electronic components on a substrate, in plane arrangement, more easily.SOLUTION: Multiple chips CP1 are laminated on a substrate WA in plane arrangement. Next, on a resin layer RS2 formed a temporary substrate WT2, multiple chips CP2 of a second layer to be mounted of the chip CP1 are arranged in plane in face-up state and fixed temporarily. The temporary substrate WT2 is then flipped up and down, and the multiple chips CP2 of the second layer are held on the temporary substrate WT2, in face-down state, and while aligning the substrate WA and temporary substrate WT2, each chip CP2 of the second layer and each chip CP1 of the first layer on the substrate WA are approached relatively, before bonding each chip CP1 and each chip CP2. Furthermore, while maintaining the state where each chip CP2 is bonded to each chip CP1, the temporary substrate WT2 is separated from multiple chip CP2 of the second layer. A laminate is obtained by repeating above-mentioned steps.SELECTED DRAWING: Figure 22

Description

  The present invention relates to a technique for mounting an electronic component such as a semiconductor chip (hereinafter also simply referred to as a chip) on a substrate.

  There is a mounting technique for bonding an electronic component such as a semiconductor chip on a substrate.

  For example, Patent Document 1 describes the following technique. Specifically, first, after applying a non-conductive adhesive (resin layer) on the substrate, a semiconductor chip (hereinafter also simply referred to as a chip) is placed on the substrate and temporarily fixed. Then, the substrate and the chip are heated and pressed to melt the solder bumps (solder bumps provided on the substrate side) provided on the lower surface of the chip. As a result, the chip is bonded onto the substrate.

JP 2004-088041 A

  However, when such a technique is used to join a plurality of chips on a substrate by repeating the operation of placing one chip on the substrate and performing the joining operation of the chip, there are many cases. There is a problem that it takes a long time. For example, if it takes 10 seconds to bond one chip, it takes 50,000 seconds (50,000 seconds) to bond 5000 (5,000) chips.

  Accordingly, an object of the present invention is to provide a mounting technique that can more efficiently realize mounting a plurality of electronic components in a planar arrangement on a substrate.

  In order to solve the above-mentioned problem, a first aspect of the present invention is an electronic component mounting method, and a) an i-th resin on an i-th substrate (where i is an integer of 1 or more) which is a temporary substrate. A step of forming a layer; b) a step of placing a plurality of electronic components of the i-th layer on the i-th resin layer in a face-up state with their joint surfaces facing upward; The predetermined substrate and the i-th substrate are relatively brought close to each other in a state where the substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other. A step of relatively bringing a plurality of electronic components of the i-th layer into close proximity to each other and joining the predetermined substrate and the plurality of electronic components of the i-th layer; and d) a plurality of the i-th layer While maintaining the electronic component bonded to the predetermined substrate, the i-th layer And separating the substrate of the i-th several electronic components is an electronic component mounting method comprising.

  According to a second aspect of the present invention, there is provided an electronic component mounting system in which an i-th resin layer formed on an i-th substrate (where i is an integer of 1 or more) is a temporary substrate. A plurality of electronic components of i layer are placed in a face-up state with their joint surfaces facing upward, and a plurality of electronic components of i layer are arranged in a plane on the i th resin layer and temporarily fixed. The predetermined substrate and the i-th substrate are relatively brought close to each other with the bonding means, the predetermined substrate, and the plurality of electronic components of the i-th layer disposed on the i-th substrate facing each other. A second bonding means for relatively bringing the predetermined substrate and the plurality of electronic components of the i-th layer close together, and bonding the predetermined substrate and the plurality of electronic components of the i-th layer; A state in which the plurality of electronic components of the i-th layer are bonded to the predetermined substrate is maintained. While it is an electronic component mounting system comprising: a separating means for separating the substrate of the first i from a plurality of electronic components of the i-th layer.

  The present invention is also directed to a substrate used in an electronic component mounting method.

  According to the present invention, it is possible to more efficiently realize mounting a plurality of electronic components in a planar arrangement on a substrate.

It is a flowchart which shows the electronic component mounting operation | movement which concerns on embodiment. It is a flowchart which shows the lamination | stacking operation | movement of the chip | tip of a 1st layer. It is a flowchart which shows the lamination | stacking operation | movement of the chip | tip of each layer after the 2nd layer. It is a figure which shows the structure of a chip mounting system. It is a figure which shows a chip supply apparatus and a COW bonding apparatus. It is a figure which shows the temporary board | substrate before resin layer formation. It is a figure which shows the temporary board | substrate with which the resin layer was formed. It is a figure which shows a mode that the 1st chip | tip is mounted on a temporary board | substrate. It is a figure which shows the state in which the 1st chip | tip was mounted on the temporary board | substrate. It is a figure which shows a mode that the 2nd chip | tip is mounted on a temporary board | substrate. It is a figure which shows the state by which the 2nd chip | tip was mounted on the temporary board | substrate. It is a figure which shows the state in which the some chip | tip was mounted on the temporary board | substrate. It is a figure which shows a mode that the dispersion | variation has arisen in the chip | tip upper end position resulting from the thickness dispersion | variation of a chip | tip. It is a figure which shows a mode that a chip | tip upper end position is aligned using a planar member. It is a figure which shows a mode that an upper end position is aligned and each chip | tip is mounted. It is a figure which shows a mode that the upper and lower sides of a temporary board | substrate are reversed. In a WOW bonding apparatus, it is a figure which shows a mode that the board | substrate of joining object and the temporary board | substrate after flipping up and down are opposingly arranged. It is a figure which shows joining operation | movement of the several chip | tip in a WOW bonding apparatus. It is a figure which shows debonding operation | movement. It is a figure which shows the state in which the resin layer was formed in the 2nd temporary board | substrate. It is a figure which shows the state in which the several chip | tip was mounted in the 2nd temporary board | substrate. It is a figure which shows a mode that the upper and lower sides of a 2nd temporary board | substrate are reversed. It is a figure which shows a mode that the board | substrate with which the chip | tip of the 1st layer was joined, and the 2nd temporary board | substrate after turning upside down are opposingly arranged. It is a figure which shows joining operation | movement of the chip | tip of a 1st layer, and the chip | tip of a 2nd layer. It is a figure which shows the debonding operation | movement which concerns on a 2nd temporary board | substrate. It is a figure which shows the state by which the chip | tip of multiple layers was laminated | stacked on the board | substrate of joining object. It is a figure which shows the mark for chip position adjustment. It is a figure which shows the mark for chip position adjustment. It is a figure which shows the relative position shift of the chip position adjustment mark. It is a figure which shows the state after an underfill process. It is a figure which shows the chip | tip position adjustment operation | movement by visible light. It is a figure which shows the board | substrate position adjustment operation | movement by visible light. It is a figure which specifies a penetration electrode. It is a figure which shows joining operation | movement. It is a figure which shows the temperature profile at the time of solder joining. It is a figure which shows the chip | tip etc. in which the copper post was provided above the penetration electrode. It is a figure which shows the chip | tip etc. in which the copper post was provided under the penetration electrode. It is a figure which shows the chip | tip etc. in which the copper post was provided in the upper and lower sides of a penetration electrode. It is a figure which shows the chip | tip etc. which do not have a copper post. It is a figure which shows a mode that the chip | tip of a 1st and 2nd layer is opposingly arranged. It is a figure which shows the lamination example of the chip | tip which has a copper post. It is a figure which shows the lamination example of the chip | tip which does not have a copper post. It is a figure which shows argon bombardment. It is a figure which shows the chip | tip surface to which OH group adhered by the hydrophilic treatment. It is a figure which shows a temporary joining state. It is a figure which shows the joining state after a heating. It is a figure which shows the defect position on a board | substrate. It is a figure which shows the state after mounting several chip | tips of a 1st layer. It is a figure which shows the joining defect generation | occurrence | production position after mounting several chip | tips of a 1st layer. It is a figure which shows the joining defect generation | occurrence | production position after mounting several chip | tips of a 2nd layer. It is a figure which shows the chip | tip arrangement | positioning object position for every chip | tip layer. It is a figure which shows a mode that the chip | tip which has a copper post is planarly arranged. It is a figure which shows a mode that the new resin layer is formed on the resin layer. It is a figure which shows the state after planarization (after CMP). It is a figure which shows a mode that the electrode part provided in the several chip | tip of the 1st layer and the pad electrode provided on the board | substrate are joined. It is a figure which shows the state by which the copper post was crushed by the pressurization operation | movement at the time of joining. It is a figure which shows the board | substrate etc. in which the pad electrode was provided in the surface recessed part. It is a figure which shows the joining state accompanying pressurization. It is a figure which shows a mode that the upper and lower sides of the 2nd temporary board | substrate sealed with resin are reversed. It is a figure which shows a mode that the 1st and 2nd board | substrates resin-sealed are opposingly arranged. It is a figure which shows a mode that new resin is supplied on a temporary board | substrate. It is a figure which shows a mode that a hole part is formed in a resin layer by mask exposure. It is a figure which shows the state in which the copper plating was given. It is a figure which shows the planarization process with respect to the exposed surface after debonding. It is a figure which shows the planarization process with respect to the exposed surface after debonding. It is a figure which shows the relationship between the size of each chip | tip, and the size of a unit part. It is a figure which shows a mode that the several chip | tip of a different size is planarly arranged. It is a figure which shows a mode that the board | substrate with which 2 types of chips were temporarily fixed, and the board | substrate of mounting object are opposingly arranged. It is a figure which shows a mode that two types of chips | tips are simultaneously joined with respect to the board | substrate of mounting object. It is a figure which shows a mode that two types of chips | tips are sequentially joined with respect to the board | substrate of mounting object. It is a figure which shows a mode that the chip | tip of various sizes is laminated | stacked in each unit part of a board | substrate. It is a figure explaining a prior art (reflow). It is a figure explaining another technique. It is a figure which shows the conventional WOW joining technique.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<1. Overview>
1 to 3 are flowcharts showing an electronic component mounting operation according to the present embodiment. By performing each process as shown in these drawings, a plurality of layers of electronic components (here, semiconductor chips (also simply referred to as chips)) are stacked at a plurality of planar positions on the substrate WA. FIG. 26 illustrates a state where a plurality of chips of three layers are stacked. Here, it is assumed that a through electrode VA is provided in each chip (specifically, a silicon (Si) chip) CP (see FIG. 33). However, in each figure, illustration of the penetration electrode VA is abbreviate | omitted suitably for convenience. The present invention is also applicable to the case where the through electrode VA is not provided in each chip CP.

  In this embodiment, basically, each chip CPi of the i-th layer (i = 1, 2,... (That is, i is an integer of 1 or more)) is bonded to the substrate WA to be bonded (see FIG. 26). ) Are repeatedly executed, a plurality of layers of chips are stacked on the substrate WA. The stacking operation of each layer is basically the same as each other. However, in the first layer stacking operation (i = 1), each chip CP1 of the first layer is “directly” with respect to the substrate WA (a chip other than the chip CP1 is interposed between the chip CP1 and the substrate WA). In the stacking operation of the i-th layer after the second layer (i is an integer equal to or greater than 2 (i ≧ 2)), each chip CPi of the i-th layer is bonded to the substrate WA. Are different from each other in that they are bonded to the respective chips of the (i-1) -th layer stacked on each other (so-called “indirectly” each chip CPi is bonded to the substrate WA). In this embodiment, in the chip bonding operation of each layer, the substrate WA that is the original mounting target of each chip CPi is used, and a temporary substrate WTi (described later) for temporary placement (temporary fixing) of each chip CPi is also used. Used.

  More specifically, as shown in FIG. 1, first, steps S11 to S14 are executed, whereby the first layer chip stacking operation (see also step S10 and FIG. 2) is performed on the substrate WA. The plurality of chips CP1 in the first layer are joined (see also FIGS. 6 to 19).

  Next, by executing the following steps S21 to S24, the stacking operation of the chips in the second and subsequent layers (i-th layer) (i ≧ 2) (see also step S20 and FIG. 3) is as follows. (See also FIGS. 20 to 25).

  Step S21: The i-th resin layer RSi is formed on the i-th substrate WTi that is a temporary substrate.

  Step S22: The plurality of chips CPi in the i-th layer are arranged in a plane on the resin layer RSi on the substrate WTi and temporarily fixed in a face-up state.

  Step S23: The plurality of chips CP (i-1) of the (i-1) th layer arranged (directly or indirectly) on the substrate WA and the plurality of i-th layers arranged on the i-th substrate WTi. The substrate WA and the i-th substrate WTi are relatively brought close to each other with the chip CPi facing each other, whereby the plurality of chips CP (i-1) of the (i-1) -th layer and the i-th layer The plurality of chips CPi are relatively brought close together, and the plurality of chips CP (i-1) in the (i-1) th layer and the plurality of chips CPi in the i-th layer are joined (directly). More specifically, the substrate WTi is turned upside down to hold the plurality of i-th layer chips CPi on the substrate WTi in a face-down state, and the plurality of i-th layer chips CPi in the face-down state and the first chip CPi on the substrate WA. The plurality of chips CP (i-1) in the (i-1) layer are relatively close to each other, and the plurality of chips CPi in the i-th layer are replaced with the plurality of chips CP (i-1) in the (i-1) -th layer. And a plurality of chips CP (i-1) in the (i-1) -th layer and a plurality of chips CPi in the i-th layer are bonded to each other.

  Step S24: While maintaining the state in which the plurality of chips CPi in the i-th layer are respectively joined to the plurality of chips CP (i-1) in the (i-1) -th layer, from the plurality of chips CPi in the i-th layer The substrate WTi is separated. The processing in step S24 is also referred to as debonding processing.

  As described above, a plurality of i-th layer chips CPi are further laminated and bonded onto the (i-1) -th layer chips CP (i-1) bonded onto the substrate WA. . In particular, by incrementing the value i and repeatedly executing steps S21 to S24, electronic components are laminated in a plurality of layers (multilayer lamination) at a plurality of planar positions on the substrate WA.

  According to this, it is possible to more easily realize mounting (especially stacked mounting) by arranging a plurality of chips (electronic components) on a substrate in a plane.

  In addition, each process of step S11-S14 regarding a 1st layer is a process similar to the corresponding process of steps S21-S24 regarding each layer after the 2nd layer, respectively. However, the processes in steps S13 and S14 are different from the processes in steps S23 and S24, respectively, in the points described above. That is, in steps S23 and S24, the chip CPi in the i-th layer (i ≧ 2) after the second layer is placed on the chip CP (i-1) in the (i-1) -th layer that has already been stacked. In contrast, in steps S13 and S14, the first layer chip CP1 is directly placed on the substrate WA.

  Below, operation | movement as mentioned above and the chip | tip mounting system 1 (1A) which performs the said operation | movement are demonstrated in detail.

<2. System configuration>
First, the configuration of the chip mounting system 1 will be described.

  FIG. 4 is a top view showing a schematic configuration of the chip mounting system (electronic component mounting system) 1. In FIG. 4 and the like, directions and the like are shown using an XYZ orthogonal coordinate system for convenience.

  The chip mounting system 1 is a system for stacking and mounting multilayer chips at a plurality of planar positions on a substrate (substrate to be mounted on a chip). For example, the chip mounting system 1 can bond a plurality of chips CP1 in the first layer on the target substrate WA. The chip mounting system 1 can also stack and bond a plurality of second-layer chips CP2 and the like on a plurality of first-layer chips CP1 arranged on the substrate WA.

  In this embodiment, the substrate WA is a semiconductor wafer, and each temporary substrate WTi (described later) is a glass substrate. However, the present invention is not limited to this, and each of the substrates WA and WTi may be various substrates.

  As shown in FIG. 4, the chip mounting system 1 is also referred to as a chip supply device 10, a bonding device 30 (also referred to as a COW (Chip On Wafer) bonding device), and a bonding device 50 (a WOW (Wafer On Wafer) bonding device). ), A transport unit 70, and a carry-in / out unit 90. The chip mounting system 1 also includes a spin coater 80 (not shown).

  The spin coater 80 is an apparatus that forms a resin layer RSi on the temporary substrate WTi using a spin coating technique.

  The chip supply apparatus 10 is an apparatus that takes out each chip CP from the diced wafer and supplies each chip CP (CPi) to the COW bonding apparatus 30. The chip supply device 10 includes a protrusion 11 and a chip transfer device 13 (see FIG. 5).

  The COW bonding apparatus 30 planarly arranges a plurality of chips (electronic components) CPi on the resin layer RSi formed on the temporary substrate WTi with the joint surfaces facing upward (face-up state) (planar arrangement). ) And temporarily fixing a plurality of chips to the resin layer RSi. For example, a thermoplastic resin is employed as the resin layer RSi.

  As shown in FIG. 5, the COW bonding apparatus 30 includes a stage 31, a bonding unit 33, an imaging unit 35, a position recognition unit 36 (not shown), and a rotary chip transfer unit 39.

  The imaging unit 35 (specifically, 35a and 35b) acquires an optical image related to marks MC1 and MC2 (described later) as image data. The position recognition unit 36 recognizes the position of each chip CP on the temporary substrate WTi based on the image captured by the imaging unit 35. Specifically, the position recognition unit 36 recognizes the position of each chip in the direction parallel to the substrate plane of the temporary substrate WTi (the position of each chip in the plane parallel to the substrate WTi) using the marks MC1 and MC2. To do.

  The bonding unit 33 is a member that places a chip on the substrate WTi, and is also referred to as a chip mounter. The bonding part 33 has a head part 33H. The head portion 33H can suck and hold the chip, and is also expressed as a chip holding member (electronic component holding member).

  The head portion 33H is movable in the Z direction by a Z direction driving mechanism. The stage 31 is movable in the X direction, the Y direction, and the θ direction by an XYθ direction driving mechanism. Thereby, the relative positional relationship between the bonding portion 33 and the stage 31 can be changed, and as a result, the position of each chip CPi on the temporary substrate WTi can be adjusted.

  The transfer unit 70 uses the transfer robot 71 to transfer the substrate (the substrate WA and the temporary substrate WTi) among the carry-in / out unit 90, the COW bonding apparatus 30, and the WOW bonding apparatus 50. In addition, the transfer robot 71 of the transfer unit 70 also performs an operation of turning the substrate (particularly the temporary substrate WTi) upside down.

  As shown in FIG. 17, the WOW bonding apparatus 50 includes a lower stage 51, an upper stage 53, an imaging unit 55 (specifically 55a and 55b), a position recognition unit 56 (not shown), and the like. The imaging unit 55 acquires a light image related to marks MW1 and MW2 (described later) as image data. Further, the position recognizing unit 56 recognizes the relative positional relationship between the substrate WA held on the lower stage 51 and the temporary substrate WTi held on the upper stage 53 based on the image taken by the imaging unit 55. Specifically, the position recognition unit 56 uses the marks MW1 and MW2 to obtain the relative positional relationship between the substrate WA and the temporary substrate WTi in a direction parallel to the substrate plane of the temporary substrate WTi.

  The upper stage 53 is movable in the Z direction by a Z direction driving mechanism. Further, the lower stage 51 is movable in the X direction, the Y direction, and the θ direction by the XYθ direction drive mechanism. As a result, the relative positional relationship between the upper stage 53 and the lower stage 51 can be changed. As a result, the positional relationship between the temporary substrate WTi and the substrate WA is adjusted, and further, a plurality of chips in the i-th layer. It is possible to adjust the positional relationship between CPi and the plurality of chips CP (i-1) in the (i-1) th layer.

  The WOW bonding apparatus 50 is an apparatus that executes a bonding operation between the substrate WA and the temporary substrate WTi. Specifically, the WOW bonding apparatus 50 holds the substrate WA on the lower stage 51 and holds the temporary substrate WTi on the upper stage 53. In the WOW bonding apparatus 50, the substrate WA is arranged with its bonding surface facing upward (face-up state). The temporary substrate WTi is held on the stage 31 in a face-up state in the COW bonding apparatus 30, but the upper stage 53 in a face-down state (with its bonding surface facing downward) in the WOW bonding apparatus 50. Retained. Specifically, the temporary substrate WTi is taken out of the COW bonding apparatus 30 by the transfer robot 71, turned upside down by the transfer robot 71, transferred to the WOW bonding apparatus 50, and held on the upper stage 53 in a face-down state. Is done.

  The WOW bonding apparatus 50 relatively brings the substrates WA and WTi closer together with the substrate WA and the temporary substrate WTi after being turned upside down facing each other. As a result, the plurality of i-th layer chips CPi held in the face-down state on the temporary substrate WTi after being turned upside down approach toward the substrate WA. Then, the plurality of i-th layer chips CPi are bonded to the substrate WA side.

  The WOW bonding apparatus 50 is an apparatus that collectively bonds (bonds) the plurality of chips CPi in the i-th layer and the plurality of chips CP (i-1) in the (i-1) -th layer. It is also called a collective joining device (gang bonder).

  In the WOW bonding apparatus 50, a separation process for separating the temporary substrate WTi from the plurality of chips CPi in the i-th layer is also executed. This separation process is performed while maintaining a state in which the plurality of i-th layer chips CPi are bonded to the substrate WA side. This separation process is performed by, for example, heating the resin layer RSi of the temporary substrate WTi with a heater (heating processing unit) built in the upper stage 53 that holds the temporary substrate WTi after the ultraviolet irradiation of the resin layer. .

  The WOW bonding apparatus 50 includes a vacuum chamber 59 (not shown) that is a processing space for the substrates WA and WTi (more specifically, the chips CP of each layer) that are objects to be bonded. The WOW bonding apparatus 50 includes the above-described lower stage 51, upper stage 53 (see FIG. 17) and the like in a vacuum chamber 59. The WOW bonding apparatus 50 can execute chip mounting processing (also expressed as bonding processing related to the substrates WA, WTi, etc.) and the like in the vacuum chamber 59.

<3. Chip position adjustment mark MC>
As will be described later, in this embodiment (see steps S12 and S22), each chip CP (CPi) is positioned in the horizontal direction on the temporary substrate WTi using alignment marks MC1 and MC2 (see FIG. 8 and the like). Placed.

  The alignment marks MC1 and MC2 are marks for adjusting the position of the chip CP (electronic component), and are also referred to as chip position adjustment marks (or component position adjustment marks). Here, two marks MC1a and MC1b are provided as the mark MC1 for one chip CP. Similarly, two marks MC2a and MC2b are provided as a mark MC2 per chip CP.

  The two types of marks MC1 and MC2 have different shapes (more specifically, shapes that do not overlap each other). For example, as shown in FIG. 27, a circular mark having a relatively small diameter is used as the mark MC1 (specifically, the marks MC1a and MC1b). On the other hand, as shown in FIG. 28, a circular shape having a relatively large diameter is used as the mark MC2 (specifically, the marks MC2a and MC2b).

  The mark MC1a is provided at the first reference position (planar position) (left front side in FIG. 27) in each chip CP, and the mark MC1b is the second reference position (planar position) in each chip CP (FIG. 27). Then, it is provided on the right back side. Further, the mark MC2a is provided at a regular position (planar position) corresponding to the first reference position of each chip CP on the temporary substrate WTi, and the mark MC2b is the second reference of each chip CP on the temporary substrate WTi. It is provided at a regular position (planar position) corresponding to the position. In short, the mark MC2a is provided at a position corresponding to the mark MC1a, and the mark MC2b is provided at a position corresponding to the mark MC1b. In addition, in order to satisfactorily adjust the relative angle between each chip CP and temporary substrate WTi, marks MC1a and MC1b may be provided at positions separated from each other (for example, near both ends of chip CP). preferable. The same applies to the marks MC2a and MC2b.

  The marks MC1a and MC1b are provided on the upper surface of the face CP1 in the face-up state (the surface opposite to the surface on the temporary substrate WT1 side). However, the present invention is not limited to this, and the marks MC1a and MC1b may be provided on the lower surface (surface on the temporary substrate WT1 side) of the chip CP1 in the face-up state, or inside the chip CP1. It may be provided embedded.

  In this embodiment, each chip CPi in the i-th layer (i = 1, 2,...) Has the same reference position (that is, the same position in each chip) in each chip CPi. It has a mark MC1 (MC1a, MC1b) (see FIG. 8, FIG. 12, FIG. 21, etc.). Further, the plurality of temporary substrates WTi have marks MC2 (MC2a, MC2b) corresponding to the chips CPi in the i-th layer at the same reference position (see FIGS. 6 and 20). That is, the plurality of temporary substrates WTi are substrates on which the same plurality of marks MC2 are respectively attached to the same plurality of positions. In addition, here, a case where each temporary substrate WTi is physically different from each other is illustrated, but the present invention is not limited to this, and each temporary substrate WTi may be physically the same substrate. . In other words, one substrate may be used as each temporary substrate WTi.

<4. Substrate position adjustment mark MW>
As will be described later, in this embodiment (see Steps S13 and S23), both the substrates WA and WTi are positioned in the horizontal direction using the alignment marks MW1 and MW2. The alignment marks MW1 and MW2 are marks for adjusting the relative positions of the substrates WA and WTi, and are also referred to as substrate position adjustment marks.

  The substrate position adjustment marks MW1 and MW2 have different shapes (more specifically, shapes that do not overlap each other), like the above-described chip position adjustment marks MC1 and MC2. For example, a circular shape having a relatively large diameter is used as the mark MW1 (specifically, the marks MW1a and MW1b), and the mark MW2 (specifically, the marks MW2a and MW2b) has a relatively small diameter. A circular shape is used.

  The mark MW1a is provided at a first reference position (planar position) in the substrate WA (left end side of the substrate WTi in FIG. 17), and the mark MW1b is a second reference position (planar position) in the substrate WA (in FIG. 17). It is provided on the right end side of the substrate WTi.

  In the temporary substrate WTi, the mark MW2a is provided at a regular position (planar position) corresponding to the first reference position of the substrate WA (the left end side of the substrate WTi in FIG. 17). The mark MW2b is provided on the temporary substrate WTi at a regular position (planar position) corresponding to the second reference position on the substrate WA (on the right end side of the substrate WTi in FIG. 17). In short, the mark MW2a is provided at a position corresponding to the mark MW1a, and the mark MW2b is provided at a position corresponding to the mark MW1b. In order to satisfactorily adjust the relative angle between the two substrates WA and WTi, the marks MW1a and MW1b are preferably provided at positions separated from each other (for example, near both ends of the substrate WA). The same applies to the marks MW2a and MW2b.

  The marks MW1a and MW1b are provided on the upper surface (surface on which each chip is fixed) of the substrate WA in the face-up state. The marks MW2a and MW2b are provided on the lower surface of the temporary substrate WTi in the face-down state (the surface on which each chip is temporarily fixed). However, the present invention is not limited to this, and each mark (MC1a, MC1b), (MW1a, MW1b) may be provided on the opposite side surface, or may be provided embedded in each substrate WA, WTi. May be.

  In this embodiment, the plurality of temporary substrates WTi have the marks MW2 (MW2a and MW2b) at the same reference position. That is, the plurality of temporary substrates WTi are the same substrates also in the sense that the same mark MW2 is attached at the same position.

<5. Operation details>
Next, the chip mounting operation (electronic component mounting operation) in this embodiment will be described in detail with reference to the flowcharts of FIGS. Here, a case where a plurality of chips are stacked in three layers is illustrated. However, the present invention is not limited to this, and it may be laminated in two layers, or may be laminated in four or more layers. Alternatively, only one chip layer may be provided on the substrate WA.

<5-1. First layer chip stacking process>
First, the stacking operation of the first layer chips (step S10) (see FIGS. 1 and 2) is performed as follows.

<Step S11: Preparation Step>
Specifically, first, in step S11 (FIG. 2), the resin layer RS1 is formed on the substrate WT1 (FIG. 6) which is a temporary substrate (FIG. 7). Note that marks MC2 and MW2 are preliminarily attached to the temporary substrate WT1 before the resin layer RS1 is formed. This resin layer RSi transmits light (infrared light or the like).

  Specifically, for example, a liquid thermoplastic resin (thermoplastic adhesive or the like) is applied onto the substrate WT1 by the spin coater 80, whereby the resin layer RS1 is formed on the substrate WT1. By forming the resin layer using the spin coating method, the resin layer can be formed very easily. However, the present invention is not limited to this, and the resin layer RS1 may be formed on the substrate WT1 by pasting a resin sheet on the substrate WT1. Also by this, a resin layer can be formed very easily.

  The temporary substrate WT1 on which the resin layer RS1 is formed is transferred to the COW bonding apparatus 30 by the transfer robot 71. The temporary substrate WT1 is placed on the stage 31 in the COW bonding apparatus 30 and held on the stage 31 (see FIGS. 4 and 5).

<Step S12: COW process>
Next, in step S12, the plurality of chips CP1 of the first layer are arranged in a plane on the resin layer RS1 in a face-up state and temporarily fixed (see FIGS. 8 to 12, etc.). Here, the “face-up state” of each chip CP is a state in which the bonding surface of each chip CP (for example, the surface to which the solder bumps BU are attached) faces upward.

  Specifically, first, dicing processing is performed in the chip supply apparatus 10 (FIG. 5) to generate a plurality of chips CP. Specifically, a substrate WC having a plurality of electronic circuits is cut into chips in the vertical and horizontal directions. Then, each cut-out chip CP is pushed up one by one by the protruding portion 11 (FIG. 5) of the chip supply device 10 and delivered to the chip transfer device 13 at the position PG1. The chip transfer device 13 adsorbs the chip CP at its tip (lower end), moves further upward, and then moves toward the chip transport unit 39 side of the COW bonding device 30. When the chip transport unit 39 receives the chip CP from the chip transfer device 13 at the position PG3, the chip transport unit 39 transports the chip CP to a position PG5 immediately below the head unit 33H of the bonding unit 33 by a rotation operation around the central axis AX.

  The head portion 33H is slightly lowered to the vicinity of the placement position PG5 of the chip CP, receives the chip CP from the chip transport portion 39, and sucks the chip CP at the tip portion (lower end portion) of the head portion 33H. Thereafter, in order to avoid interference with the head unit 33H, the chip transport unit 39 rotates by a predetermined angle, and the head unit 33H descends in a state where the head unit 33H and the chip transport unit 39 do not interfere with each other, and is sucked and held by the head unit 33H. The chip CP is lowered to the position PG7. As a result, the chip CP adsorbed at the tip of the head portion 33H is placed at a predetermined plane position on the temporary substrate WT1 on the stage 31.

  At this time, using the alignment marks MC1 and MC2 (see FIG. 8), the chip CP (CP1) is positioned and placed on the temporary substrate WT1 as described below.

  As described above, the COW bonding apparatus 30 includes the position recognition unit (also referred to as a position measurement unit) 36. The position recognition unit 36 is a processing unit that recognizes the relative position (specifically, X, Y, θ) between the chip CP and the substrate WTi in the horizontal direction.

  The positioning operation (alignment operation) between each chip CP and the temporary substrate WTi is performed by the position recognition unit 36 in two sets of marks (MC1a, MC2a), (MC1b, MC2b) attached to each chip CP and the temporary substrate WTi. ) Is executed by recognizing the position.

  As shown in FIG. 8, the position recognizing unit 36 has light sources (emitted light) of the imaging units 35a and 35b having a coaxial illumination system in a state where each chip CP (CP1) held by the head unit 33H faces the temporary substrate WT1. The position of the chip CP on the substrate WT1 is recognized using image data relating to the reflected light of illumination light (here, infrared light) emitted from the substrate WT1.

  Specifically, the light emitted from the light source of the imaging unit 35a passes through the hollow portion of the stage 31, the glass temporary substrate WTi, the resin layer RSi, the silicon (Si) portion of the chip, and the like. On the other hand, the light is reflected by the marks MC1a and MC2a, and the reflected light is received by the imaging element of the imaging unit 35a. Thereby, an image including an optical image (optical image by infrared light (reflected light) of each mark portion) regarding each chip and the substrate WTi is acquired as image data Ga. That is, a captured image Ga obtained by simultaneously reading the two types of marks MC1a and MC2a is acquired. The position recognizing unit 36 recognizes the position of a certain set of marks (MC1a, MC2a) attached to each chip and the substrate WTi based on the captured image Ga, and also detects the position of the set of marks MC1a, MC2a. The amount of positional deviation (Δxa, Δya) between each other is obtained (see FIG. 29).

  Similarly, light emitted from the light source of the imaging unit 35b passes through the hollow portion of the stage 31, the glass temporary substrate WTi, the resin layer RSi, the silicon (Si) portion of the chip, and the like. On the other hand, the light is reflected by the marks MC1b and MC2b, and the reflected light is received by the imaging device of the imaging unit 35b. Thereby, an image including an optical image (optical image by infrared light (reflected light) of each mark portion) regarding each chip and the substrate WTi is acquired as the image data Gb. That is, a captured image Gb obtained by simultaneously reading the two types of marks MC1b and MC2b is acquired. The position recognition unit 36 recognizes the position of a certain set of marks (MC1b, MC2b) attached to each chip and the substrate WTi based on the photographed image Gb, and also detects the position of the set of marks MC1ba, MC2b. A positional shift amount (Δxb, Δyb) between them is obtained.

  The imaging units 35a and 35b are movable in the X direction, the Y direction, and the Z direction, respectively, and can be adjusted by changing the imaging range.

  After that, the position recognizing unit 36 temporarily sets each chip CP in the horizontal direction (X direction, Y direction, and θ direction) based on the positional deviation amounts (Δxa, Δya), (Δxb, Δyb) of these two sets of marks. A relative positional deviation amount (Δx, Δy, Δθ) with respect to the substrate WTi is calculated.

  Then, the stage 31 is appropriately driven in two translational directions (X direction and Y direction) and a rotational direction (θ direction) so that the relative shift amount recognized by the position recognition unit 36 is reduced. . As a result, the temporary substrate WTi and the chip CP are relatively moved, and the above-described positional deviation amount is corrected.

  In this way, the alignment operation of the chip CP1 (with respect to the X direction, the Y direction, and the θ direction) is performed.

  Thereafter, the head portion 33H holding one chip CP1 of the first layer is further lowered, and the chip CP1 is placed at a predetermined horizontal position of the resin layer RS of the temporary substrate WT1 (see FIG. 9).

  The position recognition operation (position displacement measurement operation) and the alignment driving operation (position displacement correction operation) as described above are performed at least once even after the chip CP is pressed against the resin layer RS and placed. It is preferable to execute again. According to this, a more accurate alignment operation is executed.

  Furthermore, the mounting operation of the second and subsequent chips of the first layer is performed in the same manner (FIGS. 10 and 11). As a result, as shown in FIG. 12, the plurality of chips CP1 in the first layer are positioned and arranged at predetermined plane positions on the temporary substrate WTi. As described above, by using the two types of marks MC1 and MC2, each of the plurality of chips CP1 in the first layer is positioned in a direction (X, Y, θ) parallel to the substrate plane (main plane) of the temporary substrate WT1. Then, each of the plurality of chips CP1 in the first layer is placed on the resin layer RS1 on the temporary substrate WT1.

  Here, when a thermoplastic resin is used as the resin layer RS, for example, the thermoplastic resin is heated to a temperature T2 (for example, 150 ° C.) lower than a temperature T1 (for example, 200 ° C.) at which the resin layer RS is completely fluidized. Then, each chip is placed in a state where the resin is softened (semi-cured). The temperature T2 is preferably lower than the melting point of the solder so that the solder bumps of each chip do not melt. Thereafter, the resin layer RS1 is cured by cooling (including heating interruption). Thereby, each chip is temporarily fixed to the resin layer RS1.

  As will be described later, in step S12, it is preferable to execute a process (leveling process) for aligning the heights of the plurality of chips in the vertical direction.

<Step S13: WOW process>
Thereafter, the process of step S13 is executed.

  In step S13, first, the substrate WT1 is held by the transfer robot 71. The transfer robot 71 turns the substrate WT1 upside down and transfers the substrate WT1 to the WOW bonding apparatus 50 (see FIG. 16). Then, the substrate WT1 after being turned upside down is held on the upper stage 53 of the WOW bonding apparatus 50 (see FIG. 17). At this time, the plurality of chips CP1 temporarily fixed to the substrate WT1 are held in a face-down state.

  On the other hand, the substrate WA transferred by the transfer robot 71 is held in advance on the lower stage 51 of the WOW bonding apparatus 50.

  In the WOW bonding apparatus 50, both the substrates WA and WT1 are held with their bonding surfaces facing each other.

  Next, using the alignment marks MW1 and MW2, both the substrates WA and WT1 are positioned as described below.

  As described above, the WOW bonding apparatus 50 includes the position recognition unit (also referred to as a position measurement unit) 56. The position recognition unit 56 is a processing unit that recognizes the relative position (specifically, X, Y, θ) between the substrate WA and the substrate WTi in the horizontal direction.

  The positioning operation (alignment operation) between the substrate WA and the temporary substrate WTi (here, WT1) is performed by the position recognition unit 56 with two sets of marks (MW1a, MW2a), ( It is executed by recognizing the position of MW1b, MW2b).

  As shown in FIG. 17, the position recognition unit 56 includes the imaging units 55a and 55b having a coaxial illumination system in a state where the substrate WA held by the lower stage 51 and the substrate WT1 held by the upper stage 53 face each other. The positions of the substrates WA and WTi are recognized using image data relating to the reflected light of illumination light (here, infrared light) emitted from a light source (also referred to as an emission unit).

  Specifically, light (infrared light) emitted from the light source of the imaging unit 55a passes through the hollow portion of the lower stage 51, the silicon substrate WA, the resin layer RS, and the like. On the other hand, the light is reflected by the marks MW1a and MW2a, and the reflected light is received by the imaging element of the imaging unit 55a. Thereby, an image including a light image (light image by infrared light (reflected light)) regarding each mark (MW1a, MW2a) portion on both substrates WA, WTi is acquired as image data Gc. That is, the captured image Gc obtained by simultaneously reading the two types of marks MW1a and MW2a is acquired. The position recognizing unit 56 recognizes the position of a certain set of marks (MW1a, MW2a) attached to both the substrates WA, WTi based on the captured image Gc, and the pair of marks MW1a, MW2a. The amount of misalignment (Δxc, Δyc) is obtained.

  Similarly, light (infrared light) emitted from the light source of the imaging unit 55a passes through the hollow portion of the lower stage 51, the silicon substrate WA, the resin layer RS, and the like. On the other hand, the light is reflected by the marks MW1b and MW2b, and the reflected light is received by the imaging element of the imaging unit 55b. Thereby, an image including a light image (light image by infrared light (reflected light)) regarding each mark (MW1b, MW2b) portion on both substrates WA, WTi is acquired as image data Gd. That is, the captured image Gd obtained by simultaneously reading the two types of marks MW1b and MW2b is acquired. The position recognizing unit 56 recognizes the position of a certain set of marks (MW1b, MW2b) attached to both the substrates WA, WTi based on the captured image Gd, and reciprocally connects the one set of marks MW1b, MW2b. A positional deviation amount (Δxd, Δyd) is obtained.

  The imaging units 55a and 55b are movable in the X direction, the Y direction, and the Z direction, respectively, and can be adjusted by changing the imaging range.

  Thereafter, the position recognizing unit 56 uses the substrate WA and the temporary substrate in the horizontal direction (X direction, Y direction, and θ direction) based on the positional deviation amounts (Δxc, Δyc), (Δxd, Δyd) of these two sets of marks. A relative positional deviation amount (Δx, Δy, Δθ) with respect to WTi is calculated.

  Then, the lower stage 51 is appropriately driven in two translational directions (X direction and Y direction) and a rotational direction (θ direction) so that the relative shift amount recognized by the position recognition unit 56 is reduced. The Thereby, both the substrate WA and the temporary substrate WTi are relatively moved, and the relative positional deviation amount between the two is corrected.

  In this way, the alignment operation of the substrates WA and WTi (with respect to the X direction, the Y direction, and the θ direction) is executed.

  Thereafter, the upper stage 53 is further lowered, the substrate WA and the substrate WTi relatively approach each other, and the plurality of chips CPi (here CP1) held in the face-down state on the temporary substrate WTi and the substrate WA are relatively To approach. In response to this approaching operation, the plurality of chips CPi in the face-down state are respectively placed at predetermined horizontal positions on the substrate WA (see FIG. 18). The “face-down state” of the chip CPi is a state in which the bonding surface of the temporary substrate WTi on which each chip CPi is temporarily fixed (for example, the surface on which the chip CPi is temporarily fixed) faces downward. It is also expressed that the temporary substrate WTi is in a face-down state.

  At this time, in order to make sure that the plurality of chips CPi temporarily fixed to the temporary substrate WTi are brought into contact with the substrate WA, a process (pressurizing process) is performed to apply a predetermined pressure between the chip CPi and the substrate WA. It is preferable.

  Thereafter, the substrate WA is heated by the heater built in the lower stage 51, and the substrate WTi is heated by the heater built in the upper stage 53. As a result, the solder bump BU of each chip CP1 is melted, and a plurality of chips CPi are bonded onto the substrate WA.

  Here, as described above, the chip CPi is accurately positioned on the substrate WTi using the marks MC1 and MC2 (step S12), and the substrate WA and the substrate WTi are accurately positioned using the marks MW1 and MW2. Positioning has been performed (step S13). Therefore, the plurality of chips CPi in the face-down state are accurately positioned and bonded to predetermined horizontal positions of the substrate WA.

  As described above, when the substrate WA and the substrate WT1 are relatively close to each other with the substrate WA and the plurality of first-layer chips CP1 arranged on the substrate WT1 facing each other, the substrate WA and each chip CP1 is relatively close to each other, each chip CP1 in the first layer is placed at a predetermined position on the substrate WA, and the substrate WA and the plurality of chips CP1 in the first layer are joined (directly). The

<Step S14: Debonding process>
Next, in step S14, the “debonding process” is executed. Specifically, the substrate WT1 is separated from the plurality of chips CP1 while maintaining the state where the plurality of chips CP1 are respectively mounted (bonded) at predetermined positions on the substrate WA.

  More specifically, the resin layer RS1 is heated to a predetermined temperature T4 by a heater built in the upper stage 53. Then, in such a heating state, by raising the upper stage 53 while holding the temporary substrate WT1, the temporary substrate WT1 having the resin layer RS1 is peeled from the plurality of chips CP1 (see FIG. 19). FIG. 19 schematically shows the temporary substrate WT1 being peeled from the chip CP1.

  In order to prevent dripping of the thermoplastic resin in the resin layer RS1, the temperature T4 is not high enough to completely fluidize the resin layer RS1, but a temperature at which the resin layer RS1 is semi-cured (for example, 180 ° C.). It is preferable that In order to prevent the solder bump of each chip CP1 bonded to the substrate WA from being melted again, the temperature T4 is preferably lower than the melting point of the solder.

  As described above, the plurality of chips CP1 of the first layer are bonded to the predetermined position of the substrate WA in a state of being planarly arranged on the substrate WA (step S10).

<5-2. Second layer chip stacking process>
Next, the second layer chip stacking operation (step S20) (see FIGS. 1 and 3) is performed as follows. As described above, the corresponding processes in steps S21 to S24 related to the second layer are the same processes as the processes in steps S11 to S14 related to the first layer. However, in steps S13 and S14, the first layer chip CPi is directly placed on the substrate WA, whereas in steps S23 and S24 related to the i-th layer (here, i = 2), it is already stacked. The chip CPi of the i-th layer is placed on the chip CP (i-1) of the completed (i-1) -th layer.

  First, in step S21, the resin layer RS2 is formed on the substrate WT2 which is a temporary substrate (see FIG. 20). Specifically, resin layer RS2 is formed on temporary substrate WT2 using spin coater 80 or the like. The temporary substrate WT2 on which the resin layer RS2 is formed is placed on the stage 31 in the COW bonding apparatus 30 by the transfer robot 71 and held on the stage 31 (see FIGS. 4 and 5).

  In the next step S22, the plurality of chips CP2 of the second layer are arranged in a plane on the resin layer RS2 on the substrate WT2 in a face-up state and temporarily fixed (see FIG. 21).

  Specifically, each chip CPi (here CP2) cut out from the substrate WC by the chip supply device 10 (FIG. 5) is supplied to the COW bonding device 30 by the protruding portion 11 of the chip supply device 10, the chip transfer device 13, and the like. Is transferred to the chip transfer section 39. The chip transport unit 39 transports the chip CP received at the position PG3 to a position PG5 directly below the head unit 33H of the bonding unit 33. In a state where the head unit 33H and the chip transport unit 39 do not interfere with each other, the head unit 33H is lowered, and the chip CP attracted and held by the head unit 33H is lowered from the position PG5 to the position PG7. As a result, the chip CP adsorbed at the tip of the head portion 33H is placed at a predetermined plane position on the temporary substrate WT1 on the stage 31.

  Also in step S22, as in step S12, each chip CP (CP2) is positioned and placed on the temporary substrate WT2 using the alignment marks MC1 and MC2 provided for each chip CP. Also in step S22, it is preferable to execute a process (leveling process) for aligning the heights of the plurality of chips in the Z direction (vertical direction).

  Further, in step S23, first, the temporary substrate WT2 is held by the transfer robot 71. The transfer robot 71 turns the temporary substrate WT2 upside down and transfers the temporary substrate WT2 to the WOW bonding apparatus 50 (see FIG. 22). Then, the temporary substrate WT2 after being turned upside down is held on the upper stage 53 of the WOW bonding apparatus 50 (see FIG. 23). At this time, the plurality of chips CP2 temporarily fixed to the temporary substrate WT2 are held in a face-down state.

  On the other hand, the lower stage 51 of the WOW bonding apparatus 50 holds the substrate WA that has been subjected to the processing of step S10.

  Also in step S23, in the same manner as in step S13, the relative positions in the horizontal direction of both the substrates WA and WT2 are adjusted using the alignment marks MW1 and MW2 with the temporary substrate WT2 and the substrate WA facing each other.

  Thereafter, the upper stage 53 is further lowered to bring the temporary substrate WT2 and the substrate WA facing each other relatively close to each other, whereby the plurality of chips CP2 and the substrate WA in the second layer in the face-down state (specifically, the substrate WA) The plurality of chips CP1) in the first first layer are made relatively close to each other (see FIG. 23). Then, a plurality of i-th layer chips CPi (CP2) in the face-down state are located at predetermined positions of the substrate WA (specifically, the (i-1) -th layer chip CPi (CP1) already stacked on the substrate WA). (See FIG. 24).

  In this way, the substrate WA and the temporary substrate WT2 are positioned in the horizontal direction using the substrate position adjustment mark MW1 on the substrate WA and the substrate position adjustment mark MW2 on the temporary substrate WT2. As a result, the positional relationship between each of the plurality of first layer chips CP1 held on the substrate WA and each of the plurality of second layer chips CP2 held on the substrate WT2 is adjusted, and each chip CP1 is adjusted. And the corresponding chips CP2 are respectively joined.

  Here, each chip CP2 of the second layer is accurately positioned on the substrate WT2 using the marks MC1 and MC2 (step S22), and the substrate WA and the substrate WT2 are accurately positioned using the marks MW1 and MW2. (Step S23). Therefore, each chip CP2 of the second layer in the face-down state is accurately positioned and bonded to a predetermined horizontal position on the substrate WA (specifically, on each chip CP1 of the first layer of the substrate WA).

  Thereafter, in step S24, while maintaining the state in which the plurality of chips CP2 of the second layer are respectively bonded to the substrate WA (specifically, the plurality of chips CP1 of the first layer placed on the substrate WA), The substrate WT2 is separated from the plurality of chips CP2 in the second layer. More specifically, the temporary substrate WT2 having the resin layer RS2 is peeled from the plurality of chips CP2 by raising the upper stage 53 while holding the temporary substrate WT2 while the resin layer RS2 is heated to the temperature T4. (See FIG. 25). FIG. 25 schematically shows the temporary substrate WT2 being peeled from the chip CP2.

  As described above, the plurality of chips CP2 of the second layer are further laminated and bonded onto the plurality of chips CP1 of the first layer bonded onto the substrate WA.

  If it is determined in step S30 (FIG. 1) that the process has not yet been completed, the process returns to step S20 again. Then, in the same manner as the second layer stacking operation, the third layer and subsequent chip stacking operations are executed. If it is determined that the final layer chip stacking operation has been completed (YES in step S30), this process ends.

  For example, the stacking operation of the third-layer chip CP3 is performed as follows.

  First, in step S21, the resin layer RS3 is formed on the temporary substrate WT3, and in step S22, the plurality of chips CP3 of the third layer are temporarily arranged and fixed on the resin layer RS3 in a face-up state.

  Next, in step S23, the temporary substrate WT3 is turned upside down, and the plurality of chips CP3 in the third layer are held in the temporary substrate WT3 in a face-down state, and the substrate WA and the temporary substrate WT3 facing each other are relatively close to each other. To do. Accordingly, the plurality of chips CP3 in the third layer in the face-down state and the plurality of chips CP2 in the second layer on the substrate WA relatively approach each other, and the plurality of chips CP2 in the second layer and the third layer The plurality of chips CP3 are joined to each other.

  Then, in step S24, the temporary substrate WT3 is separated from the plurality of chips CP3 in the third layer while maintaining the state in which the plurality of chips CP3 in the third layer are respectively joined to the plurality of chips CP2 in the second layer. .

  In this way, the plurality of chips CP3 in the third layer are further stacked on the plurality of chips CP1 in the first layer and the plurality of chips CP2 in the second layer stacked on the substrate WA.

<6. Effects of the embodiment>
By the way, by using the above-described conventional technology (prior art document 1), a plurality of single-layer semiconductor chips (hereinafter also simply referred to as chips) are arranged in a plane on a substrate (wafer) and bonded. As a technique to be performed (also referred to as a single layer COW (Chip On Wafer) mounting technique), the following technique can be considered.

  Specifically, first, after a substrate (wafer) is coated with a non-conductive resin and a resin layer is formed on the substrate, a plurality of chips are planarly placed on the resin layer. The chip is temporarily fixed to the resin layer. Then, the substrate and the plurality of chips are collectively heated and pressed from above and below, and the solder bumps provided on the lower surface of each chip (specifically, the solder bumps provided on the substrate side) are melted to form a plurality of chips. Is bonded onto the substrate. The resin layer on the substrate is formed, for example, by applying a resin material to the substrate by a spin coating technique. Or the said resin layer may be formed by sticking a resin sheet on a board | substrate.

  However, this mounting technique (single-layer COW mounting technique) is a technique for mounting a single-layer chip layer in which a plurality of chips are arranged in a plane on a substrate (wafer).

  On the other hand, in recent years, higher integration has been demanded, and a mounting technique (also referred to as a multilayer COW mounting technique) for stacking and mounting a plurality of chip layers in the vertical direction has been demanded.

  However, it is not easy to stack and mount a plurality of chip layers in the vertical direction.

  For example, when the above-described single-layer COW mounting technology is applied to the multi-layer COW mounting technology as it is, a resin layer may be formed on the first-layer chip when the second-layer chip is stacked on the first-layer chip. Desired.

  However, it is not always easy to form the resin layer on the first layer chip when the second layer chip is stacked on the first layer chip. For example, in the state where the first layer chip is already bonded on the substrate, unevenness due to the first layer chip is generated on the surface of the substrate. Therefore, the resin is uniformly applied on the substrate using a spin coating technique. It is difficult to form a simple resin layer. In addition, it is conceivable to attach the resin sheet on each of the plurality of chips of the first layer. In that case, the sheet is individually attached to each of the plurality of chips of the first layer provided on the substrate surface. Is required, and very complicated work occurs.

  On the other hand, according to the above-described aspect, first, a plurality of i-th chips CPi are arranged in a plane in a face-up state on a resin layer RSi formed on a temporary substrate WTi different from the substrate WA. Fixed. Then, the temporary substrate WTi is turned upside down, and the plurality of chips CPi in the i-th layer are held facing the temporary substrate WTi in a face-down state. Next, the temporary substrate WTi and the substrate WA on which the chip CP (i-1) of the (i-1) th layer is disposed in a plane are relatively approached, and the plurality of chips CPi of the ith layer and the (i -1) The chip CP (i-1) in the layer is bonded to each other. Thereafter, the temporary substrate WTi is separated from the plurality of chips CPi in the i-th layer.

  According to this, when the i-th layer chip is stacked on the (i-1) -th layer chip, it is not necessary to form a resin layer on the (i-1) -th layer chip.

  Accordingly, the plurality of chips CPi in the i-th layer can be easily stacked on the plurality of chips CP (i-1) in the (i-1) -th layer. That is, it is possible to more easily realize that a plurality of chips are stacked and mounted on the substrate.

  Further, according to the above-described embodiment, in steps S12 and S22, the temporary substrate WTi corresponding to each of the component position adjustment mark MC1 in each of the i-th chip CPi and each of the i-th chip CPi. Each of the plurality of i-th layer chips CPi is positioned in a direction parallel to the substrate plane of the temporary substrate WTi and mounted on the resin layer RSi on the temporary substrate WTi. Placed. At this time, only the alignment of each chip CPi of one layer (i-th layer) has to be performed on the temporary substrate WTi. In other words, alignment of multiple layers of chips on the temporary substrate WTi is not necessary. Accordingly, it is possible to easily perform an accurate positioning operation of each chip CPi on the temporary substrate WTi.

  Temporarily, a plurality of layers of chips CPi (i = 1, 2,...) Are sequentially stacked and placed on the substrate WA in a face-down state. Utilizing a technique (also referred to as a technique according to a comparative example) in which alignment is performed in a state where a plurality of chips are stacked on the substrate WA.

  In this case, even if a positional shift of any of the plurality of marks MC1 having the same shape stacked on the upper and lower sides is detected, it is determined which position chip (the chip in which layer) the positional shift has occurred. It is difficult to identify. A method of clearly displaying the optical image of the mark attached to the chip of the specific layer on the photographed image by intentionally shifting the in-focus position of the imaging system is also conceivable. However, when the thickness of the chip and the distance between the chips are very small (for example, about 10 μm), such a method may not be used, depending on the focus adjustment accuracy.

  On the other hand, according to the above-described embodiment, in a state in which a plurality of chips are stacked (see FIG. 26), a plurality of chips CP of different layers can place the same mark MC1 (MC1a, MC1b) on the same reference position ( Even in the case of (position in the horizontal direction), it is not necessary to align the chips of the plurality of layers on the substrate WA using the mark MC1 of the chips of the plurality of layers. The alignment of the chips CPi of one layer (i-th layer) may be performed on the temporary substrate WTi different from the substrate WA. Therefore, each chip can be positioned accurately and easily.

  Thereafter, the temporary substrate WTi is turned upside down, and in steps S13 and S23, the substrate WA and the temporary substrate WTi are formed using the substrate position adjustment mark MW1 on the substrate WA and the substrate position adjustment mark MW2 on the temporary substrate WTi. The positional relationship between the substrate WA and the temporary substrate WTi is adjusted by positioning in the direction parallel to the substrate plane of the temporary substrate WTi. According to this, each of the plurality of chips CP1 of the first layer can be accurately positioned and placed at a predetermined position on the substrate WA. Similarly, each chip CPi of the i-th layer held on the temporary substrate WTi is accurately positioned with respect to the corresponding chip CP (i-1) of the (i-1) -th layer held on the substrate WA. Can be placed.

  In particular, in steps S13 and S23, the plurality of chips CPi in the i-th layer are collectively bonded to the corresponding chips CP (i-1) in the (i-1) -th layer. Therefore, an efficient stacking operation is realized. In particular, the bonding time can be shortened as compared to the case where a plurality of chips CPi in the i-th layer are bonded to the corresponding chip CP (i-1) in the (i-1) -th layer. Further, by shortening the heating time on the substrate WA, it is possible to suppress the oxidation of the solder on the substrate WA.

  Moreover, according to the said embodiment, solder joining of step S13 (, S23) is performed in the state in which the solder bump BU is not immersed in resin. Therefore, it is possible to realize highly reliable bonding as compared with the case where the solder bump is immersed in the resin (particularly, when the soldering is performed by adding an activator such as flux to the resin).

  Moreover, according to the said embodiment, it is possible to aim at coexistence of high-speed and reliability by isolate | separating the process (chip temporary fixing process) of step S12, and the process (main joining process) of step S13. is there. In the conventional method, when bonding one chip at a time, it takes about 10 s (seconds) per chip (for example, 5000 pieces require 50000 seconds). On the other hand, in this method, after temporarily fixing the chip on the wafer in about 1 s (seconds), if, for example, 5000 pieces are placed on the wafer and then bonded together, it takes a little more than 1 hour to vacuum or non-oxidize. Atmosphere (nitrogen, Ar gas, etc.) formation treatment, reducing atmosphere (hydrogen gas, formic acid gas, etc.) formation treatment, surface activation treatment (detailed later), etc. are possible, and where more reliable bonding is highly productive It becomes possible. Further, in the COW bonding apparatus 30, it takes 5000 seconds to mount 5000 chips with a mounting time of 1 s (seconds) per chip, and in the WOW bonding apparatus 50, vacuuming is performed over a little over 1 hour. Etc. are performed to perform batch joining. Therefore, the processing time in the COW bonding apparatus 30 and the processing time in the WOW bonding apparatus 50 are close to each other (ideally the same), and good in both processes (between the COW process and the WOW process). Balance (ie, good line balance) can be achieved. That is, bonding with higher reliability is possible at a high productivity with a balanced line.

  For example, the steps of S12 and S22 in the COW bonding apparatus 30 are temporarily fixed (temporarily fixed) to the temporary substrate at a high speed, and after the thousands are mounted, the processes of steps S13 and S23 in the WOW bonding apparatus 50 are performed in a nitrogen atmosphere. By performing the above, it is possible to easily realize bonding with higher reliability.

  More specifically, it is preferable to realize the following solder joint. Hereinafter, the solder bonding operation and the like in step S23 will be described in more detail, but the same applies to step S13.

  In step S23 (FIG. 3), when each substrate WTi is transferred into the vacuum chamber 59 (not shown), the internal space of the vacuum chamber 59 is depressurized to be in a vacuum state, and then the nitrogen space is placed in the internal space of the vacuum chamber 59. Is supplied. It should be noted that an appropriate period (for example, about 1 hour) is required from the start of pressure reduction in the internal space of the vacuum chamber 59 to the completion of nitrogen filling. Thereafter, as described above, the positioning operation and the bonding operation regarding both the substrates WA and WTi are executed. Note that the positioning operation may be performed before decompression, not after decompression.

  In this way, in the processing space (vacuum) in which the plurality of chips CP (i-1) in the (i-1) layer on the substrate WA and the plurality of chips CPi in the i layer on the temporary substrate WTi are accommodated. In the chamber 59), the solder bumps BU of the plurality of chips CPi and the electrode portions of the plurality of chips CP (i-1) (electrode portions facing the upper-layer solder bumps BU (with the decompression process and nitrogen supply process over a predetermined period) (Not shown)) is performed (see FIGS. 23 and 24). By performing the WOW bonding process as described above in a nitrogen atmosphere, it is possible to realize good solder bonding while preventing solder oxidation, and it is possible to perform fluxless bonding. Moreover, it is more preferable if it is in a reducing atmosphere (hydrogen gas, formic acid gas, etc.).

  Here, in recent years, with the miniaturization of semiconductor manufacturing technology, the thickness of electronic components (chips and the like) has also become smaller (thinner). This is because, when a through electrode is provided on a chip or the like by a chip stacking technique, the diameter of the through electrode is further miniaturized, and the production of a “shallow hole” having a miniaturized diameter is miniaturized. This is due to the fact that it is relatively easy to make a “deep hole” of a different diameter.

  However, the conventional method (specifically, the method of heating and soldering a chip placed on a wafer (also referred to as C4 method (reflow method))) is applied to a relatively thin chip as it is. In the case of application, there arises a problem that the chip warps due to the influence of heat during heating. In this conventional method (so-called reflow method), each chip is heated in the furnace without being pressurized in the vertical direction (see FIG. 72). FIG. 72 is a diagram showing a heating state of the chip in such a conventional method. As shown in FIG. 72, in the conventional method, a substrate having a single-layer chip disposed on the surface thereof is heated in a heating furnace, and solder bonding between the chip and the substrate is performed. At this time, as shown by a broken line in FIG. 72, the thin chip (CP) is warped by heating.

  On the other hand, in order to avoid such a “warp” problem, for example, a technique in which another chip is stacked on one chip (substrate) and heated while being pressurized and then cooled and bonded in a pressurized state. (See FIG. 73). In the technique shown in FIG. 73, a predetermined number of chips (five in FIG. 73) are stacked vertically. Then, the stacked chips (laminated chips) are heated between the lower heat stage HS and the upper heat tool HT and heated in the stacked direction (vertical direction), and then cooled. As a result, interlayer bonding (solder bonding) in the multilayer chip is performed. As described above, this technique is a technique for performing pressure heating and cooling (cooling in a pressurized state) for each predetermined number (for example, five) of chips stacked in the vertical direction according to the number of stacked chips. .

  However, in this method, the chips are stacked in the vertical direction (although the chips are stacked in a vertical direction), the heating and the like are performed for each stacked chip (a set of stacked chips) in a plan view. Therefore, enormous time is required to create a large number of laminated chips. For example, when a heating / cooling time of about 10 seconds is required per chip (specifically, per set of laminated chips), it takes 50000 seconds to produce 5000 laminated chips. Moreover, even if it is 10 seconds, it is not a sufficient time for improving the reliability of solder bonding, and there is also a problem of bonding in the air, which is a participating atmosphere.

  On the other hand, according to the said aspect regarding step S23 etc., since the aggregate | assembly of the chip | tip integrated | stacked by the board | substrate unit instead of every chip | tip (chip unit) is joined together, increase of time can be suppressed.

  For example, if an extra 1 hour process is performed for each chip when processing 5000 chips as described above, 5000 hours are further required. On the other hand, in the above aspect, if the above-described processing is performed collectively on 5000 chips, the processing increase time is about 1 hour as a whole. In this case, the required time (increase in processing time) per chip in the 1 hour nitrogen atmosphere forming process (total time of the vacuuming process and nitrogen supply time) is less than 1 second (0.72 Second (= 1 * 3600/5000)).

  In this way, it is possible to more efficiently realize mounting a plurality of electronic components in a planar arrangement on the substrate. That is, high productivity can be obtained.

  Further, in the method shown in FIG. 73, solder bonding is performed in the atmosphere. In this technique, flux is used to prevent solder oxidation.

  However, there is a problem that the residue of the flux causes poor bonding, and that the cleaning of the flux requires labor. Further, as processing is miniaturized, there is a problem that it is difficult to remove the flux that has entered the minute gap. Therefore, the reliability of solder bonding in the air is not high.

  On the other hand, according to the above aspect, since the bonding is performed not in the air but in a nitrogen atmosphere or the like, it is not necessary to use a flux for preventing oxidation. Therefore, it is possible to obtain a good solder joint having high reliability by reducing the flux.

  Thus, according to the above aspect, it is possible to obtain high productivity while obtaining highly reliable solder joints.

<7. Leveling process>
As described above, in steps S12 and S22, the following leveling process is preferably performed.

  There may be variations in the thickness of the plurality of chips CPi in the i-th layer (for example, the plurality of chips CP1). When such a variation exists, when each chip CP1 is placed on the surface in accordance with the surface position reference of the resin layer RS (the upper surface position reference of the resin layer RS) in steps S12 and S22, a plurality of chips CP1 are obtained as shown in FIG. There is a difference in the upper end position of each chip CP1 (the variation in the upper end position) between the chips CP1.

  The variation in the upper end position appears as variation in the lower end position of the chip CP1 disposed on the upper side when the temporary substrate WT1 is turned upside down in step S13 (, S23) to face the substrate WA. Then, if each chip CP1 is pressed toward the substrate WA as it is, a certain chip CP1 is in contact with the substrate WA, while another chip CP1 is not in contact with the substrate WA and may float from the substrate WA. is there.

  In order to avoid such a situation, in steps S12 and S22, a leveling step of aligning the heights of the upper end positions of the plurality of i-th chips CPi temporarily placed on the resin layer RS in the face-up state is provided. Is preferred. According to this, it is possible to absorb the thickness variation of the plurality of chips CPi.

  For example, in steps S12 and S22, as shown in FIG. 14, parallel to the substrate WTi, on the upper end side of the plurality of chips of the i-th layer temporarily placed face-up on the resin layer RS on the substrate WTi. What is necessary is just to make the height of the upper end position of several chip | tip CPi of the i-th layer uniform by pressing the hold | maintained planar member PL. At this time, the resin layer RS is preferably heated to a temperature T2 that realizes a semi-cured state. Then, after pressing the planar member PL and aligning the upper end positions of the plurality of chips CPi in the i-th layer, the resin layer RS is cooled and solidified, whereby each chip CPi is placed in a predetermined position (predetermined horizontal). (Direction position and predetermined vertical position). Thus, the process (leveling process) which aligns the vertical position (Z direction position) of the upper end side of a some chip | tip collectively using the planar member PL should just be performed.

  Alternatively, leveling processing may be performed for each chip in step S12.

  Specifically, as shown in FIG. 15, the head portion 33H (see FIG. 5) holding each chip CPi of the i-th layer in a face-up state is lowered, and each chip CPi is placed on the resin layer RSi. To do. More specifically, the position of the head portion 33H in the Z direction is adjusted so that the tip of the head portion 33H is lowered to the predetermined position Z0. This position Z0 is also expressed as the upper end position (Z direction position) of each chip CPi. The position Z0 is a common (identical) position among the plurality of chips CPi. At this time, each chip CPi in the face-up state is placed on the resin layer RSi with its lower surface (surface opposite to the upper bonding surface) side buried in the resin layer RSi.

  The resin layer RSi has a thickness (for example, several tens of micrometers to several hundreds of micrometers or more) that can absorb variations in chip thickness. The resin layer RSi is formed of a thermoplastic resin and has a semi-cured state when the chip is placed. For example, the head portion 33H is heated to a predetermined temperature, and the resin layer RSi may be softened by heating the resin layer RSi to the temperature T2 via each chip CPi.

  After the plurality of chips CPi are placed on the resin layer RSi with the upper end positions aligned as described above, the semi-cured resin layer RSi is cooled and solidified. Thus, the chips CPi are temporarily fixed to the resin layer RSi in a state where the heights of the upper end positions of the plurality of chips CPi in the i-th layer are aligned with each other.

  According to such leveling processing, it is possible to absorb variations in the thickness of the plurality of chips CPi. Note that the leveling process as described above may be performed in the COW bonding apparatus 30 or may be performed in the WOW bonding apparatus 50.

  Such a leveling process is also useful when the flatness of the stage is impaired along with the heating process (particularly when the leveling process is performed by the WOW bonding apparatus 50 or the like). For example, by performing the leveling process as described above in a situation where the center portion of the stage (specifically, the upper stage 53 or the lower stage 51) protrudes by a minute amount from the peripheral portion in accordance with the heat treatment, the surface of the stage Even in the lowered flatness state, the upper end positions of the plurality of chips CPi placed on the surface can be aligned. In the aspect in which the planar member PL is pressed against the plurality of chips CPi as shown in FIG. 14, the planar member PL is not limited to the one having a completely flat surface, but a very slightly curved surface (for example, A convex curved surface or a concave curved surface). The upper end positions of the plurality of chips CPi may be aligned by pressing the planar member having a very slightly curved surface against the plurality of chips CPi. At this time, by joining with the joining object having the same curved shape, the size of the gap between the joining portions facing each other can be made uniform with respect to the plurality of joining portions (arranged in the horizontal direction). Further, the planar member PL may be an object to be bonded (other objects to be bonded). By leveling in a state where the joint portions are aligned and in a solid phase having a melting point or lower, opposing joint portions can be joined very well. In this case, after leveling below the melting point and curing the resin, it is possible to easily increase the bonding temperature and then perform bonding with high reliability. In addition, it is preferable that a minute positional deviation at the time of leveling is joined again after alignment to improve the positional accuracy.

  Considering the 8-inch wafer size, the variation in chips is about several μm, whereas the variation (flatness) due to thermal expansion at about 250 ° C. of the 8-inch wafer size stage is on the order of several tens of μm. In the case of joining in the solid phase, the swell of the stage appears as a pressure difference and does not often lead to poor bonding, but in the case of joining in the liquid phase such as solder joining, the flatness of the stage is joined as it is. As a result, the bumps may be crushed at a portion where the height is reduced, and a short circuit may occur between adjacent bumps. Therefore, it has been difficult to perform solder bonding at the wafer level with the conventional method. According to this method, leveling is performed in a state where the solder is in a solid phase at a temperature near the solder melting point, so that it is possible to perform solder melt bonding by absorbing the swell of the stage even at the solder bonding temperature. The leveling process is preferably performed by the WOW bonding apparatus 50, but the leveling process may be performed using another apparatus (such as a dedicated leveling apparatus) having a similar thermal expansion state (similar to the thermal expansion state of the WOW bonding apparatus 50). May be performed.

<8. Modified example>
The present invention is not limited to the above-described contents, and various modifications can be made.

<8-1. Resin layer>
For example, in the said embodiment etc., although the case where resin layer RS was formed with a thermoplastic resin was illustrated, it is not limited to this, Resin layer RS is formed with photocurable resin (ultraviolet curable resin etc.). You may do it.

  When the resin layer RS is composed of a photocurable resin (such as an ultraviolet curable resin), in steps S12 and S22, each chip is formed by curing or semi-curing the resin by light irradiation (such as ultraviolet irradiation). What is necessary is just to temporarily fix to temporary board | substrate WTi. In steps S14 and S24, each chip may be separated from the temporary substrate WTi by using a laser ablation technique as will be described later.

  When the resin layer RS is made of a photocurable resin (such as an ultraviolet curable resin), the leveling process may be performed for each chip in steps S12 and S22 as follows.

  It is assumed that the resin layer RSi has not yet been irradiated with light (ultraviolet rays) and the resin layer RSi has a semi-cured state immediately before the chip placement.

  As shown in FIG. 15, the head portion 33H holding each chip CPi of the i-th layer in the face-up state is lowered, and each chip CPi is placed on the resin layer RSi. At this time, the position of the head portion 33H in the Z direction is adjusted so that the tip of the head portion 33H is lowered to the predetermined position Z0. As described above, this position (the upper end position of each chip CPi) Z0 is a common (identical) position among the plurality of chips CPi.

  Then, the mounting region (partial region) RG of the resin layer RSi is cured by irradiating light (ultraviolet rays) to the mounting region RG of the chip CPi immediately after mounting in the semi-cured resin layer RSi. Is done. As a result, the chip CPi is temporarily fixed to the resin layer RSi.

  A similar operation is repeatedly performed for a plurality of chips CPi. Specifically, each time the upper end positions of the plurality of chips CPi are aligned and placed on the resin layer RSi, light (ultraviolet rays) is focused on the placement area of each chip in the semi-cured resin layer RSi. The placement region (partial region) of the resin layer RSi is cured by partial irradiation. Thus, the chips CPi are temporarily fixed to the resin layer RSi in a state where the heights of the upper end positions of the i-th layer chips CPi are aligned with each other.

  Further, the resin layer RS may be formed of a thermosetting resin.

  When the resin layer RS is made of a thermosetting resin, in steps S12 and S22, each chip is temporarily fixed to the temporary substrate WTi by heating and curing the uncured resin. Good. In steps S14 and S24, each chip may be separated from the temporary substrate WTi by using a laser ablation technique (a technique for generating bubbles in the resin layer by irradiating a laser beam).

  In addition, by simply controlling the adhesive strength (adhesive strength of thermosetting resin as an adhesive), it is possible to secure a strength sufficient to withstand bonding and to provide an intermediate strength that can be peeled off after bonding. .

  In steps S12 and S22, the leveling process may be performed for each chip as follows. Specifically, first, the upper end position of each chip is arranged at a predetermined position Z0 in the vertical direction. Thereafter, the tip of the head portion 33H is heated to a predetermined temperature, and the resin layer RSi is heated via each chip to cure the resin layer RSi, and each chip may be temporarily fixed to the resin layer RSi. .

<8-2. Debonding process>
In the above-described embodiment and the like, as the debonding process in step S24 (S14), the technique of heating and melting the resin layer RS to the temperature T4 and peeling the temporary substrate WTi from the chip CP is exemplified, but the present invention is not limited thereto. .

  For example, the internal structure of the resin layer RS is changed by irradiating the resin layer RS formed of a thermoplastic resin with ultraviolet rays, and then the temperature T5 (for example, about 160 ° C.) (lower than the above-described temperature T4) The temporary substrate WTi may be peeled off from the chip CP by low-temperature heating with (temperature) (T5 <T4). The ultraviolet rays may be irradiated to the resin layer through the temporary substrate (glass substrate) WTi formed of glass.

  More specifically, first, in step S11 (, S21), the temporary substrate WTi is coated with a thermoplastic adhesive, pre-baked at about 180 ° C., and the solvent component is volatilized to form the temporary substrate WTi on the temporary substrate WTi. A cured resin layer RSi is formed.

  Thereafter, in step S12 (, S22), the head portion 33H and / or the stage 31 is heated at a low temperature, and the plurality of i-th chips CPi are placed on the resin layer RSi whose surface is adhesive. Further, the resin layer RSi is heated at a temperature T12 (for example, 200 ° C.) for about 10 minutes to transition the resin layer RSi to a semi-cured state, and then a leveling process is performed using the planar member PL. Thereafter, the resin layer RSi is cooled to temporarily fix each chip CPi to the temporary substrate WTi. In this modified example, each chip CPi is preferably provided with solder bumps by high-temperature solder (for example, melting point 280 ° C.). The resin is denatured by a heating reaction at 200 ° C. for 10 minutes, and it can withstand without heating even at 300 ° C. during soldering.

  Next, in step S13 (, S23), the upper stage 53 and / or the lower stage 51 of the WOW bonding apparatus 50 are heated to melt the solder bumps of the chips CPi, and the chips CPi of the i-th layer are transferred to the substrate WA. (Or to each chip CP (i-1) of the (i-1) th layer).

  In step S14 (, S24), after the resin layer RSi is heated to a relatively low temperature T5, ultraviolet rays are transmitted through the temporary substrate (glass substrate) WTi and irradiated onto the resin layer RSi. The internal structure of the resin layer RSi is changed by ultraviolet irradiation, and the resin layer RSi is easily peeled from each chip CPi by, for example, low-temperature heating of about 160 ° C.

  The debonding process as described above may be performed.

  Alternatively, in the case where the resin layer RS is formed of an ultraviolet curable resin (UV curable resin), a technique (so-called laser) that generates bubbles in the resin layer by irradiating the resin layer cured by ultraviolet irradiation with laser light. The temporary substrate WTi may be peeled off from the chip CP by an ablation technique. The laser beam may be irradiated to the resin layer through the temporary substrate (glass substrate) WTi formed of glass, similarly to the ultraviolet rays.

<8-3. Heat treatment during bonding by the WOW bonding apparatus 50>
In the above embodiment and the like, in steps S13 and S23, the substrate WA is heated by the heater on the lower stage 51 side, and the temporary substrate WTi is heated by the heater on the upper stage 53 side, whereby the solder bumps BU of each chip CPi are formed. Although a case where a plurality of chips CPi are bonded on the substrate WA is illustrated as an example, the present invention is not limited to this.

  For example, in the WOW bonding apparatus 50 or the like, a plurality of layers stacked in the vertical direction are heated by heating only the member holding the chip (upper stage 53) without heating the member holding the substrate WA (lower stage 51). You may make it suppress the temperature rise of chip | tip CP (i-1) of a comparatively lower layer among the chip | tips of a layer. This prevents re-melting of the solder bumps of the relatively lower chips CP (i-1) that are already bonded. As a result, it is possible to more surely prevent the once-completed bonding of the chips of each layer from being removed by heating when bonding the chips of the upper layer.

  Moreover, in the said embodiment etc., although the case where the thing of the same material is used as a solder of chip | tip CPi of each layer is illustrated, it is not limited to this. For example, a solder having a relatively low melting point may be used as the solder of the chip CPi of the relatively upper layer. For example, a solder bump having a melting point lower than that of the solder bump of the first layer chip CP1 may be used as the solder bump of the second layer chip CP2. According to this, remelting or the like of the solder bumps of the chips CP (i-1) that are already bonded to each other is prevented. Alternatively, a solder material whose melting temperature rises at the time of reheating after being once heated and melted and alloyed (as compared with heating before alloying) may be used.

<8-4. Underfill process after debonding>
Moreover, in the said embodiment etc., although the case where step S21 is performed as it is after step S14 is illustrated, it is not limited to this. For example, an underfill process is provided between step S14 related to the first layer and step S21 related to the second layer (or between step S24 related to the i-th layer and step S21 related to the next (i + 1) -th layer). You may do it. That is, you may make it provide an underfill process after a debonding process.

  In this underfill process, a non-conductive resin (NCP: Non conductive Paste) is used as an underfill resin RU by a dispenser between the substrate WA and the lower surface of the chip CP1 (or the upper surface of the lower chip CP (i-1)). And a lower surface of the upper chip CPi) (see FIG. 30). The filled underfill resin RU is cured by heating or the like. According to this, it is possible to more reliably prevent the once-completed joining of the chips of each layer from being removed by heating at the time of joining the chips of the upper layer.

  Further, a residue cleaning step may be added between step S14 and step S21 (when the above underfill step is provided, etc., before the underfill step). The cleaning step is also effective, for example, for cleaning residues that may occur when using a flux together during solder bonding and resin residues after debonding.

<8-5. Position adjustment by visible light>
Moreover, in the said embodiment etc., although the case where the image for position recognition is acquired using infrared light is illustrated, it is not limited to this. For example, an image for position recognition may be acquired using visible light.

  Specifically, as shown in FIG. 31, a light-transmitting glass substrate that transmits visible light is used as the temporary substrate WTi, and each mark MC1 (MC1a, MC1b) is placed on each chip CPi in the face-up state. It is provided on the surface FT on the temporary substrate WTi side. Then, an image obtained by simultaneously capturing optical images of the marks MC1 and MC2 obtained through the glass substrate WTi and the light-transmitting resin layer RSi that transmits visible light is acquired as a position recognition image. That's fine.

  Similarly, as shown in FIG. 32, light relating to marks MW1 and MW2 obtained by disposing imaging portions 55a and 55b on the temporary substrate WTi side (not on the substrate WA side) and transmitting through the glass substrate WTi and the resin layer RSi. You may make it acquire the image which image | photographed the image simultaneously as a position recognition image.

  As the resin layer RSi, a resin layer having a light transmitting property that transmits both infrared light and visible light may be used.

<8-6. Example of modification in solder bonding>
Further, the solder bonding (steps S13 and S23) in the above-described embodiment or the like may be realized as follows. Here, as in the above embodiment, each chip CP is provided with a through electrode (for example, made of copper (Cu)) VA, and a solder bump BU is provided on the surface of the through electrode VA. A case is assumed (see FIG. 33). Here, the case where the solder bumps BU are provided only on the upper surface of the through electrode VA is illustrated, but the present invention is not limited to this, and the solder bumps BU are also provided on the lower surface of the through electrode VA (that is, on both upper and lower sides). You may do it. Alternatively, the solder bump BU may be provided only on the lower surface of the through electrode VA.

  In this modified example, a case where the bonding operation using the WOW bonding apparatus 50 is executed in a nitrogen atmosphere with management of a temperature profile (see FIG. 35) at the time of solder bonding. By managing the temperature change (temperature change with time) during solder bonding, it is possible to realize better solder bonding while preventing solder oxidation.

  More specifically, when each substrate WTi is transferred into the vacuum chamber 59 in step S23, nitrogen is supplied into the vacuum chamber 59 after the internal space of the vacuum chamber 59 is depressurized and brought into a vacuum state.

  Thereafter, as described above, both the substrates WA and WTi are held in a state in which their joint surfaces face each other, and a positioning operation or the like is performed.

  Then, the temporary substrate WT2 and the substrate WA facing each other are relatively close to each other, and the plurality of i-th layer chips CPi (specifically, their solder bumps BU) and the plurality of (i−1) -th layers on the substrate WA. Chip CP (i-1) (specifically, its electrode portion (through electrode VA)) is relatively close to the chip CP (i-1), and then contacted and pressurized to start a bonding operation (solder bonding operation) ( (See FIG. 34).

  In this modified example, as described above, the bonding operation is performed with management of the temperature profile at the time of solder bonding (see FIG. 35). Specifically, first, each substrate or the like is heated using a heater on the upper stage 53 side and / or a heater on the lower stage 51 side, and the temperature is set to the temperature TE1 (for example, room temperature) in the temperature increase period TMa (for example, 20 minutes). To a predetermined temperature TE2 (for example, 280 ° C.). Then, after the constant temperature period TMb (for example, 10 minutes) has elapsed, the temperature is lowered from the temperature TE2 to the temperature TE1 in the temperature decrease period TMc (for example, 40 minutes).

  As described above, in step S23, the bonding of the plurality of i-th layer chips CPi to the substrate WA is performed with the solder bonding process (specifically, the plurality of (i−1) -th layers on the substrate WA). The solder bonding process is performed using solder provided on at least one bonding surface of the chip CP (i-1) and the plurality of chips i in the i-th layer), and the solder bonding process is performed with a predetermined temperature profile. Executed. In such a temperature profile, a corresponding time (here, a total of 70 minutes) is required.

  In addition, although step S23 was mainly demonstrated here, it is the same also about step S13.

  According to such a modified example, since the solder bonding operation in which the temperature profile is controlled is performed, it is possible to obtain a very good solder bonding.

  In particular, as described above, since an assembly of chips integrated in units of substrates, not in units of chips, is joined together, an increase in time can be suppressed.

  For example, assuming that a further 70 minutes of process is used for each chip when processing 5000 chips, approximately 5800 hours are further required. On the other hand, if the same processing is applied to 5000 chips, the total increase time is 70 minutes. In this case, the required time per chip related to the temperature profile management time of 70 minutes is also expressed as about 1 second (= 70 * 60/5000).

  Therefore, it is possible to obtain high productivity while obtaining highly reliable solder joints.

  In this modified example, for example, in the COW process by the COW bonding apparatus 30, it takes 5000 seconds to load 5000 chips with a mounting time of 1 s (seconds) per chip. In the WOW process, the temperature profile (temperature increase process, temperature decrease process, etc.) is managed over a period of just over an hour (here, 70 minutes + α), and batch bonding is performed. Therefore, the processing time in the COW bonding apparatus 30 and the processing time in the WOW bonding apparatus 50 are close to each other (ideally the same), and good in both processes (between the COW process and the WOW process). Balance (that is, good line balance) can be realized, and more reliable bonding is possible at a high productivity of 1 second / chip.

  In addition, here, a case where solder bonding is performed in a nitrogen atmosphere is illustrated, but the present invention is not limited to this. For example, solder bonding or the like may be performed in another non-oxidizing atmosphere such as an argon (Ar) gas atmosphere. Alternatively, the solder bonding operation may be performed by performing only evacuation without supplying nitrogen (that is, in vacuum). Alternatively, the solder bonding operation may be performed in a reducing atmosphere. Specifically, the WOW bonding apparatus 50 evacuates the vacuum chamber 59, then supplies hydrogen gas (and / or formic acid gas, etc.) to the vacuum chamber 59 to form a reducing atmosphere, and solders in the reducing atmosphere. You may make it perform joining operation | movement.

  Further, here, the case where the solder bump BU is directly provided on the through electrode VA is illustrated, but the present invention is not limited to this. For example, a solder bump BU may be provided on a copper post (copper pillar) formed on the through electrode VA.

<8-7. Surface activation treatment (beam irradiation, etc.)>
In the above-described embodiment and the like, solder bonding is exemplified, but the present invention is not limited to this, and the present invention can be applied to other bonding. For example, the present invention can also be applied to a case where electrode materials (for example, copper (Cu)) are directly bonded (direct bonding) without using solder (solder bump). Here, a case is illustrated in which each chip CP is provided with a through electrode (for example, made of copper (Cu)) VA, and a copper (Cu) post PS is further provided on the surface of the through electrode VA. (See FIG. 36).

  In particular, at the time of direct bonding of electrode materials (for example, copper (Cu)), as described below, the surface activation treatment is performed on the bonding surface (bonding surface) of the electrode material. It is preferable to bond materials (solid phase bonding). In other words, it is preferable to perform a surface activation process on the electrode material provided on the bonding surface when bonding the plurality of i-th chips CPi to the substrate WA. Below, such a modified example is demonstrated.

  Conventionally, it is generally considered that bonding between layers is performed by a bump (solder bump) provided on a copper post as a wiring. However, as illustrated here, a surface activation process is performed. According to this, it is also possible to realize interlayer bonding by directly bonding copper posts without using bumps. That is, it is possible to perform interlayer bonding by direct bonding of electrodes. Solder bumps and copper posts are collectively referred to as protruding electrodes.

  In this modified example, the WOW bonding apparatus 50 is placed on the bonding surface of each chip (electronic component) placed on the substrate WA and the temporary substrate WTi in a chamber under reduced pressure (vacuum chamber). It is possible to activate each bonding surface of each chip (electronic component) with an atomic beam or the like and bond both bonding surfaces to each other. With such a configuration, it is possible to perform surface activation treatment on both bonding surfaces and perform solid-phase bonding on both the bonded surfaces.

  Specifically, the WOW bonding apparatus 50 according to the modified example further includes a beam irradiation unit BM (not shown). In the bonding process (steps S13 and S23), the following operation is performed using the beam irradiation unit BM and the like. Hereinafter, step S23 will be mainly described, but the same applies to step S13.

  In this modified example, a vacuum state is formed in the internal space of the vacuum chamber 59 of the WOW bonding apparatus 50 after the substrate WTi is loaded in step S23.

  Thereafter, the surface of the electrode material of each chip is irradiated with an atomic beam of a specific substance (here, argon (Ar)) using a beam irradiation unit BM or the like, and an argon bombardment process (surface activation process) is executed. (See FIG. 43). The vacuuming process and the argon bombardment process require appropriate times (for example, 30 minutes and 5 minutes), respectively.

  Here, as shown in FIG. 43, the beam irradiation unit BM accelerates an ionized specific substance (such as argon) by an electric field toward a bonding surface of an object to be bonded (such as copper (Cu) that is an electrode material). By releasing the specific substance, the bonding surface of the object to be bonded is activated. In other words, the beam irradiation unit BM performs a surface activation process that activates the bonding surface of the object to be bonded by irradiating (releasing) energy waves.

  As shown in FIG. 43, in this surface activation treatment, the adhering substance 99 on the bonding surface is removed by causing a specific substance (such as argon) to collide with the bonding surface of the object to be bonded (here, the bonding surface of Cu). As a result, a dangling bond (indicated by a short line segment in FIG. 43) which is an unbonded hand of the surface atom of the object to be bonded is exposed. Such surface activation treatment is performed on the bonding surface of at least one of the two chips (bonded objects) CPi and CP (i-1) (both in this case), so that dangling bonds are formed on the two chips CPi. , CP (i-1) are formed on the bonding surface. Thereafter, the dangling bonds are bonded to each other by bringing the bonding surfaces of these objects to be bonded into contact with each other. Thereby, two to-be-joined objects are joined at an atomic level. According to this, a very strong joined state can be realized.

  Specifically, the bonding surface of an electrode material (here, Cu) or the like, for example, the bonding surface of the copper post PS of the i-th layer chip CPi and the through electrode of the (i-1) -th layer chip CP (i-1). A surface activation process is performed by irradiating a bonding surface of VA (here, made of copper) with an atomic beam of a specific substance (here, argon (Ar)).

  Thereafter, as described above, the positioning operation and the bonding operation regarding both the substrates WA and WTi are performed (see FIG. 40).

  Further, during the bonding operation, heat treatment is also performed in a state where both the substrates WA and WTi are pressurized. For example, a heat treatment for raising the temperature to about 150 ° C. is performed. Note that this heat treatment also requires a corresponding time (for example, 30 minutes).

  As described above, in step S23, the plurality of chips CP (i-1) in the (i-1) th layer and the plurality of chips CPi in the ith layer are provided on at least one of the bonding surfaces (here, both). The surface activation treatment is performed on the electrode material (specifically, the bonding surface thereof). Thereafter, the substrate WA in a state where the plurality of chips CP (i-1) in the (i-1) th layer disposed on the substrate WA and the plurality of chips CPi in the ith layer disposed on the substrate WTi are opposed to each other. The substrate TWi approaches relatively. Then, the plurality of chips CP (i-1) in the (i-1) th layer and the plurality of chips CPi in the ith layer are relatively close to each other, and the plurality of chips CP (i-1) in the (i-1) th layer. -1) and the plurality of chips CPi in the i-th layer are bonded to each other.

  According to the bonding process involving such a surface activation process, it is possible to obtain a very good bond. Specifically, by performing the surface activation treatment, bonding at a relatively low temperature can be realized. More specifically, bonding is possible at room temperature (25 ° C.) to 150 ° C. in a vacuum, and bonding at a relatively low temperature of about 200 ° C. to 250 ° C. is possible in a nitrogen atmosphere. It is. In the case where the surface activation treatment is not involved, it is necessary to heat to a relatively high temperature (for example, about 400 ° C. for bonding between copper and about 300 ° C. for bonding between solders). On the other hand, according to the surface activation treatment, since bonding at a relatively low temperature can be realized, it is possible to suppress the thermal expansion and realize high-precision bonding. Furthermore, when bonding between different materials is performed, the difference in thermal expansion caused by the difference in thermal expansion coefficient between both materials (dissimilar materials) is realized by realizing bonding at a relatively low temperature. It is also possible to suppress it.

  In particular, as described above, since an assembly of chips integrated in units of substrates, not in units of chips, is joined together, an increase in time can be suppressed.

  For example, assuming that a process such as a surface activation process of 65 minutes (30 minutes + 5 minutes + 30 minutes) is used for each chip when processing 5000 chips, about 5400 hours are further required. On the other hand, if the same processing is applied to 5000 chips, the total increase time is 65 minutes. In that case, the required time per chip for the surface activation treatment for 1 hour is also expressed as about 0.8 seconds (= 65 * 60/5000).

  Therefore, it is possible to obtain a high productivity while obtaining a direct bonding between very good electrode materials by the surface activation treatment. In other words, regarding the electronic component mounting process (chip bonding process), it is possible to suppress an increase in processing time while obtaining high reliability.

  In addition, although the case where the heat processing which heats up to about 150 degreeC in a vacuum is performed is illustrated here, you may make it not perform heat processing.

  Here, the case where the surface activation process is performed in a vacuum is illustrated, but the present invention is not limited to this, and the surface activation process may be performed in a nitrogen atmosphere. In this case, in the heating step after joining, it is preferable to raise the temperature to about 200 ° C. to 250 ° C. and heat it.

  Further, here, a case where the copper post PS is provided only on the upper surface of the through electrode VA is illustrated, but the present invention is not limited to this, and the copper post PS is also provided on the lower surface of the through electrode VA (that is, both upper and lower sides). May be provided (see FIG. 38). In such a case, by repeating the above-described processing, it is possible to obtain a multilayer chip as shown in FIG. 41 (five-layer chip in FIG. 41).

  Alternatively, the copper post PS may be provided only on the lower surface of the through electrode VA (see FIG. 37).

  Furthermore, the through electrodes VA may be directly joined without providing the copper post PS (see FIG. 39). In this case, it is preferable that the surface activation treatment is performed not only on the electrode portion (through electrode VA) but also on the silicon (Si) portion before bonding. According to this, not only the electrode parts but also the silicon parts can be bonded well. Then, by repeating the above-described processing, it is possible to obtain a multilayer chip (five-layer chip in FIG. 42) as shown in FIG. In FIG. 42, a multilayer chip is produced in which not only the electrode parts of adjacent chip layers adjacent in the vertical direction but also the silicon (Si) parts of the adjacent chip layers are well bonded. Moreover, since not only the electrode portion but also the silicon portion is bonded, the bonding strength between adjacent chips can be improved.

  Here, a beam irradiation process is illustrated as the surface activation process, and an atomic beam irradiation process is illustrated as the beam irradiation process. However, the present invention is not limited to this.

Specifically, ion beam irradiation processing or the like may be employed as the beam irradiation processing.
Here, in the atomic beam irradiation process, after ionized specific substances (such as argon) are accelerated by an electric field, they are immediately combined with the charges supplied in the beam irradiation unit, and the electrical characteristics thereof are neutralized. And the specific substance electrically neutralized goes to a to-be-joined object at high speed.

  On the other hand, in ion beam irradiation, an ionized specific substance (argon or the like) is released while being ionized after being accelerated by an electric field. And the said specific substance heads to a to-be-joined object with an ion state. Note that argon or the like in an ionic state is electrically neutralized by being combined with electric charges before reaching the surface of the object to be bonded.

  As described above, the timing of electrical neutralization differs between an ion beam and an atom beam, but they are common in that an ionized specific substance (such as argon) is accelerated by an electric field. And it is common also in the point that the surface activation process as shown in FIG. 43 is performed when the accelerated specific substance collides with a joining surface at high speed.

  Moreover, in the above, although argon is mainly illustrated as a specific substance, it is not limited to this. For example, other inert gases (such as krypton (Kr) or xenon (Xe)) may be used as a specific substance in energy wave irradiation.

  Moreover, in the above, the case where the penetration electrode VA is provided also to the board | substrate WA is illustrated. In this case, it is preferable that the through electrode VA of each chip on the substrate WT1 and the corresponding through electrode VA on the substrate WA are also joined together with a surface activation process in the same manner as described above. The substrate WA may be provided with electrodes (pads or the like) that are not through electrodes (see FIG. 55). In that case, it is preferable that the through electrode VA of each chip on the substrate WT1 and the corresponding electrode (pad or the like) on the substrate WA are also joined together with the surface activation process in the same manner as described above.

<8-8. Surface activation treatment (hydrophilic treatment, etc.)>
Moreover, in the above, although the case where a joining process was performed accompanying the surface activation process by beam irradiation (argon bombardment etc.) was illustrated, it is not limited to this. For example, the present invention can also be applied to a case where a bonding process is performed with a surface activation process using a hydrophilic process. Below, such a modified example is demonstrated.

  Here, the case where the through electrodes VA of the upper and lower layers of the chips CP are directly joined without the copper post PS being provided on the through electrode of each chip CP is illustrated. However, the present invention is not limited to this. For example, the present invention may be applied when the copper post PS is provided on at least one of the upper surface and the lower surface of the through electrode VA.

  In this modified example, the WOW bonding apparatus 50 is placed on the bonding surface of each chip (electronic component) placed on the substrate WA and the temporary substrate WTi in a chamber under reduced pressure (vacuum chamber). Plasma treatment is performed on the bonding surface of each chip (electronic component) to activate each bonding surface and bond both bonding surfaces to each other.

  Specifically, the WOW bonding apparatus 50 according to the modified example further includes a plasma processing unit PM (not shown). Then, in the bonding process (steps S13 and S23), the following operation is executed using the plasma processing unit PM and the like. Hereinafter, step S23 will be mainly described, but the same applies to step S13.

  In step S23, after the substrate WTi is carried in, a vacuum state is formed in the internal space of the vacuum chamber 59 of the WOW bonding apparatus 50.

  Thereafter, oxygen plasma is applied to the surface of each chip (both the exposed surface portion of the through electrode and the silicon portion) using the plasma processing unit PM and the like, and hydrophilic treatment (surface activation treatment) is performed. The In the hydrophilization treatment, OH groups are generated by exposure to an environment containing moisture. It is also possible to generate OH groups with moisture contained in the atmosphere simply by exposure under a low vacuum after the plasma treatment. Here, oxygen plasma processing is illustrated, but other plasma processing (for example, nitrogen plasma processing) may be performed.

  Thereafter, as described above, the positioning operation and the bonding operation regarding both the substrates WA and WTi are executed.

  Further, during the bonding operation, heat treatment is performed in a state where both the substrates WA and WTi are pressurized. For example, a heat treatment for raising the temperature to about 150 ° C. is performed. Note that this heat treatment requires an appropriate time (for example, 1 hour).

  44 to 46 are diagrams for explaining a bonding principle involving a surface activation process (hydrophilization process) using plasma. Here, “surface activation treatment” by plasma is a chemical reaction treatment of the surface layer of the bonding surface of the object to be bonded by active ions or the like in the plasma to activate the bonding surface of the object to be bonded. It includes a process for facilitating the joining of objects.

As shown in FIG. 44, OH groups (hydroxyl groups) are respectively attached to the Si surface and Cu surface by the hydrophilization treatment (surface activation treatment) using oxygen plasma. Specifically, by causing oxygen ions in the oxygen plasma to collide with the bonding surface with a relatively strong collision force, the OH group easily adheres to the bonding surface, replacing the oxygen ions adhering to the bonding surface. The state of the bonding surface is changed. In this state, moisture (H ₂ O) in the atmosphere or OH groups based on moisture contained in the water gas additionally supplied into the vacuum chamber 59 adheres to the bonding surface, and a hydrophilic treatment is performed.

  Next, as shown in FIG. 45, both objects to be bonded (chip CPi and chip CP (i-1)) are brought into contact and temporarily bonded by hydrogen bonding.

Thereafter, as shown in FIG. 46, H ₂ O (water) is released by heating. Thereby, a strong bond of Si—O—Si and Cu—O—Cu is obtained.

  Thus, in step S23, oxygen plasma is used for the bonding surfaces of the plurality of chips CP (i-1) in the (i-1) th layer and the bonding surfaces of the plurality of chips CPi in the ith layer. The surface activation treatment (hydrophilization treatment) was applied. Thereafter, the substrate WA in a state where the plurality of chips CP (i-1) in the (i-1) th layer disposed on the substrate WA and the plurality of chips CPi in the ith layer disposed on the substrate WTi are opposed to each other. The substrate TWi approaches relatively. Then, the plurality of chips CP (i-1) in the (i-1) th layer and the plurality of chips CPi in the ith layer are relatively close to each other, and the plurality of chips CP (i-1) in the (i-1) th layer. -1) and the plurality of chips CPi in the i-th layer are bonded to each other.

  According to the joining process involving such a hydrophilic treatment (surface activation process), it is possible to obtain a very good joint.

  In particular, as described above, since an assembly of chips integrated in units of substrates, not in units of chips, is joined together, an increase in time can be suppressed.

  Therefore, it is possible to obtain high productivity while obtaining very good direct bonding between electrode materials by surface activation treatment (hydrophilization treatment). In other words, regarding the electronic component mounting process (chip bonding process), it is possible to suppress an increase in processing time while obtaining high reliability.

  In addition, although the case where the surface activation process accompanied by a hydrophilization process is performed using plasma (hydrophilization process by a dry process (surface activation process)) is illustrated here, it is not limited to this. Hydrophilic treatment (surface activation treatment) by a wet process may be performed without using plasma. For example, after the substrates WA and WTi are immersed in a hydrogen fluoride (hydrofluoric acid) (HF) solution, the substrate may be washed with pure water to perform a hydrophilic treatment.

  Further, the surface activation treatment by plasma irradiation is also expressed as surface activation treatment by energy wave irradiation.

<8-9. Non-defective chip and bonded state inspection>
In the above description, it is preferable that each chip CP supplied from the chip supply device 10 to the COW bonding device 30 is confirmed in advance to be a non-defective product. Specifically, the chip supply device 10 determines whether each of the plurality of chips CP is a non-defective chip or a non-defective chip (a pass / fail determination is made), and a chip determined to be a non-defective chip (that is, a non-defective chip). ) Is preferably supplied to the COW bonding apparatus 30.

  By the way, even if COW bonding is performed using only non-defective chips, the non-defective product ratio of the multilayer chip may be very small due to the occurrence of bonding failure at the time of bonding each layer. For example, if the bonding failure rate of each layer is 20% (in other words, the bonding non-defective rate is 80%), the pass rate (non-defective product rate) of the three-layer laminated chip is about 50% (= 0.8). * 0.8 * 0.8). Such a laminating operation is inefficient. This was an issue with the traditional WOW process.

  Therefore, as described below, when a plurality of chips CP are arranged in each layer and stacked in multiple layers at each position, the bonding between the upper and lower chips is performed each time the plurality of chips CP in each layer is arranged. It is preferable to perform a state inspection (a quality inspection regarding the conduction state between the upper and lower layers) and adjust the location of the next layer based on the inspection result.

  Specifically, after the plurality of i-th layer chips CPi on the substrate WA are arranged in a plane, the bonding state inspection for each of the plurality of i-th layer chips CPi in a state of being arranged on the substrate WA. (Inspection of electrical connection state between upper and lower layers (continuity inspection) or the like) is executed. This bonding state inspection is performed by inspecting the bonding state from the first layer to the i-th layer (or the bonding state from the substrate WA to the i-th layer including the bonding state between the substrate WA and the first layer). Are preferred. The bonded state inspection may be performed by bringing a probe into contact with each target electrode and inspecting conduction between the target electrodes.

  Then, when the plurality of chips CP (i + 1) in the (i + 1) th layer next to the ith layer are arranged in a plane, it is determined that the bonding state inspection on each of the plurality of chips CPi in the ith layer is defective. The position corresponding to the chip (bonding defective chip) is excluded from the arrangement target position. Also, defective chip positions detected in the bonding state inspection up to the (i-1) th layer are also excluded from the arrangement target positions. Thereby, the plurality of chips in the (i + 1) -th layer are arranged in a plane excluding the positions corresponding to the bonding failure chips up to the i-th layer. The (i + 1) th layer next to the i-th layer is also expressed as a new i-th layer after incrementing the value i.

  According to this, a new chip of the next layer is arranged in a stacked manner (stacked arrangement) only on a chip determined to have good connection (chip with good connection). Therefore, in the COW bonding apparatus 30, an efficient chip placement operation (stacking operation) can be realized. For example, since it is not necessary to arrange a new chip on a poorly bonded chip, it is not necessary to perform an unnecessary chip arrangement operation. In addition, it is possible to eliminate chip waste caused by placing a new chip (particularly a good chip) at the position of a defective bonding chip.

  When a through electrode or the like is present on the substrate WA, the same operation may be performed by inspecting the continuity between the upper side and the lower side of the substrate WA.

  Hereinafter, such a modification will be described with reference to FIGS. 47 to 51. Below, it demonstrates centering on difference with the said embodiment. In FIGS. 48 to 51, in order to show the corresponding positional relationship between each chip and the substrate WA, each chip of the temporary substrate WTi is vertically inverted and disposed on the substrate WA. .

  First, at a time prior to step S11 (see FIG. 2), a continuity test of the substrate WA is performed. In this continuity test, continuity between the upper side and the lower side of the substrate WA by each through electrode is inspected. In this continuity test, when a defective through electrode is detected, the chip mounting position corresponding to the defective through electrode is determined as a defective position on the substrate WA. FIG. 47 is a diagram showing a defect position on the substrate WA. In FIG. 47, positions (three positions in this case) PN1, PN2, and PN3 determined as defective positions among a plurality of chip arrangement positions on the substrate WA (positions of each diamond portion surrounded by a broken line) are hatched. It is shown with an attached.

  This determination result is used in step S12. Specifically, in step S12, the plurality of chips CP1 in the first layer exclude the positions determined as defective positions in the continuity test on the substrate WA itself from the chip placement target, and are on the temporary substrate WT1 (in detail). Are arranged in a plane on the resin layer RS1). FIG. 48 is a diagram illustrating a state after mounting the plurality of chips CP1 in the first layer. FIG. 48 shows a state where a plurality of chips CP1 in the first layer are arranged at positions other than the hatching positions PN1, PN2, and PN3 (chip positions indicated by solid diamonds without hatching).

  In addition, after the plurality of chips CP1 of the first layer are planarly arranged on the substrate WA (specifically, after the step S14 (and before the step S22)), the chips CP1 are arranged on the substrate WA. The bonding state inspection is performed on each of the plurality of chips CP1 in the first layer in the above state.

  In this bonding state inspection, for example, continuity between the lower side of the through electrode of the substrate WA and the upper side of the through electrode in the first layer chip is inspected. When a connection failure (bonding failure) is detected in this bonding state inspection, the chip placement position corresponding to the defective bonding is determined as a defective position related to the first layer chip. FIG. 49 is a diagram illustrating a position where a bonding failure occurs after mounting the plurality of chips CP1 in the first layer. In FIG. 49, among the positions of a plurality of chips (each diamond-shaped portion surrounded by a broken line) on the substrate WA, the positions (three positions here) PN4, PN5, and PN6 determined as defective positions are hatched. Has been shown.

  This determination result is used in step S22 regarding the chip arrangement of the second layer. Specifically, in step S22, the plurality of chips CP2 in the second layer exclude the positions PN4, PN5, and PN6 determined as defective positions in the bonding state inspection related to the first layer chip from the chip placement target, A plane is arranged on the substrate WT2 (specifically, on the resin layer RS2). In addition, the plurality of chips CP2 in the second layer also exclude the positions PN1, PN2, and PN3, which are determined as defective positions in the continuity inspection on the substrate WA itself, from the chip placement target, and on the temporary substrate WT2 (in detail The resin layer RS2 is planarly disposed.

  Furthermore, after the plurality of chips CP2 of the second layer are arranged in a plane on the substrate WA, in detail, after step S24 related to the second layer chip (and before step S22 related to the third layer chip). , A bonding state inspection is performed on each of the plurality of chips of the second layer in a state of being arranged on the substrate WA.

  In this bonding state inspection, for example, continuity between the lower side of the substrate WA and the upper side of the through electrode in the second-layer chip CP2 is inspected. Specifically, it is inspected whether or not conduction through the first layer chip between the lower side of the substrate WA and the upper side of the through electrode in the second layer chip is normal. When defective bonding is detected in this bonding state inspection, the chip placement position corresponding to the defective bonding is determined as a defective position related to the second layer chip CP2. FIG. 50 is a diagram illustrating a position where a bonding failure occurs after mounting the plurality of chips CP2 of the second layer. In FIG. 50, positions (three positions here) PN7 and PN8 determined as defective positions among the positions of a plurality of chips (each diamond-shaped portion surrounded by a broken line) on the substrate WA are hatched. It is shown.

  This determination result is used in step S22 regarding the next third-layer chip arrangement. Specifically, in step S22, the plurality of chips CP3 in the third layer exclude the positions PN7 and PN8, which are determined as defective positions in the bonding state inspection related to the second layer chip CP2, from the chip placement target. A plane is arranged on the substrate WT3 (specifically, on the resin layer RS3). Further, the positions PN1, PN2, and PN3 determined as defective positions in the continuity inspection regarding the substrate WA itself, and the positions PN4, PN5, and PN6 determined as defective positions in the bonding state inspection regarding the first layer chip CP1 are also arranged in the chip. Excluded from the target. That is, the third plurality of chips CP3 are arranged in a plane on the temporary substrate WT3 (specifically, on the resin layer RS3), excluding all the cumulative defective positions PN1 to PN8 so far from the chip arrangement target. .

  FIG. 51 is a diagram showing the chip placement target position for each chip layer. In order from the bottom, the chip placement target positions for the first-layer chip CP1, the second-layer chip CP2, and the third-layer chip CP3 are shown. Chips of each layer are arranged at rhombus-shaped positions not hatched.

  Thereafter, by repeating the same operation, chips are stacked at a plurality of planar positions where no bonding failure has occurred to form a multilayer chip.

  In this embodiment as well, the plurality of chips CP arranged in each layer are preferably “good chips” (chips that have been confirmed to be good (chips that have been determined to be good) in advance).

<8-10. New resin layer and CMP treatment>
Moreover, in the said embodiment etc., although the leveling process (step S12, S22) by adjusting the chip position in a perpendicular direction (up-down direction) etc. was illustrated, it is not limited to this. For example, when the electrode portions are provided so as to protrude from the chips of each layer, the vertical positions of the tip portions of the electrode portions are aligned between the plurality of chips using the following method. Also good. Here, a case where a copper (Cu) post PS further protrudes from the upper surface of each chip CP is illustrated (see FIG. 52). FIG. 52 shows a situation in which there are variations in chip thickness and bump height between chips. Note that the copper post PS may be disposed on the upper side of the through electrode provided on the chip CP, or may be disposed on the upper side of a portion other than the through electrode.

  Hereinafter, such a modification will be described with reference to FIGS. 53 to 56. In the following description, differences from the above embodiment will be mainly described.

  In this modified example, in step S12, first, the plurality of chips CP1 in the first layer are positioned and arranged in a plane on the substrate WT1 as in the above-described embodiment (see FIG. 52). FIG. 52 shows a state in which a plurality of chips CP1 are arranged at predetermined positions. Each chip CP1 is provided with an electrode portion (copper post PS) protruding from the upper surface thereof.

  Next, using a spin coater 80 (resin coating device) or the like, resin is supplied to the upper side of the plurality of chips CP1 in the first layer on the substrate WT1. This resin is supplied (deposited) to a position above the upper surface of the plurality of chips CP1 so as to cover the upper surface of the plurality of chips CP1 of the first layer arranged in a plane on the resin layer RS1. Then, the resin layer RS12 is formed (FIG. 53). The material of the resin layer RS12 may be the same as the material of the resin layer RS1, or may be different from the material of the resin layer RS1. FIG. 53 is a diagram illustrating a state in which a new resin layer RS12 is formed on the resin layer RS1. In FIG. 53, a cross section of the resin layer RS12 and the like is shown. However, in plan view (top view), the electrode portion protruding from the upper surface of the plurality of chips CP1 in the first layer is made of resin. The layers RS12 are interspersed (in a plane).

  Then, after the resin RS12 is cured, a planarization polishing process (specifically, chemical mechanical polishing (CMP)) is applied to the resin portion (resin layer RS12) on the upper surface of the plurality of chips CP1 of the first layer. Mechanical Polishing) is performed. The flattening polishing process may be performed in the spin coater 80 or in an apparatus separate from the spin coater 80. The “planarization polishing process” is not limited to a chemical mechanical polishing (CMP) process, and may be a non-chemical mechanical polishing process or the like.

  By this polishing treatment, the surface of the resin layer RS12 is slightly scraped off and the surface is flattened. In particular, it is preferable that the surface of the resin layer RS12 is scraped (ground) to the extent that all the copper posts PS are exposed on the surface of the resin layer RS12. FIG. 54 is a diagram showing a state after planarization (after polishing). According to this, as shown in FIGS. 52 to 54, even when there is a variation in the thickness of the chip and / or a variation in the bump height, there is a variation in the thickness of the chip and / or the variation in the bump height. By absorbing, the upper end positions of the copper posts PS (electrode portions) can be aligned between the plurality of chips CP1. That is, it is possible to suppress a variation in the upper end position of the electrode portions of the plurality of chips CP1 and realize a good bonding.

  As described above, in this modified example, in step S12, the resin is supplied until the upper surface of the plurality of first layer chips CP1 arranged on the temporary substrate WT1 is covered. Then, after the resin is cured, an electrode portion which is a resin portion on the upper surface of the plurality of chips CP1 in the first layer and which protrudes from the upper surface of the plurality of chips CP1 in the first layer is dotted in a plane. A planarization polishing process (CMP process or the like) is performed on the existing resin portion.

  In subsequent step S13, the electrode portions provided on the plurality of chips CP1 of the first layer and the corresponding portions of the substrate WA (pad electrodes provided on the substrate WA, through electrode surfaces provided on the substrate WA, etc.) ) And are joined.

  FIG. 55 shows a state in which the electrode portions provided on the plurality of chips CP1 of the first layer and the pad electrodes PD provided on the substrate WA are joined.

  In such bonding, the copper post PS of the chip CP1 and the pad electrode PD on the substrate WA are well connected. Specifically, as shown in FIG. 56, the copper post PS is in good contact with the pad electrode PD in a state where the copper post PS is crushed with the pressurizing operation during the joining. At this time, the resin around the copper post PS is appropriately deformed according to the deformation of the copper post PS. Therefore, the state in which the electrode material is well sealed with the resin material is maintained, and good resin sealing can be realized. In particular, it is possible to obtain both the sealing effect regarding the plurality of chips and the effect of suppressing the variation in the vertical position between the plurality of chips without separately providing the underfill process and the leveling process.

  In addition, although the case where the pad electrode PD is disposed so as to protrude on the substrate WA is illustrated here, the present invention is not limited thereto.

  For example, as shown in FIG. 57, a pad electrode PD may be provided in a recess provided on the surface of the substrate WA. Also in this case, as shown in FIG. 58, the copper post PS of the chip CP1 and the pad electrode PD of the substrate WA are satisfactorily bonded to each other by deformation of the resin (specifically, the resin is pushed and spread).

  Alternatively, when the upper end of the pad electrode PD exists at the same position (vertical direction position) as the upper surface of the substrate WA, the same processing as described above may be performed.

  Moreover, in the above, although step S12, S13 was demonstrated, it is the same also about step S22, S23.

  Specifically, in step S22, the resin is used until the upper surface of the plurality of i-th chips CPi (CP2 and the like) arranged in a plane on the resin layer of the i-th temporary substrate WTi (for example, WT2) is covered. Supplied. Then, after the resin is cured, an electrode portion that is a resin portion on the upper surface of the plurality of chips CPi in the i-th layer and protrudes from the upper surface of the plurality of chips CPi in the i-th layer is dotted in a plane. A planarization polishing process (CMP process or the like) is performed on the existing resin portion.

  Thereafter, in step S23, electrode portions provided on the plurality of chips CPi of the i-th layer and corresponding portions of the plurality of chips CP (i-1) of the (i-1) -th layer (through electrode surface or pad electrode). And are joined. Specifically, the temporary substrate WT2 (WTi) is turned upside down as shown in FIG. 59, and the chips CP2 (CPi) and the substrate WA arranged on the temporary substrate WT2 (WTi) as shown in FIG. Each chip CP <b> 1 (CP (i−1)) arranged in the counter is arranged to face. Then, the chips arranged opposite to each other are joined.

  Prior to step S23, at the time of debonding in step S14 (or step S24) immediately before that, resin layer RS1 is removed along with separation of substrate WT1 from chip CP1. The resin layer RS1 is preferably formed very thin (for example, thickness = 1 micrometer) in step S11. In that case, there is almost no step between the exposed surface of the resin layer RS12 and the surface of the chip CP1 (new bonding surface) after the resin layer RS1 is removed (see FIG. 59). Even when the step portion is generated, when the resin layer RS22 provided on the substrate WT2 comes into contact with the resin layer RS12 on the substrate WA and the chip CP1 in the bonding process in step S23. In addition to being pressurized from above and below, the stepped portion (gap portion) can be filled by expanding in a planar manner. Therefore, it is possible to realize good resin sealing.

  Further, after the substrate WTi is separated from the i-th layer chip CPi (that is, after debonding), the exposed surface of the chip CPi disposed on the substrate WA (new bonding surface, in other words, the substrate WTi is separated). A flattening polishing process (CMP process or the like) may be performed on the surface (separated surface)). For example, as shown in FIG. 64, a planarization polishing process may be performed on a new bonding surface (the upper surface in FIG. 64) of the chip CP1 on the substrate WA. According to this, a step between the exposed surface of the resin layer RS12 and the surface of the chip CP1 (new bonding surface) and chip thickness variations can be more reliably eliminated.

  Further, the planarization of the chip CPi on the substrate WA after debonding can be applied even when the resin layer RS12 is not provided. For example, when the resin layer RS12 is not provided as shown in FIG. 65 (see FIG. 19), the upper exposed surface of the chip CPi disposed on the substrate WA (in other words, a new bonding surface ( A flattening polishing process (CMP process or the like) may be performed on a new chip mounting surface)). According to this, the variation in the height of each chip CPi can be absorbed, and the upper end position of the chip after being arranged on the substrate can be aligned. In this case, the substrate WA or the like in the state shown in FIG. 65 is subjected to an underfill process, and a resin is prefilled between the substrate WA and the chip CPi to form a state similar to that shown in FIG. Then, it is preferable that a flattening polishing process is performed.

  Further, by performing the planarization polishing process on the new bonding surface of the chip after debonding in this way, it is not necessary to thin the chip in advance, and the thickness of the chip after the debonding is reduced. It is possible to adjust (in detail thinning). In general, it is relatively difficult to handle a thin chip, but according to such an embodiment, it is only necessary to handle a relatively thick chip before debonding, so that the chip handling can be improved.

  Further, in the above modification, the case where the chip having the copper post formed on the surface thereof is planarly arranged on the substrate in step S12 is illustrated, but the present invention is not limited to this. For example, the copper post PS may be formed on the chip surface after a plurality of chips are arranged in a plane on the substrate. Hereinafter, such an aspect will be described with reference to FIGS.

  Specifically, in step S12, first, the plurality of chips CP1 in the first layer are each positioned and planarly arranged on the substrate WT1 as in the above embodiment. However, at this time, each chip CP does not yet have the copper post PS on its upper surface.

  Next, the resin is supplied until the upper surface of the plurality of chips CP1 of the first layer arranged in a plane on the resin layer RS1 is covered. FIG. 61 shows a state where a resin is further supplied onto the resin layer RS1 and a new resin layer RS12 is formed. Here, it is assumed that the resin layer RS12 is formed of a photocurable resin.

  Further, a mask exposure process or the like is performed on the resin portion on the upper surface of the plurality of chips CP1 in the first layer, and as shown in FIG. 62, in the resin portion on the upper surface of the plurality of chips CP1 in the first layer, Electrode forming holes HL are provided at respective positions in the plane. Specifically, in the resin layer RS12 on the upper surface of the plurality of chips CP1 of the first layer, light is selectively irradiated only on the portion other than the portion corresponding to the hole HL. The portion corresponding to the hole HL is not irradiated with light, and the portion corresponding to the hole HL is not cured. And the hole part HL like FIG. 62 is formed by removing the resin material of the non-hardened part among resin layer RS12.

  Next, an electrode material is supplied to the surface of the resin layer RS12. As a result, the electrode material is also supplied to each hole HL, and an electrode portion is formed on the upper surface of the plurality of chips CP1 in the first layer. For example, the surface of the resin layer RS12 is subjected to copper plating to supply copper (Cu) to each hole HL, and a copper plating layer ML is formed on the upper side of the plurality of chips CP1 of the first layer. At the same time, a copper post PS is formed on the upper surface of the plurality of chips CP1 in the first layer (see FIG. 63).

  Thereafter, a planarization polishing process (CMP process or the like) is performed on the resin layer RS12 on the upper surface of the plurality of chips CP1 of the first layer. By this polishing process, the copper plating layer on the upper side of the plurality of chips CP1 of the first layer is scraped off, and all the copper posts PS are exposed on the upper side. Thereby, each chip CP1 having the same state as that of FIG. 54 is obtained. Thereafter, the same processing as described above is performed.

  According to this, as shown in FIG. 61 to FIG. 63 and FIG. 54, even when there is a variation in the thickness of the chip, the variation in the thickness of the chip is absorbed, and between the plurality of chips CP1. The upper end position of the copper post PS (electrode part) can be aligned. That is, it is possible to suppress a variation in the upper end position of the electrode portions of the plurality of chips CP1 and realize a good bonding.

  The same applies to step S22. In particular, according to such a method, variation in the thickness of the chip is absorbed for each layer, and a uniform thickness resin layer (RS12 or the like) in which a plurality of chips CPi are sealed with resin is formed. For this reason, even when chips are stacked in multiple layers, it is possible to satisfactorily absorb variations in the thickness of the chip by the upper chip layer without being affected by the lower chip layer.

  Further, the planarization after debonding is preferably performed in the same manner as described above. That is, it is preferable that the same flattening polishing process or the like is performed on the exposed surface (new chip mounting surface) after stacking the chips in the second and subsequent layers.

<8-11. Chip size>
In the above embodiment, the chip CPi having a size (planar size) different from the final chip size SZ (the size of the finished product chip after cutting from the substrate (described below)) is arranged on the substrate WA. ing. Specifically, a chip CPi having a size (planar size) smaller than the final chip size SZ is placed.

  Conventionally, in the WOW technology in which substrates are simply bonded together, dicing is performed in a state where the lower layer substrate WA1 and the upper layer substrate WA2 are overlapped, and a part (unit) of the lower layer substrate WA1 and the upper layer substrate WA2 is overlapped. A portion UT) is cut out by dicing to form a final chip CPZ (see FIG. 74). At this time, the unit portion UT of the lower layer substrate WA1 and the unit portion UT of the upper layer substrate WA2 have the same size. That is, the size of the unit portion UT cut out from both the substrates WA1 and WA2 is the same between the upper layer and the lower layer. In other words, only a unit portion of the same size (upper layer side) can be placed on a certain unit portion of the lower layer substrate WA1. Note that the size of the chip (electronic component) that is finally cut and generated from the substrate WA in this way (the size after cutting) is also referred to as “final size” SZ.

  On the other hand, according to the embodiment, the size of the chip arranged on the substrate WA does not need to be the same as the final size SZ. That is, the size of the chip in each layer may be different from the size SZ of the unit portion (portion corresponding to each finished product chip) UT cut out from the substrate WA by dicing. The unit portion UT of the substrate WA is also expressed as a constituent unit of a final chip (finished product chip).

  More specifically, for example, as shown in FIG. 66, a chip CP1 having a size SS1 (<SZ) smaller than the final chip size (unit portion UT size) SZ is a COW process (steps S12 and S22). Thus, the substrate is placed on the substrate WT1 at a predetermined pitch p1 (here, the same pitch as the arrangement pitch p0 of the unit portions UT). Then, by executing the WOW process (steps S13 and S23) and the debonding process (S14 and S24), the plurality of chips CPi on the substrate WT1 are arranged (bonded) to the substrate WA.

  In this way, each of the plurality of chips CPi having a size SS1 different from the final chip size SZ after being cut out from the substrate WA is arranged in each unit portion UT of the substrate WA. Since the size of the chip CPi arranged in each unit portion UT is not limited to the same size as the size of the unit portion UT, chips of various sizes can be arranged. That is, the above idea has a very wide range of application.

  In particular, when mounting a chip made of a different material, for example, when mounting an optical element or an RF device on a wafer having a memory chip or an arithmetic element as a substrate, the optical element or the RF device is manufactured from a different material other than Si, and the cost From the surface, the size of the wafer is also small. Although it was impossible to implement this with the conventional WOW method, it becomes possible by adopting the above-described method (the WOW method after COW). That is, joining between different material chips is also possible.

  The present invention is not limited to this, and a plurality of chips may be arranged in a plane in each chip (unit portion UT) that is finally cut out from the substrate WA. Furthermore, the sizes of a plurality of chips arranged in a plane on each chip may be different from each other (see FIG. 67). In other words, a plurality of chips having different sizes may be arranged in a plane with respect to each chip (unit portion UT).

  For example, as shown in FIG. 67, both the first type chip CP11 and the second type chip CP12 may be arranged in each chip (each unit portion UT) after cutting. Specifically, the chip CP11 and the chip CP12 may be arranged at different plane positions on the substrate WA by shifting their plane positions so as not to overlap each other in a plane. Here, the size of the second type chip CP12 is smaller than the size of the first type chip CP11. Further, the size of the second type chip CP12 and the size of the first type chip CP11 are both smaller than the final chip size SZ.

  As described above, a plurality of types of chips of different sizes may be mixed and disposed in the same chip layer (i-th layer). According to such an aspect, it is possible to efficiently create a chip (finished product chip) composed of chips of various sizes.

  In addition, such a planar arrangement operation of a plurality of types of chips may be performed as follows.

  Specifically, the first-type chip CP11 and the second-type chip CP12 are placed on the substrate WT1 in advance by the above-described COW process (steps S12, S22) and the like. S13, S23) may be executed (see FIG. 68).

  More specifically, in step S12, the first type chips CP11 are planarly arranged at a predetermined pitch p1 on the temporary substrate WT1, and the second type chips CP12 are also planarly arranged at a predetermined pitch p1. (See FIG. 67). Further, the chip CP11 and the chip CP12 are each temporarily fixed to the substrate WT1. Thereafter, in step S13, as shown in FIG. 68, the temporary substrate WT1 and the substrate WA to be mounted are disposed to face each other. More specifically, the chip CP11 and the chip CP12 are respectively arranged to face each unit portion UT of the substrate WA. Then, as the substrate WA and the substrate WT1 approach each other, the chip CP11 and the chip CP12 are bonded to each unit portion UT of the substrate WA (see FIG. 69). In this way, a plurality of types of chips may be bonded to the substrate to be mounted at the same time.

  Alternatively, once a plurality of first-type chips in the i-th layer are arranged in a plane by a method similar to the above (steps S11 to S14 or S21 to S24, etc.), the substrate WA is predetermined by a similar method. A plurality of second-type chips in the same layer (i-th layer) may be arranged in a plane at a position (a position different from the placement position of the first-type chip) (see FIG. 70). That is, a plurality of types of chips may be bonded to a substrate to be mounted sequentially (sequentially).

  In FIG. 70, only the first-type plurality of chips CP11 of the first layer are already planarly arranged on the substrate WA by the same method (steps S11 to S14 or S21 to S24). A state (step S13) in which a plurality of second-type chips CP12 in the same layer (first layer) are being arranged in a plane by the same method (steps S11 to S14 or S21 to S24) is shown. . As described above, by repeatedly executing the above method (steps S11 to S14 or S21 to S24) for each chip type, a plurality of types of chips in the same layer (i-th layer) are planarized on the substrate WA. It may be arranged and joined.

  Further, the same applies to the second and higher chip layers. The i-th layer chip CPi having a size different from the final chip size SZ (specifically, smaller than the final chip size SZ) may be planarly arranged in the same manner. At this time, the size of each chip CPi in the i-th layer may be the same as or different from the size of each chip CP (i-1) in the (i-1) -th layer facing in step S23. .

  FIG. 71 shows a state in which the second layer chips CP21 and CP22 are being stacked on the first layer chips CP11 and CP12 using the temporary substrate WAT2 in each unit portion UT on the substrate WA. Yes. Thereafter, the second layer chip CP21 is stacked on the first layer chip CP11, and the second layer chip CP22 is stacked on the first layer chip CP12. Here, the size of the second layer chip CP21 is smaller than the size of the first layer chip CP11. As described above, the size of each chip in the i-th chip layer of the second layer or more may be different from the size of each chip in the (i-1) -th chip layer. According to this, chips of various sizes can be stacked. On the other hand, the size of the second layer chip CP22 is the same as the size of the first layer chip CP12. Thus, the size of each chip in the i-th chip layer of the second layer or higher may be the same as the size of each chip in the (i-1) -th chip layer.

<8-12. Other>
Moreover, in the said embodiment etc., although copper (Cu) is mainly illustrated as an electrode material, it is not limited to this, As other electrode materials (gold (Au), silver (Ag)) as an electrode material Etc.) may be used.

  Further, in the above-described embodiment and the like, the case where the stacking operation of the first layer chip is performed in the same manner as the stacking operation of the chip of each layer after the second layer is illustrated, but not limited thereto. A plurality of chips in the first layer may be arranged in a plane on the substrate WA using other methods.

  Moreover, in the said embodiment etc., although the case where the image for position recognition is acquired using the reflected light by an alignment mark is illustrated, it is not limited to this. For example, an illumination system may be disposed on one side with the alignment mark interposed therebetween, an imaging unit may be disposed on the other side, and a position recognition image may be acquired using transmitted light related to the alignment mark.

  In the above-described embodiment and the like, the case where two imaging units 35a and 35b are provided and two captured images Ga and Gb at two different reference positions are captured at the same time is illustrated, but the present invention is not limited thereto. Not. For example, by providing a single imaging unit 35a and sequentially moving the imaging unit 35a along the XY plane, two captured images Ga and Gb at two reference positions are sequentially captured. Also good. The single or two imaging units may be provided not on the lower side of the table 31 (lower side of the temporary substrate WTi) but on the head unit H33 side (upper side of the table 31 (upper side of the temporary substrate WTi)). good. Moreover, you may use for both. The imaging method can be recognized from the side opposite to the bonding surface of the chip or substrate if an infrared transmission method is used.

  The same applies to the two imaging units 55a and 55b. For example, by providing a single imaging unit 55a and sequentially moving the imaging unit 55a along the XY plane, two captured images Gc and Gd at two reference positions are sequentially captured. Also good. The single or two imaging units may be provided not on the lower side of the lower table 51 (lower side of the substrate WA) but on the upper side of the upper stage 53 (upper side of the temporary substrate WTi).

  Further, in the above-described embodiment and the like, in the chip supply device 10, each chip is cut out from the substrate WC having each chip CP in the face-up state, and each chip is supplied as it is to the temporary substrate WTi in the face-up state. However, the present invention is not limited to this. For example, each chip CP may be cut out and supplied from the substrate WC having each chip CP in the “face-down state”. In this case, the chip supply device 10 is provided with a reversing mechanism for reversing the top and bottom of each chip CP cut out in the face-down state, and each chip flipped up and down by the reversing mechanism is placed on the temporary substrate WTi in the face-up state. It should just be made to be supplied to.

  Further, in the above-described embodiment and the like, the temporary substrate WTi is turned upside down, and the bonding surface side of the substrate WA (for example, the plurality of chips CP (i−1) in the (i−1) th layer disposed on the substrate WA). ) And the plurality of i-th chips CPi arranged on the temporary substrate WTi are illustrated as being relatively close to each other with the substrate WA and the temporary substrate WTi. In other words, in a facing state in which the face-up substrate WA is arranged on the lower side and the face-down temporary substrate WTi is arranged on the upper side (both substrates WA and WTi), the substrate WA and the temporary substrate WTi are The case where it approaches relatively is illustrated. However, the present invention is not limited to this. For example, conversely, of the substrate WA and the temporary substrate WTi, the substrate WA is turned upside down, and the bonding surface side of the substrate WA (for example, the plurality of chips CP ((i-1) layer disposed on the substrate WA) ( The substrate WA and the temporary substrate WTi may be relatively close to each other in a state where the i-1)) and the plurality of i-th layer chips CPi disposed on the temporary substrate WTi face each other. In other words, in a facing state in which the face-down substrate WA is disposed on the upper side and the face-up temporary substrate WTi is disposed on the lower side (both substrates WA and WTi), the substrate WA and the temporary substrate WTi are You may make it approach relatively.

  Moreover, in the said embodiment etc., although the case where both marks MC1 and MC2 have a mark of a mutually different shape is illustrated, it is not limited to this. For example, both marks MC1 and MC2 may have the same shape. However, in this case, in order to avoid that both MC1 and MC2 completely overlap each other during alignment, it is preferable that both marks MC1 and MC2 are arranged at different reference positions (horizontal reference positions). . More specifically, the mark MC2 may be disposed at a reference position that is offset by a predetermined amount from the reference position of the mark MC1. A positional relationship based on a predetermined offset amount between the reference position of the mark MC1 and the reference position of the mark MC2 (predetermined positional relationship) (specifically, positions between the marks MC1a, MC1b, MC2a, MC2b) By using (Relationship), it is possible to perform precise alignment using the marks MC1 and MC2. Moreover, when imaging a chip | tip and a board | substrate with a separate imaging part, the same mark may be arrange | positioned and accumulated in the same position. According to the imaging unit having the infrared transmission function, it is also possible to recognize from the side opposite to the bonding surface of the chip or the substrate.

  The same applies to the marks MW1 and MW2. For example, both marks MW1, MW2 may have the same shape. However, in this case, in order to avoid that both MW1 and MW2 completely overlap each other during alignment, it is preferable that both marks MW1 and MW2 are arranged at different reference positions (horizontal reference positions). . More specifically, the mark MW2 may be arranged at a reference position that is offset by a predetermined amount from the reference position of the mark MW1. Positional relationship based on a predetermined offset amount between the reference position of the mark MW1 and the reference position of the mark MW2 (predetermined positional relationship) (specifically, positions between the marks MW1a, MW1b, MW2a, MW2b) By using the relationship, it is possible to perform precise alignment using the marks MW1 and MW2. In addition, when the upper substrate and the lower substrate are respectively imaged by individual imaging units, the same mark may be arranged at the same position. According to the imaging unit having the infrared transmission function, it is also possible to recognize from the side opposite to the bonding surface of the chip or the substrate.

  Further, the number of each substrate mark may be one. If there are two or more marks that can define the rotation direction on the entire wafer (substrate), the θ direction can be calculated, and therefore one mark may be used at each substrate position.

  In the above-described embodiment and the like, alignment is performed only after heating after the substrate WA and the plurality of chips CP1 in the first layer face each other in the WOW bonding step (see FIGS. 17 and 18) in step S13 (FIG. 2). Although the mode in which the operation is performed is illustrated, it is not limited to this.

  For example, after both the substrate WA and the plurality of chips CP1 in the first layer are opposed to each other, an alignment operation may be further performed before the two are in contact with each other to be bonded. Specifically, first, in the same manner as described above, the alignment operation before heating is performed with the substrate WA and the plurality of chips CP1 in the first layer facing each other. However, at this time, the substrate WA and the plurality of chips CP1 in the first layer are not yet in contact with each other. Next, the substrate WA and the plurality of chips CP1 in the first layer are heated, and the solder bumps BU of the chips CP1 are melted. Then, in the molten state of the solder bump BU, an alignment operation in the horizontal direction (X direction, Y direction, θ direction) is executed. By this alignment operation, each of the plurality of chips CP1 is positioned in a direction parallel to the substrate plane of the substrate WT1. When the positional deviation in the horizontal direction between the substrate WA and the plurality of chips CP1 in the first layer falls within an allowable range, the substrate WA and the plurality of chips CP1 in the first layer come close to each other and come into contact with each other. Is done. Thus, alignment may be performed again during heating and before contact. According to this, it is possible to correct misalignment due to thermal expansion.

  Further, the alignment operation may be performed in a state where the substrate WA and the plurality of chips CP1 in the first layer are heated and in contact with each other. Specifically, the alignment operation before heating and the alignment operation during heating and before contact are performed as described above. At this time, the substrate WA and the plurality of chips CP1 in the first layer are heated, and the solder bumps BU of the chips CP1 are melted. In the molten state of the solder bumps BU, the substrate WA and the plurality of chips CP1 in the first layer come close to each other and come into contact with each other. Further, the alignment operation in the horizontal direction (X direction, Y direction, θ direction) is executed while the contact state between the two and the bump melting state are continued. By this alignment operation, each of the plurality of chips CP1 is positioned in a direction parallel to the substrate plane of the substrate WT1. Then, after the positional shift between the substrate WA and the plurality of chips CP1 in the first layer falls within an allowable range by this alignment operation, the substrate WA and the plurality of chips CP1 in the first layer are cooled and joined. In this way, alignment may be performed during heating and melting of solder bumps and during contact. According to this, it is possible to correct misalignment due to thermal expansion and new misalignment caused by physical contact between the substrate WA and the plurality of chips CP1 of the first layer. Alignment can be performed.

  The same applies to the WOW bonding step (see FIGS. 23 and 24) in step S23 (FIG. 3). Specifically, after both of the chip CP (i-1) in the (i-1) layer and the plurality of chips CP1 in the i layer face each other, the alignment operation is further performed before the contact between the two and during heating. It may be performed so that the both are joined. In addition, the alignment operation is performed in a state where the chip CP (i-1) in the (i-1) -th layer and the plurality of chips CPi in the i-th layer are heated and in contact with each other (the chip CPi is in a molten state and in a contact state). You may do it.

DESCRIPTION OF SYMBOLS 1 Chip mounting system 10 Chip supply apparatus 30 Bonding apparatus 31 Stage 33 Bonding part 33H Head part 35,35a, 35b, 55,55a, 55b Imaging part 36,56 Position recognition part 39 Chip conveyance part 50 Bonding apparatus 51 Lower stage 53 On Stage 70 Transfer part 71 Transfer robot 90 Carry-in / out part CPi Chip MC1, MC2 Chip position adjustment mark (part position adjustment mark)
MW1, MW2 Substrate position adjustment mark PL Planar member RSi resin layer RU Underfill resin WA substrate WTi Temporary substrate

In order to solve the above-mentioned problem, a first aspect of the present invention is an electronic component mounting method, and a) an i-th resin on an i-th substrate (where i is an integer of 1 or more) which is a temporary substrate. A step of forming a layer; b) a step of placing a plurality of electronic components of the i-th layer on the i-th resin layer in a face-up state with their joint surfaces facing upward; The predetermined substrate and the i-th substrate are relatively brought close to each other in a state where the substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other. A step of relatively bringing a plurality of electronic components of the i-th layer into close proximity to each other and joining the predetermined substrate and the plurality of electronic components of the i-th layer; and d) a plurality of the i-th layer While maintaining the electronic component bonded to the predetermined substrate, the i-th layer Comprising a step of separating the substrate of the i-th several electronic components, wherein the step b) is temporarily placed in a face-up state in b-1) uniform thickness resin layer of the i-th formed of And aligning the heights of the upper end positions of the plurality of electronic components in the i-th layer, and the step b-1) is temporarily performed on the i-th resin layer in the b-1-1) face-up state. Aligning the heights of the upper end positions of the plurality of electronic components of the i-th layer having variations in thickness by pressing a planar member against the upper end sides of the placed electronic components of the i-th layer; It is characterized by having.
The second aspect of the present invention is an electronic component mounting method, comprising: a) forming an i-th resin layer on an i-th substrate (where i is an integer of 1 or more), which is a temporary substrate; b) a step of placing a plurality of electronic components of the i-th layer on the i-th resin layer in a face-up state with their joint surfaces facing upward, and temporarily fixing them; c) a predetermined substrate and the i-th layer By moving the predetermined substrate and the i-th substrate relatively close to each other with the plurality of electronic components of the i-th layer arranged on the substrate facing each other, the predetermined substrate and the i-th layer A step of relatively bringing the plurality of electronic components close to each other and joining the predetermined substrate and the plurality of electronic components of the i-th layer; and d) the plurality of electronic components of the i-th layer being the predetermined substrate The plurality of electronic components of the i-th layer are The step b) includes a step b-1) a plurality of the i-th layers temporarily placed face-up on the i-th resin layer formed to have a uniform thickness. Aligning the height of the upper end position of the electronic component, and the step b-1) includes: b-1-2) each electronic component constituting the plurality of electronic components of the i-th layer is an electronic component holding member. Each electronic component in a state where the upper end position of each electronic component is present at a predetermined position in the vertical direction by adjusting the position of the electronic component holding member in the vertical direction. Is temporarily fixed to the i-th resin layer, thereby aligning the heights of the upper end positions of the plurality of electronic components of the i-th layer having variations in thickness.
According to a third aspect of the present invention, there is provided an electronic component mounting method comprising: a) forming an i-th resin layer on an i-th substrate (where i is an integer of 1 or more), which is a temporary substrate; b) a step of placing a plurality of electronic components of the i-th layer on the i-th resin layer in a face-up state with their joint surfaces facing upward, and temporarily fixing them; c) a predetermined substrate and the i-th layer By moving the predetermined substrate and the i-th substrate relatively close to each other with the plurality of electronic components of the i-th layer arranged on the substrate facing each other, the predetermined substrate and the i-th layer A step of relatively bringing the plurality of electronic components close to each other and joining the predetermined substrate and the plurality of electronic components of the i-th layer; and d) the plurality of electronic components of the i-th layer being the predetermined substrate The plurality of electronic components of the i-th layer are Separating the substrate, wherein the step c) is an electrode material provided on a bonding surface when the plurality of electronic components of the i-th layer are bonded to the predetermined substrate. A step of collectively performing a surface activation process on the electrode materials of the plurality of electronic components of the i-th layer temporarily fixed on the substrate, and the temporary fixing to the predetermined substrate and the i-th substrate With the predetermined substrate and the i-th substrate relatively approaching each other with the plurality of electronic components in the i-th layer facing each other, the predetermined substrate and the plurality of electronic components in the i-th layer And relatively bonding the predetermined substrate and the plurality of electronic components of the i-th layer, respectively.
According to a fourth aspect of the present invention, there is provided an electronic component mounting method comprising: a) forming an i-th resin layer on an i-th substrate (where i is an integer of 1 or more), which is a temporary substrate; b) a step of placing a plurality of electronic components of the i-th layer on the i-th resin layer in a face-up state with their joint surfaces facing upward, and temporarily fixing them; c) a predetermined substrate and the i-th layer By moving the predetermined substrate and the i-th substrate relatively close to each other with the plurality of electronic components of the i-th layer arranged on the substrate facing each other, the predetermined substrate and the i-th layer A step of relatively bringing the plurality of electronic components close to each other and joining the predetermined substrate and the plurality of electronic components of the i-th layer; and d) the plurality of electronic components of the i-th layer being the predetermined substrate The plurality of electronic components of the i-th layer are The step b) until b-2) covers the upper side surfaces of the plurality of electronic components of the i-th layer arranged in a plane on the i-th resin layer. After the resin is supplied and cured, the resin portion of the upper surface of the plurality of electronic components of the i-th layer is provided protruding from the upper surface of the plurality of electronic components of the i-th layer. A step of performing a flattening polishing process on a resin portion in which the electrode portions are scattered in a plane, and in the step c), the electrodes provided on the plurality of electronic components of the i-th layer The portion and the corresponding portion of the plurality of electronic components of the (i-1) th layer or the corresponding portion of the predetermined substrate are joined.
According to a fifth aspect of the present invention, there is provided an electronic component mounting method comprising: a) forming an i-th resin layer on an i-th substrate (where i is an integer of 1 or more), which is a temporary substrate; b) a step of placing a plurality of electronic components of the i-th layer on the i-th resin layer in a face-up state with their joint surfaces facing upward, and temporarily fixing them; c) a predetermined substrate and the i-th layer By moving the predetermined substrate and the i-th substrate relatively close to each other with the plurality of electronic components of the i-th layer arranged on the substrate facing each other, the predetermined substrate and the i-th layer A step of relatively bringing the plurality of electronic components close to each other and joining the predetermined substrate and the plurality of electronic components of the i-th layer; and d) the plurality of electronic components of the i-th layer being the predetermined substrate The plurality of electronic components of the i-th layer are Separating each of the substrates, wherein each of the plurality of electronic components of the i-th layer is a unit portion cut out from the predetermined substrate by dicing, and the size of the plurality of electronic components of the i-th layer It is characterized in that it is different from the cut-out size for the unit portion where each is arranged.

  According to a sixth aspect of the present invention, there is provided an electronic component mounting system in which an i-th resin layer formed on an i-th substrate (where i is an integer of 1 or more) is a temporary substrate. A plurality of electronic components of i layer are placed in a face-up state with their joint surfaces facing upward, and a plurality of electronic components of i layer are arranged in a plane on the i th resin layer and temporarily fixed. The predetermined substrate and the i-th substrate are relatively brought close to each other with the bonding means, the predetermined substrate, and the plurality of electronic components of the i-th layer disposed on the i-th substrate facing each other. A second bonding means for relatively bringing the predetermined substrate and the plurality of electronic components of the i-th layer close together, and bonding the predetermined substrate and the plurality of electronic components of the i-th layer; A state in which the plurality of electronic components of the i-th layer are bonded to the predetermined substrate is maintained. And separating means for separating the i-th substrate from the plurality of electronic components of the i-th layer, wherein the first bonding means is formed on the i-th resin layer formed to have a uniform thickness. Leveling processing means for aligning the heights of the upper end positions of the plurality of electronic components of the i-th layer temporarily placed in a face-up state, and the leveling processing means is face-up on the i-th resin layer. By pressing a planar member against the upper end side of the temporarily placed electronic components of the i-th layer, the heights of the upper end positions of the electronic components of the i-th layer having variations in thickness are made uniform. It is characterized by.
  A seventh aspect of the present invention is an electronic component mounting system, in which an i-th resin layer formed on an i-th substrate (where i is an integer equal to or greater than 1) is a temporary substrate. A plurality of electronic components placed in a face-up state with their joint surfaces facing upward, and a plurality of electronic components of the i-th layer are arranged in a plane on the i-th resin layer and temporarily fixed. And moving the predetermined substrate and the i-th substrate relatively close to each other while the predetermined substrate and the plurality of electronic components of the i-th layer arranged on the i-th substrate are opposed to each other. A second bonding means for bringing the predetermined substrate and the plurality of electronic components of the i-th layer relatively close to each other and bonding the predetermined substrate and the plurality of electronic components of the i-th layer; A plurality of i-layer electronic components are maintained bonded to the predetermined substrate. Separating means for separating the i-th substrate from the plurality of electronic components of the i-th layer, wherein the first bonding means faces up to the i-th resin layer having a uniform thickness. Leveling processing means for aligning the heights of the upper end positions of the plurality of electronic components of the i-th layer temporarily placed in a state, the leveling processing means comprising each of the plurality of electronic components of the i-th layer By holding the electronic component in a face-up state using the electronic component holding member and adjusting the position of the electronic component holding member in the vertical direction, the upper end position of each electronic component exists at a predetermined position in the vertical direction. In this state, by temporarily fixing each electronic component to the i-th resin layer, the heights of the upper end positions of the plurality of electronic components of the i-th layer having variations in thickness are made uniform.
  An eighth aspect of the present invention is an electronic component mounting system, in which an i-th resin layer formed on an i-th substrate (where i is an integer equal to or greater than 1) is a temporary substrate. A plurality of electronic components placed in a face-up state with their joint surfaces facing upward, and a plurality of electronic components of the i-th layer are arranged in a plane on the i-th resin layer and temporarily fixed. And moving the predetermined substrate and the i-th substrate relatively close to each other while the predetermined substrate and the plurality of electronic components of the i-th layer arranged on the i-th substrate are opposed to each other. A second bonding means for bringing the predetermined substrate and the plurality of electronic components of the i-th layer relatively close to each other and bonding the predetermined substrate and the plurality of electronic components of the i-th layer; A plurality of i-layer electronic components are maintained bonded to the predetermined substrate. Separation means for separating the i-th substrate from the plurality of electronic components of the i-th layer, and the joining of the plurality of electronic components of the i-th layer to the predetermined substrate on the i-th resin layer Surface activation treatment means for collectively performing surface activation treatment on electrode materials provided on the joint surfaces of the plurality of electronic components of the i-th layer temporarily fixed, and the second bonding means includes: A plurality of electronic components of the i-th layer whose surface is subjected to the surface activation treatment, and the plurality of electronic components of the i-th layer temporarily fixed to the i-th substrate are the predetermined substrate. It joins with respect to.
  A ninth aspect of the present invention is an electronic component mounting system, in which an i-th resin layer formed on an i-th substrate (where i is an integer equal to or greater than 1) is a temporary substrate. A plurality of electronic components placed in a face-up state with their joint surfaces facing upward, and a plurality of electronic components of the i-th layer are arranged in a plane on the i-th resin layer and temporarily fixed. And moving the predetermined substrate and the i-th substrate relatively close to each other while the predetermined substrate and the plurality of electronic components of the i-th layer arranged on the i-th substrate are opposed to each other. A second bonding means for bringing the predetermined substrate and the plurality of electronic components of the i-th layer relatively close to each other and bonding the predetermined substrate and the plurality of electronic components of the i-th layer; A plurality of i-layer electronic components are maintained bonded to the predetermined substrate. Separating means for separating the i-th substrate from the plurality of electronic components of the i-th layer, and upper side surfaces of the plurality of electronic components of the i-th layer arranged in a plane on the i-th resin layer. A resin supply means for supplying a resin until it is covered; and a resin portion of the upper surface of the plurality of electronic components of the i-th layer after the resin is cured, and the upper side of the plurality of electronic components of the i-th layer Polishing means for performing a planarization polishing process on a resin portion in which electrode portions protruding from the surface are scattered in a plane, and the second bonding means includes a plurality of the i-th layer. The electrode portion provided on the electronic component and the corresponding portion of the plurality of electronic components of the (i-1) -th layer or the corresponding portion of the predetermined substrate are joined.
  A tenth aspect of the present invention is an electronic component mounting system, in which an i-th resin layer formed on an i-th substrate (where i is an integer equal to or greater than 1) is a temporary substrate. A plurality of electronic components placed in a face-up state with their joint surfaces facing upward, and a plurality of electronic components of the i-th layer are arranged in a plane on the i-th resin layer and temporarily fixed. And moving the predetermined substrate and the i-th substrate relatively close to each other while the predetermined substrate and the plurality of electronic components of the i-th layer arranged on the i-th substrate are opposed to each other. A second bonding means for bringing the predetermined substrate and the plurality of electronic components of the i-th layer relatively close to each other and bonding the predetermined substrate and the plurality of electronic components of the i-th layer; A plurality of electronic components of i layer are maintained in a state of being bonded to the predetermined substrate. Separating means for separating the i-th substrate from the plurality of electronic components of the i-th layer, and each size of the plurality of electronic components of the i-th layer is cut out from the predetermined substrate by dicing. The cut-out size of the unit portion in which each of the plurality of electronic components of the i-th layer is arranged is different.

Claims (50)

An electronic component mounting method,
a) forming an i-th resin layer on an i-th substrate which is a temporary substrate (where i is an integer of 1 or more);
b) a step of temporarily fixing a plurality of electronic components of the i-th layer in a plane arrangement on the i-th resin layer in a face-up state with their joint surfaces facing upward;
c) By bringing the predetermined substrate and the i-th substrate relatively close to each other while the predetermined substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other. A step of relatively approaching the predetermined substrate and the plurality of electronic components of the i-th layer, and joining the predetermined substrate and the plurality of electronic components of the i-th layer;
d) separating the i-th substrate from the plurality of electronic components in the i-th layer while maintaining the state where the plurality of electronic components in the i-th layer are bonded to the predetermined substrate;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
e) The value i is incremented and the step a), the step b), the step c), and the step d) are repeatedly executed, and electronic components are formed in a plurality of layers at a plurality of planar positions on the predetermined substrate. Laminating step,
An electronic component mounting method characterized by further comprising: The electronic component mounting method according to claim 1,
Said step c) is when the value i = 1,
By relatively approaching the predetermined substrate and the first substrate in a state where the predetermined substrate and the plurality of electronic components of the first layer disposed on the first substrate are opposed to each other, The predetermined substrate and the plurality of electronic components of the first layer are relatively approached, the plurality of electronic components of the first layer are respectively placed at predetermined positions on the predetermined substrate, and the predetermined substrate Bonding the substrate and the plurality of electronic components of the first layer;
Have
Said step d) is when the value i = 1,
Separating the first substrate from the plurality of electronic components of the first layer while maintaining a state in which the plurality of electronic components of the first layer are bonded to the predetermined substrate;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
The value i is an integer greater than or equal to 2,
Said step c)
The predetermined substrate in a state where the plurality of electronic components of the (i-1) -th layer disposed on the predetermined substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other. And the i-th substrate relatively close to each other, the plurality of electronic components of the (i-1) -th layer and the plurality of electronic components of the i-th layer are relatively brought close to each other. i-1) bonding a plurality of electronic components of the layer and a plurality of electronic components of the i-th layer,
Have
Said step d)
While maintaining the state in which the plurality of electronic components of the i-th layer are respectively joined to the plurality of electronic components of the (i-1) -th layer, the i-th substrate is transferred from the plurality of electronic components of the i-th layer. Separating step,
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step b)
b-1) aligning the heights of the upper end positions of the plurality of electronic components of the i-th layer temporarily placed on the i-th resin layer in a face-up state;
An electronic component mounting method comprising: The electronic component mounting method according to claim 5,
Step b-1)
b-1-1) A plurality of electrons in the i-th layer by pressing a planar member against upper end sides of the plurality of electronic components in the i-th layer temporarily placed on the i-th resin layer in a face-up state. Aligning the height of the top edge of the part,
An electronic component mounting method comprising: The electronic component mounting method according to claim 5,
Step b-1)
b-1-2) Holding each electronic component constituting the plurality of electronic components of the i-th layer in a face-up state using an electronic component holding member, and adjusting the position of the electronic component holding member in the vertical direction. By temporarily fixing each electronic component to the i-th resin layer in a state where the upper end position of each electronic component exists at a predetermined position in the vertical direction, the plurality of electronic components of the i-th layer The step of aligning the height of the top position,
An electronic component mounting method comprising: The electronic component mounting method according to claim 7,
The i-th resin layer is formed of a photocurable resin,
In each of the steps b-1-2), each time the electronic components constituting the plurality of electronic components of the i-th layer are arranged with their upper end positions aligned with the predetermined positions in the vertical direction, The i-th resin layer is cured by irradiating light on the placement area of each electronic component in the i-th resin layer, and each electronic component is temporarily fixed to the i-th resin layer. Electronic component mounting method. The electronic component mounting method according to claim 7,
In step b-1-2), the head portion of the electronic component holding member is heated to a predetermined temperature, the upper end position of each electronic component is disposed at the predetermined position in the vertical direction, and each electronic component is An electronic component mounting method characterized by being temporarily fixed to an i-th resin layer. The electronic component mounting method according to claim 1,
Said step d)
d-1) separating the i-th substrate from the plurality of electronic components of the i-th layer by performing a laser ablation process on the i-th resin layer formed of a photocurable resin;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step d)
d-2) separating the i-th substrate from the plurality of electronic components of the i-th layer by heating the i-th resin layer formed of a thermoplastic resin;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step d)
d-3) By heating the i-th resin layer after irradiating the i-th resin layer formed of a thermoplastic resin with ultraviolet rays, the i-th substrate is removed from the plurality of electronic components of the i-th layer. Separating the steps,
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step a)
a-1) applying a resin on the i-th substrate by a spin coater;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step a)
a-2) attaching a resin sheet on the i-th substrate;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Each of the plurality of electronic components in the i-th layer has a first type component position adjustment mark,
The i-th substrate has a second type component position adjustment mark corresponding to each of the plurality of electronic components of the i-th layer,
In step b)
The first type component position adjustment mark in each of the plurality of electronic components in the i-th layer and the first substrate provided on the i-th substrate corresponding to each of the plurality of electronic components in the i-th layer. Each of the plurality of electronic components in the i-th layer is positioned in a direction parallel to the plane of the i-th substrate using two types of component position adjustment marks, and each of the plurality of electronic components in the i-th layer Is mounted on the i-th resin layer on the i-th substrate. The electronic component mounting method according to claim 15,
The electronic component mounting method, wherein the second type component position adjustment mark is provided as a mark having a different shape from the first type component position adjustment mark. The electronic component mounting method according to claim 15,
The electronic component mounting method, wherein the second type component position adjustment mark is provided at a position offset by a predetermined amount from a reference position of the first type component position adjustment mark. The electronic component mounting method according to claim 15,
e) The value i is incremented and the step a), the step b), the step c), and the step d) are repeatedly executed, and electronic components are formed in a plurality of layers at a plurality of planar positions on the predetermined substrate. Laminating step,
Further comprising
The electronic component mounting method, wherein each of the plurality of electronic components of the i-th layer has the first type component position adjustment mark at the same position in the electronic component. The electronic component mounting method according to claim 15,
The i-th substrate is a glass substrate;
The first type component position adjustment mark is provided on a surface on the i-th substrate side in each of the plurality of electronic components of the i-th layer,
In step b)
The first type component position adjustment mark in each of the plurality of electronic components in the i-th layer and the first substrate provided on the i-th substrate corresponding to each of the plurality of electronic components in the i-th layer. Each of the plurality of electronic components of the i-th layer is positioned in a direction parallel to the i-th substrate plane using images obtained by imaging two types of component position adjustment marks with visible light, and the i-th substrate Each of a plurality of electronic components of a layer is placed on the i-th resin layer on the i-th substrate. The electronic component mounting method according to claim 15,
In step b)
The first type component position adjustment mark in each of the plurality of electronic components in the i-th layer and the first substrate provided on the i-th substrate corresponding to each of the plurality of electronic components in the i-th layer. Each of the plurality of electronic components of the i-th layer is positioned in a direction parallel to the i-th substrate plane using images obtained by imaging two types of component position adjustment marks with infrared light, and An electronic component mounting method, wherein each of the plurality of i-layer electronic components is placed on the i-th resin layer on the i-th substrate. The electronic component mounting method according to claim 15,
The predetermined substrate has a first type substrate position adjustment mark,
The i-th substrate has a second type substrate position adjustment mark,
In the step c), the predetermined substrate and the second type substrate position adjusting mark on the predetermined substrate and the second type substrate position adjusting mark on the i th substrate are used. The i-th substrate is positioned in a direction parallel to the i-th substrate plane, so that each of the plurality of electronic components held on the predetermined substrate and the i-th substrate is held on the i-th substrate. An electronic component mounting method, wherein a positional relationship with each of a plurality of electronic components of the i-th layer is adjusted. The electronic component mounting method according to claim 21,
The electronic component mounting method, wherein the second type substrate position adjustment mark is provided as a mark having a different shape from the first type substrate position adjustment mark. The electronic component mounting method according to claim 21,
The electronic component mounting method, wherein the second type substrate position adjustment mark is provided at a position offset by a predetermined amount from a reference position of the first type substrate position adjustment mark. The electronic component mounting method according to claim 1,
In the step c), a plurality of electrons of the i-th layer arranged on the predetermined substrate and the i-th substrate are turned upside down on either the predetermined substrate or the i-th substrate. An electronic component mounting method, wherein the predetermined substrate and the i-th substrate are relatively approached in a state where the component faces each other. The electronic component mounting method according to claim 1,
In step c), the plurality of electronic components of the i-th layer are bonded to the predetermined substrate together with a solder bonding process, and the solder bonding process is performed with a predetermined temperature profile. Electronic component mounting method. The electronic component mounting method according to claim 1,
In the step c), the plurality of electronic components of the i-th layer are bonded to the predetermined substrate together with a solder bonding process, and the solder bonding processing is accommodated by the plurality of electronic components of the i-th layer. An electronic component mounting method, wherein the electronic component mounting method is performed with a decompression process over a predetermined period in a processing space. The electronic component mounting method according to claim 1,
Said step c)
The predetermined substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other and the plurality of electronic components of the i-th layer are heated. Performing an alignment operation with the i-th substrate to position each of the plurality of electronic components of the i-th layer in a direction parallel to the i-th substrate plane;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step c)
The predetermined substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other, and the plurality of electronic components of the i-th layer are heated to melt the solder bumps for bonding, and The alignment operation between the predetermined substrate and the i-th substrate is performed in a state where the predetermined substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are in contact with each other. Positioning each of the plurality of electronic components of the i-th layer in a direction parallel to the i-th substrate plane;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
The value i is an integer greater than or equal to 2,
Said step c)
The plurality of electronic components of the (i-1) th layer arranged on the predetermined substrate and the plurality of electronic components of the i-th layer arranged on the i-th substrate are opposed to each other and the plurality of the i-th layer is arranged. The electronic component is heated to melt the solder bump for bonding, and the predetermined number of the electronic components in the (i-1) layer and the plurality of electronic components in the i-th layer are in contact with each other. Positioning the plurality of electronic components of the i-th layer in a direction parallel to the i-th substrate plane by performing an alignment operation between the substrate and the i-th substrate;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step c)
Performing a surface activation process on an electrode material provided on a bonding surface at the time of bonding the plurality of electronic components of the i-th layer to the predetermined substrate;
By relatively approaching the predetermined substrate and the i-th substrate in a state where the predetermined substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other, Relatively approaching the predetermined substrate and the plurality of electronic components of the i-th layer, and bonding the predetermined substrate and the plurality of electronic components of the i-th layer, respectively,
An electronic component mounting method comprising: The electronic component mounting method according to claim 30, wherein
The electronic component mounting method, wherein the surface activation process includes a process of activating a bonding surface by irradiating an energy wave. The electronic component mounting method according to claim 31,
The method of mounting an electronic component, wherein the energy wave is irradiated by accelerating a specific substance with an electric field. In the electronic component mounting method according to claim 32,
The electronic component mounting method, wherein the specific substance includes an inert gas substance. The electronic component mounting method according to claim 30, wherein
The electronic component mounting method, wherein the surface activation process includes a process of activating a bonding surface with a hydrophilic process. The electronic component mounting method according to claim 34,
The electronic component mounting method, wherein the surface activation process is performed with a plasma process. In the electronic component mounting method according to claim 35,
The electronic component mounting method, wherein the plasma treatment includes at least one of oxygen plasma treatment and nitrogen plasma treatment. The electronic component mounting method according to claim 1,
f) Each of the plurality of electronic components of the i-th layer in a state of being disposed on the predetermined substrate after the plurality of electronic components of the i-th layer are planarly disposed on the predetermined substrate. Performing a first bonding state inspection;
Further comprising
After step d), the value i is incremented and the steps a) to d) are executed again,
In step b), which is executed again after incrementing the value i, a plurality of the i-th layers are excluded, excluding positions corresponding to electronic components determined to be defective in the first bonding state inspection. The electronic component mounting method is characterized in that the electronic component is planarly arranged on the i-th resin layer. The electronic component mounting method according to claim 37,
After step d), the value i is incremented and the steps a) to d) and f) are executed again,
In step f), which is executed again after incrementing the value i, a second bonding state inspection is performed on each of the plurality of electronic components in the i-th layer in a state of being arranged on the predetermined substrate. ,
After the step d), which is executed again after the increment of the value i, the value i is re-incremented and the steps a) to d) are executed again,
In step b), which is executed again after re-incrementing the value i, the position corresponding to the electronic component determined to be defective in the second bonding state inspection is also excluded, and the i-th layer A plurality of electronic components are arranged in a plane on the i-th resin layer. The electronic component mounting method according to claim 1,
f) The plurality of electronic components of the i-th layer and the plurality of non-defective electronic components that have been determined to be non-defective are arranged on the predetermined substrate and then disposed on the predetermined substrate. Performing a first bonding state inspection on each of the plurality of electronic components of the i-th layer;
Further comprising
After step d), the value i is incremented and the steps a) to d) are executed again,
In step b), which is executed again after incrementing the value i, a plurality of the i-th layers are excluded, excluding positions corresponding to electronic components determined to be defective in the first bonding state inspection. A plurality of electronic components that have been determined as non-defective products are arranged in a plane on the i-th resin layer. The electronic component mounting method according to claim 39,
After step d), the value i is incremented and the steps a) to d) and f) are executed again,
In step f), which is executed again after incrementing the value i, a second bonding state inspection is performed on each of the plurality of electronic components in the i-th layer in a state of being arranged on the predetermined substrate. ,
After the step d), which is executed again after the increment of the value i, the value i is re-incremented and the steps a) to d) are executed again,
In step b), which is executed again after re-incrementing the value i, the position corresponding to the electronic component determined to be defective in the second bonding state inspection is also excluded, and the i-th layer A plurality of electronic components are arranged in a plane on the i-th resin layer. The electronic component mounting method according to claim 1,
Said step b)
b-2) Resin is supplied until it covers the upper surface of the plurality of electronic components of the i-th layer arranged in a plane on the i-th resin layer, and after the resin is cured, the plurality of i-th layers The resin part on the upper side surface of the electronic part of the electronic component is flattened with respect to the resin part in which the electrode parts protruding from the upper surface of the electronic parts of the i-th layer are scattered in a plane Applying a polishing process;
Have
In step c), the electrode portions provided on the plurality of electronic components of the i-th layer and the corresponding portions of the plurality of electronic components of the (i-1) -th layer or the corresponding portions of the predetermined substrate are An electronic component mounting method characterized by being bonded. The electronic component mounting method according to claim 41,
Step b-2)
b-2-1) planarly arranging a plurality of electronic components of the i-th layer provided with electrode portions protruding on the upper surface thereof on the i-th resin layer;
b-2-2) supplying resin until the upper surface of the plurality of electronic components of the i-th layer arranged in a plane on the i-th resin layer is covered;
b-2-3) performing a planarization polishing process on the resin portion of the upper surface of the plurality of electronic components of the i-th layer after the resin is cured;
An electronic component mounting method comprising: The electronic component mounting method according to claim 41,
Step b-2)
b-2-1) planarly arranging the plurality of electronic components of the i-th layer on the i-th resin layer;
b-2-2) supplying resin until the upper surface of the plurality of electronic components of the i-th layer arranged in a plane on the i-th resin layer is covered;
b-2-3) In the resin portion of the upper surface of the plurality of electronic components of the i-th layer, providing a hole for forming an electrode at a predetermined position in a plane;
b-2-4) supplying an electrode material to the hole and forming an electrode portion on the upper surface of the plurality of electronic components of the i-th layer;
b-2-5) performing a planarization polishing process on the resin portion on the upper surface of the plurality of electronic components of the i-th layer;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Said step d)
After the i-th substrate is separated from the plurality of electronic components of the i-th layer, performing a planarization polishing process on the exposed surfaces of the plurality of electronic components of the i-th layer;
An electronic component mounting method comprising: The electronic component mounting method according to claim 1,
Each size of the plurality of electronic components of the i-th layer is a unit portion that is cut out from the predetermined substrate by dicing, and after the cut-out with respect to the unit portion in which each of the plurality of electronic components of the i-th layer is arranged Electronic component mounting method characterized by being different from size. The electronic component mounting method according to claim 4,
The electronic component mounting method, wherein the size of the plurality of electronic components of the i-th layer is different from the size of the plurality of electronic components of the (i-1) -th layer facing each other in the step c). An electronic component mounting system,
A face-up state in which a plurality of electronic components of the i-th layer are placed with their joint surfaces facing upward on the i-th resin layer formed on the i-th substrate (where i is an integer of 1 or more) which is a temporary substrate A first bonding means for placing and temporarily fixing a plurality of electronic components of the i-th layer in a planar arrangement on the i-th resin layer;
By bringing the predetermined substrate and the i-th substrate relatively close to each other while the predetermined substrate and the plurality of electronic components of the i-th layer disposed on the i-th substrate are opposed to each other, A second bonding means for relatively bringing a predetermined substrate and the plurality of electronic components of the i-th layer close to each other, and bonding the predetermined substrate and the plurality of electronic components of the i-th layer;
Separating means for separating the i-th substrate from the plurality of electronic components in the i-th layer while maintaining a state in which the plurality of electronic components in the i-th layer are bonded to the predetermined substrate;
An electronic component mounting system comprising: The electronic component mounting system according to claim 47,
Each of the plurality of electronic components in the i-th layer has a first type component position adjustment mark,
The i-th substrate has a second type component position adjustment mark corresponding to each of the plurality of electronic components of the i-th layer,
The first bonding means includes
The first type component position adjustment mark in each electronic component constituting the plurality of electronic components of the i-th layer and the second type provided on the i-th substrate corresponding to each electronic component First position recognition means for recognizing the position of each electronic component in a direction parallel to the i-th substrate plane using the component position adjustment mark of
Each of the electronic components on the i-th substrate is driven by relatively driving the i-th substrate and each of the electronic components based on the position of each of the electronic components recognized by the first position recognition means. First driving means for adjusting the position of
An electronic component mounting system comprising: The electronic component mounting system according to claim 48,
The predetermined substrate has a first type substrate position adjustment mark,
The i-th substrate has a second type substrate position adjustment mark having a shape different from that of the first type substrate position adjustment mark,
The second bonding means includes
Using the first type substrate position adjustment mark on the predetermined substrate and the second type substrate position adjustment mark on the i-th substrate in a direction parallel to the i-th substrate plane Second position recognition means for obtaining a relative positional relationship between the predetermined substrate and the i-th substrate;
Based on the relative positional relationship obtained by the second position recognition means, the predetermined substrate and the i-th substrate are relatively driven, and the positional relationship between the predetermined substrate and the i-th substrate is determined. A second driving means for adjusting;
An electronic component mounting system comprising: A substrate used as the i-th substrate in the electronic component mounting method according to claim 21,
The second type component position adjustment mark;
The second type substrate position adjustment mark;
A substrate characterized by comprising:

Images