JP2012238775A - Alignment device and alignment method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an alignment technique capable of positioning two objects at higher speed with higher accuracy.SOLUTION: A bonding device 30 includes a head 33H for holding a chip CP and a substrate holding unit for holding a substrate WT and measurement means (imaging units 35a, 35b, etc.) for measuring a relative position error between both objects CP and WT. In a state that the chip CP is disposed at a predetermined bonding position (X, Y) in a plane, on which both objects CP and WT are disposed to face each other and which is parallel to the mounting plane of the substrate WT, the measurement means measures the relative position error between both objects CP, WT by imaging an alignment mark MC1 related to the chip CP and an alignment mark MC2 related to the substrate WT from at least one plane side (the upper side of the chip CP and/or the lower side of the substrate WT) out of two anti-opposite planes which are planes on the opposite side of each facing plane of both objects CP, WT.

Description

  The present invention relates to an alignment apparatus (such as a bonding apparatus) that aligns two objects and a technique related thereto.

  There is a chip bonding apparatus as one of alignment apparatuses that align two objects. The chip bonding apparatus is an apparatus that positions and arranges a semiconductor chip (hereinafter also simply referred to as a chip) on a substrate or the like and bonds the chip to the substrate or the like.

  For example, in Patent Document 1, the position of a substrate supported by a lower bonding stage is moved horizontally with respect to a chip held by an upper bonding tool, and the chip and the substrate are precisely positioned. A chip bonding apparatus for lowering a bonding tool is described.

  Specifically, the chip bonding apparatus described in Patent Document 1 includes a two-field camera (two cameras that simultaneously observe the vertical direction), and the two-field camera is connected to an upper chip and a lower substrate. By inserting in between, images relating to both the upper chip and the lower substrate are respectively acquired, and the positional deviation between the two in the horizontal direction is recognized. Then, the bonding stage is moved along the horizontal plane so as to reduce the positional deviation between the two (X, Y, and θ directions), whereby the chip is accurately positioned with respect to the substrate. Thereafter, the two-field camera is extracted from between the upper chip and the lower substrate, and the bonding tool is lowered in the vertical direction (Z direction) to bond the chip to the substrate (for example, thermocompression bonding).

  According to such an apparatus, the relative displacement (relative position error) between the chip and the substrate is measured immediately before bonding. Specifically, the relative position error is measured in a state where the chip is arranged at the bonding position (X, Y) in the XY plane parallel to the substrate plane. Therefore, it is possible to perform the alignment of the two accurately.

JP 2000-269242 A

  By the way, when a chip is placed on a substrate, high speed and accuracy are required.

  However, the technique described in Patent Document 1 requires time for inserting the two-field camera between the chip and the substrate and time for extracting the two-field camera from between the chip and the substrate. That is, it takes time to insert and remove the two-field camera. Therefore, there is a limit to speeding up in this technology.

  In the technique described in Patent Document 1, a two-field camera is inserted between the chip and the substrate, and the chip and the substrate are relatively separated from each other in the vertical direction (Z direction). The relative positional relationship between the two is obtained. For this reason, an error may occur when moving in the vertical direction after alignment, and the accuracy of the relative positions of the two after the vertical movement may not always be sufficient.

  Therefore, an object of the present invention is to provide an alignment technique capable of aligning two objects at higher speed and with higher accuracy.

  In order to solve the above problems, the invention of claim 1 is an alignment apparatus, wherein the first holding means for holding the first object, the second holding means for holding the second object, Both the first object and the second object are arranged to face each other, and the first object is located at a predetermined bonding position in a plane parallel to the placement surface of the second object. The alignment mark related to the first object and the second object from at least one surface side of two opposite surfaces that are surfaces opposite to the opposing surfaces of the two objects. The measurement means for measuring the relative position error between the two objects by imaging the alignment mark relating to the object, and the first object and the second object are parallel to the placement surface. Drive relative to the direction to correct the relative position error Characterized in that it comprises a driving means.

  According to a second aspect of the present invention, in the alignment apparatus according to the first aspect of the invention, the measuring means captures an image including an alignment mark related to the first object from the opposite surface side of the first object. It has a 1st object side imaging means, It is characterized by the above-mentioned.

  According to a third aspect of the present invention, in the alignment apparatus according to the second aspect of the present invention, the measuring means captures an image including an alignment mark related to the second object from the opposite surface side of the second object. It further has a 2nd object side image pick-up means, It is characterized by the above-mentioned.

  According to a fourth aspect of the present invention, in the alignment apparatus according to the third aspect of the present invention, an operation of imaging an image including an alignment mark related to the first object by the first object-side imaging means and the second object The operation of imaging the image including the alignment mark by the second object side imaging means is executed in parallel.

  According to a fifth aspect of the present invention, in the alignment apparatus according to the third aspect of the invention, the first apparatus is inserted between the first object and the second object at the predetermined bonding position. Supply means for delivering the object to the first holding means, wherein the supply means has a thin plate shape, and the first object-side imaging means includes the first object. An alignment mark relating to the first object is included within a period from the time when the supply means is transferred to the first holding means to the time when the supply means is retracted from the predetermined bonding position. The second object side imaging means picks up an image, and the second object side imaging means starts the supply from the predetermined bonding position from the time when the movement of the bonding target portion of the second object to the bonding position is completed. In the period until the saving completion of, characterized by capturing an image including an alignment mark for said second object.

  According to a sixth aspect of the present invention, in the alignment apparatus according to the third aspect of the present invention, the measuring means performs alignment on the first object before the first object contacts the second object. By imaging a mark and an alignment mark relating to the second object, a first relative position error between the two objects is measured, and the first object becomes the second object. After the contact, the second relative position error between the two objects is measured by imaging the alignment mark related to the first object and the alignment mark related to the second object. And

  According to a seventh aspect of the invention, in the alignment apparatus according to the sixth aspect of the invention, the measuring means executes an alignment failure determination process based on the second relative position error.

  According to an eighth aspect of the present invention, in the alignment apparatus according to the sixth aspect of the invention, the measuring unit is configured to perform the first operation related to the same type of object as the first object based on the second relative position error. A correction amount for the relative position error is determined.

  According to a ninth aspect of the present invention, in the alignment apparatus according to the second aspect of the invention, the first object-side imaging unit is configured to align the first object from the opposite surface side of the first object. And measuring the relative position error by capturing an image including an alignment mark related to the second object.

  According to a tenth aspect of the present invention, in the alignment apparatus according to the ninth aspect of the present invention, the alignment mark portion of the first object transmits infrared light, and the first object-side imaging means uses red as photographing light. An image including an alignment mark related to the first object and an alignment mark related to the second object is captured using external light.

  An eleventh aspect of the present invention is the alignment apparatus according to the ninth aspect of the invention, wherein the first object-side imaging means is both before and during contact of the first object with the second object. The relative position error is measured by capturing an image including an alignment mark related to the second object and an alignment mark related to the first object from the opposite surface side of the first object. It is characterized by doing.

  According to a twelfth aspect of the present invention, in the alignment apparatus according to the first aspect of the present invention, the measuring means includes an image including an alignment mark related to the first object and an alignment mark related to the second object. It has the 2nd object side imaging means which picturizes from the counter-opposite surface side of this object.

  According to a thirteenth aspect of the present invention, in the alignment apparatus according to the first or second aspect of the present invention, the measuring means captures a first image including a first alignment mark provided on the first object. A first imaging unit that performs imaging, a second imaging unit that captures a second image including a second alignment mark provided on the first object, the first image, and the second image. And calculating means for calculating the relative position error including a relative posture error between the two objects.

  According to a fourteenth aspect of the present invention, in the alignment apparatus according to the third aspect of the invention, the first object-side imaging means displays a first image including a first alignment mark provided on the first object. A first imaging unit that captures an image; and a second imaging unit that captures a second image including a second alignment mark provided on the first object, the second object side The imaging unit includes a third imaging unit that captures a third image including a third alignment mark provided on the second object, and the measurement unit includes the first image and the third image. Calculating means for calculating the relative position error including a relative posture error between the two objects based on the second image, the third image, and the posture angle of the second object at a reference time point; Furthermore, it is characterized by having.

  According to a fifteenth aspect of the present invention, in the alignment apparatus according to the fourteenth aspect of the invention, the posture angle of the second object at the reference time point is determined by each of two alignment marks provided on the second object. Is obtained based on two captured images captured by the third imaging unit.

  According to a sixteenth aspect of the present invention, in the alignment apparatus according to the second aspect of the present invention, a moving member connected to the first holding means and moving in the stacking direction of the two objects, and rotating around a predetermined axis together with the moving member The first object-side imaging means is connected to the rotating member and rotates together with the rotating member.

  According to a seventeenth aspect of the present invention, in the alignment apparatus according to the sixteenth aspect of the present invention, the first object side imaging means has an imaging unit, and changes the direction of the optical path of the photographic light with respect to the imaging unit. However, the imaging unit and the optical path changing member are each rotated about the predetermined axis in synchronization with the rotation of the rotating member.

  According to an eighteenth aspect of the present invention, in the alignment apparatus according to the seventeenth aspect of the present invention, the first holding means has a hollow portion for allowing photographing light to pass therethrough and is connected to the moving member. And rotating around the predetermined axis in synchronization with the rotation of the rotating member.

  According to a nineteenth aspect of the present invention, in the alignment apparatus according to any one of the first to eighteenth aspects of the present invention, the second object has a resin layer on its mounting surface, It further comprises resin curing means for curing the resin layer.

  According to a twentieth aspect of the present invention, in the alignment apparatus according to the nineteenth aspect of the invention, the resin layer is formed of a photocurable resin, and the resin curing unit is configured to irradiate the resin layer by ultraviolet irradiation by an ultraviolet irradiation unit. It is characterized by curing.

  According to a twenty-first aspect of the present invention, in the alignment apparatus according to the nineteenth aspect of the invention, the resin layer is formed of a thermosetting resin, and the resin curing means removes the resin layer by heating using a heating means. It is characterized by curing.

  According to a twenty-second aspect of the invention, in the alignment apparatus according to the nineteenth aspect of the invention, the resin layer is formed of a thermoplastic resin, and the resin curing means softens the resin layer by heating using a heating means. And the resin layer is cured by cooling accompanied by stopping the heating of the heating means.

  According to a twenty-third aspect of the present invention, in the alignment apparatus according to any one of the first to twenty-second aspects, the first object is a semiconductor chip, and the second object is a substrate. It is characterized by.

  The invention of claim 24 is an alignment method for aligning the first object held by the first holding means and the second object held by the second holding means, and a) Both the first object and the second object are arranged to face each other, and the first object is placed at a predetermined bonding position in a plane parallel to the placement surface of the second object. The alignment mark related to the first object and the second object from at least one surface side of two opposite surfaces that are surfaces opposite to the opposing surfaces of the two objects. Measuring a relative position error between the two objects by imaging an alignment mark relating to the object; and b) relative to the first object and the second object in the first direction. To correct the relative position error. Characterized in that it comprises a flop, a.

  According to the invention described in claims 1 to 24, compared to the technique described in Patent Document 1, it is not necessary to insert and remove the two-field camera, so that the speed can be increased. In addition, as compared with the technique described in Patent Document 1, it is not necessary to perform alignment in a state where a two-field camera is inserted between the two objects, and the two objects are relatively close to each other. Therefore, it is possible to achieve high accuracy.

  In particular, according to the invention described in claim 5, the period for alignment of both objects is provided separately from the supply operation period of the first object by the supplying means (including the retracting period of the supplying means). Since it is not necessary, further speedup can be achieved.

  In particular, according to the invention described in claim 11, more accurate alignment can be performed.

  In particular, according to the invention described in claim 13, two images related to two alignment marks provided on the first object can be taken at high speed using two imaging units.

  In particular, according to the invention described in claim 14, it is possible to calculate the relative position error including the relative posture error of both objects by using the three imaging units without requiring the four imaging units. Therefore, cost reduction can be achieved.

  In particular, according to the invention described in claim 17, since the imaging unit and the optical path changing member rotate in synchronization with the rotation of the rotating member, the optical path changing member can be used either before or after the rotating operation of the rotating member. It is possible to guide an image accompanied by an optical path change by the imaging unit.

  In particular, according to the invention described in claim 18, since the hollow portion also rotates in synchronization with the rotation of the rotating member, alignment marks provided at various positions while maintaining the area of the effective photographing portion. It is possible to photograph appropriately.

It is a figure showing composition of a chip mounting system concerning a 1st embodiment. It is a figure which shows a chip supply apparatus and a COW bonding apparatus. It is a figure which shows the structure of the upper side of a COW bonding apparatus. It is sectional drawing which shows the II cross section in FIG. It is sectional drawing which shows the II-II cross section in FIG. It is a top view which shows the structure of the stage vicinity in a COW bonding apparatus. It is sectional drawing which shows the structure of the lower side of a COW bonding apparatus. It is a figure which shows the chip | tip for a chip position adjustment provided in the chip | tip. It is a figure which shows the mark for chip position adjustment provided in the board | substrate. It is a figure which shows the relative position shift of both the chip position adjustment marks. It is a figure which shows the detailed structure of a head part. It is a figure which shows the positional relationship of the mark on a chip | tip, and the hollow part of a head part. It is a figure which shows the positional relationship of the mark on another chip | tip, and the hollow part of a head part. It is a figure which shows a mode that an imaging | photography range is changed according to the relative movement of the imaging part and mirror (optical path changing member) in a Z direction. It is a top view of a chip supply device and a COW bonding device. It is a top view of a chip supply device and a COW bonding device. It is a timing chart which shows the operation | movement which concerns on 1st Embodiment. It is a flowchart which shows an electronic component mounting operation. It is a flowchart which shows the lamination | stacking operation | movement of a 1st layer chip | tip. It is a flowchart which shows the lamination | stacking operation | movement of the chip | tip of each layer after the 2nd layer. It is a figure which shows the temporary board | substrate before resin layer formation. It is a figure which shows the temporary board | substrate with which the resin layer was formed. It is a figure which shows a mode that the 1st chip | tip is mounted on a temporary board | substrate. It is a figure which shows the state in which the 1st chip | tip was mounted on the temporary board | substrate. It is a figure which shows a mode that the 2nd chip | tip is mounted on a temporary board | substrate. It is a figure which shows the state by which the 2nd chip | tip was mounted on the temporary board | substrate. It is a figure which shows the state in which the some chip | tip was mounted on the temporary board | substrate. It is a figure which shows a mode that the upper and lower sides of a temporary board | substrate are reversed. In a WOW bonding apparatus, it is a figure which shows a mode that the board | substrate of joining object and the temporary board | substrate after flipping up and down are opposingly arranged. It is a figure which shows joining operation | movement of the several chip | tip in a WOW bonding apparatus. It is a figure which shows debonding operation | movement. It is a figure which shows the state in which the resin layer was formed in the 2nd temporary board | substrate. It is a figure which shows the state in which the several chip | tip was mounted in the 2nd temporary board | substrate. It is a figure which shows a mode that the upper and lower sides of a 2nd temporary board | substrate are reversed. It is a figure which shows a mode that the board | substrate with which the chip | tip of the 1st layer was joined, and the 2nd temporary board | substrate after turning upside down are opposingly arranged. It is a figure which shows joining operation | movement of the chip | tip of a 1st layer, and the chip | tip of a 2nd layer. It is a figure which shows the debonding operation | movement which concerns on a 2nd temporary board | substrate. It is a figure which shows the state by which the chip | tip of multiple layers was laminated | stacked on the board | substrate of joining object. It is sectional drawing which shows the stage vicinity of the COW bonding apparatus which concerns on 2nd Embodiment. It is a timing chart which shows the alignment operation | movement which concerns on 3rd Embodiment. It is a figure which shows the head part which concerns on a modification. It is a figure which shows the imaging part which concerns on a modification. It is a figure which shows a mode that a chip | tip is mounted in a board | substrate in a face-down state. It is a figure which shows the chip supply apparatus which has a chip inversion mechanism. It is a top view which shows the chip supply apparatus etc. of a chip tray system. It is sectional drawing which shows the component tray conveyance part vicinity. It is a top view which shows the chip supply apparatus etc. which have a finished product tray conveyance part. It is sectional drawing which shows the finished product tray conveyance part vicinity. It is a timing chart which shows the operation | movement which concerns on a comparative example.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

<1. First Embodiment>
<1-1. Overview>
In this embodiment, as will be described later, by performing each process as shown in FIGS. 18 to 20, a plurality of layers of electronic components (here, semiconductor chips (simply referred to as chips) in a plurality of plane positions on the substrate WA are performed. (Also referred to as FIG. 38). FIG. 38 illustrates a state where a plurality of chips of three layers are stacked. 18 to 20 are flowcharts showing the electronic component mounting operation.

  In this embodiment, basically, the operation of bonding each chip CPi of the i-th layer (i = 1, 2,...) To the substrate WA (see FIG. 38) side to be bonded is repeatedly executed. As a result, a plurality of layers of chips are stacked on the substrate WA. The stacking operation of each layer is basically the same as each other. However, in the stacking operation of the first layer, each chip CP1 of the first layer is directly bonded to the substrate WA, whereas the stacking operation of the i-th layer (i> 2) after the second layer. 1 is different in that each chip CPi of the i-th layer disposed on the temporary substrate WTi is bonded to each chip of the (i-1) -th layer stacked on the substrate WA.

  More specifically, as shown in FIG. 18, first, steps S11 to S14 are executed, whereby the first layer chip stacking operation (see also step S10 and FIG. 19) is performed on the substrate WA. The plurality of chips CP1 in the first layer are joined (see also FIGS. 21 to 31).

  Next, by performing the following steps S21 to S24, the stacking operation of the chips of the second and subsequent layers (i-th layer) (i> 2) (see also step S20 and FIG. 20) is as follows. (See also FIGS. 32 to 37).

  Step S21: The resin layer RSi is formed on the temporary substrate WTi.

  Step S22: The plurality of chips CPi in the i-th layer are arranged in a plane on the resin layer RSi on the substrate WTi and temporarily fixed in a face-up state.

  Step S23: The substrate WTi is turned upside down to hold the plurality of i-th layer chips CPi on the substrate WTi in a face-down state, and the plurality of i-th layer chips CPi in the face-down state and the first ( i-1) A plurality of chips CP (i-1) in the layer are relatively brought close to each other. Then, the plurality of chips CPi in the i-th layer are placed on (contacted with) the plurality of chips CP (i-1) in the (i-1) -th layer, and the plurality of chips in the (i-1) -th layer. CP (i-1) and the plurality of chips CPi in the i-th layer are bonded to each other.

  Step S24: While maintaining the state in which the plurality of chips CPi in the i-th layer are respectively joined to the plurality of chips CP (i-1) in the (i-1) -th layer, from the plurality of chips CPi in the i-th layer The substrate WTi is separated. The processing in step S24 is also referred to as debonding processing.

  As described above, a plurality of i-th layer chips CPi are further laminated and bonded onto the (i-1) -th layer chips CP (i-1) bonded onto the substrate WA. .

  According to this, it is possible to more easily realize stacking of chips (electronic components) and mounting on a substrate.

  In addition, each process of step S11-S14 regarding a 1st layer is a process similar to the corresponding process of steps S21-S24 regarding each layer after the 2nd layer, respectively. However, the processes in steps S13 and S14 are different from the processes in steps S23 and S24, respectively, in the points described above. That is, in steps S23 and S24, the chip CPi of the i-th layer (i> 2) after the second layer is placed on the chip CPi of the (i-1) -th layer that has already been stacked. In steps S13 and S14, the first layer chip CPi is directly placed on the substrate WA.

  Below, operation | movement as mentioned above and the chip | tip mounting system 1 which performs the said operation | movement are demonstrated in detail.

<1-2. System configuration>
First, the configuration of the chip mounting system 1 (also referred to as 1A) according to this embodiment will be described.

  FIG. 1 is a top view showing a schematic configuration of a chip mounting system (electronic component mounting system) 1. In FIG. 1 and the like, directions and the like are shown using an XYZ orthogonal coordinate system for convenience.

  The chip mounting system 1 is a system for stacking and mounting multilayer chips at a plurality of planar positions on a substrate (substrate to be mounted on a chip). For example, the chip mounting system 1 can bond a plurality of chips CP1 in the first layer on the target substrate WA. The chip mounting system 1 can also stack and bond a plurality of second-layer chips CP2 and the like on a plurality of first-layer chips CP1 arranged on the substrate WA.

  In this embodiment, the substrate WA is a semiconductor wafer, and each temporary substrate WTi (described later) is a glass substrate. However, the present invention is not limited to this, and each of the substrates WA and WTi may be various substrates.

  As shown in FIG. 1, the chip mounting system 1 is also referred to as a chip supply device 10, a bonding device 30 (also referred to as a COW (Chip On Wafer) bonding device), and a bonding device 50 (a WOW (Wafer On Wafer) bonding device). ), A transport unit 70, and a carry-in / out unit 90. The chip mounting system 1 also includes a spin coater 80 (not shown).

  The spin coater 80 is an apparatus that forms a resin layer RSi on the temporary substrate WTi using a spin coating technique.

  The chip supply apparatus 10 is an apparatus that takes out each chip CP from the diced wafer and supplies each chip CP (CPi) to the COW bonding apparatus 30. The chip supply device 10 includes a protruding portion 11 and a chip transfer device 13 (see FIG. 2).

  The COW bonding apparatus 30 is an apparatus (also referred to as an alignment apparatus) that positions and arranges a plurality of chips CP supplied from the chip supply apparatus 10 on a substrate. For example, the COW bonding apparatus 30 planarly arranges a plurality of chips (electronic components) CPi on the resin layer RSi formed on the temporary substrate WTi with the joint surfaces facing upward (face-up state) ( A plurality of chips are temporarily fixed to the resin layer RSi. For example, a thermoplastic resin is employed as the resin layer RSi.

  The configurations of the COW bonding device 30 and the chip supply device 10 will be described in detail later.

  The transfer unit 70 uses the transfer robot 71 to transfer the substrate (the substrate WA and the temporary substrate WTi) among the carry-in / out unit 90, the COW bonding apparatus 30, and the WOW bonding apparatus 50. In addition, the transfer robot 71 of the transfer unit 70 also performs an operation of turning the substrate (particularly the temporary substrate WTi) upside down.

  As shown in FIG. 29, the WOW bonding apparatus 50 includes a lower stage 51, an upper stage 53, an imaging unit 55 (55a and 55b in detail), a position recognition unit 56 (not shown), and the like. The imaging unit 55 acquires a light image related to marks MW1 and MW2 (described later) as image data. Further, the position recognizing unit 56 recognizes the relative positional relationship between the substrate WA held on the lower stage 51 and the temporary substrate WTi held on the upper stage 53 based on the image taken by the imaging unit 55. Specifically, the position recognition unit 56 uses the marks MW1 and MW2 to obtain the relative positional relationship between the substrate WA and the temporary substrate WTi in a direction parallel to the substrate plane of the temporary substrate WTi.

  The upper stage 53 is movable in the Z direction by a Z direction driving mechanism. Further, the lower stage 51 is movable in the X direction, the Y direction, and the θ direction by the XYθ direction drive mechanism. As a result, the relative positional relationship between the upper stage 53 and the lower stage 51 can be changed. As a result, the positional relationship between the temporary substrate WTi and the substrate WA is adjusted, and further, a plurality of chips in the i-th layer. It is possible to adjust the positional relationship between CPi and the plurality of chips CP (i-1) in the (i-1) th layer.

  The WOW bonding apparatus 50 is an apparatus that executes a bonding operation between the substrate WA and the temporary substrate WTi. Specifically, the WOW bonding apparatus 50 holds the substrate WA on the lower stage 51 and holds the temporary substrate WTi on the upper stage 53. In the WOW bonding apparatus 50, the substrate WA is arranged with its bonding surface facing upward (face-up state). The temporary substrate WTi is held on the stage 31 in a face-up state in the COW bonding apparatus 30, but the upper stage 53 in a face-down state (with its bonding surface facing downward) in the WOW bonding apparatus 50. Retained. Specifically, the temporary substrate WTi is taken out of the COW bonding apparatus 30 by the transfer robot 71, turned upside down by the transfer robot 71, transferred to the WOW bonding apparatus 50, and held on the upper stage 53 in a face-down state. Is done.

  The WOW bonding apparatus 50 relatively brings the substrates WA and WTi closer together with the substrate WA and the temporary substrate WTi after being turned upside down facing each other. As a result, the plurality of i-th layer chips CPi held in the face-down state on the temporary substrate WTi after being turned upside down approach toward the substrate WA. Then, the plurality of i-th layer chips CPi are bonded to the substrate WA side.

  The WOW bonding apparatus 50 is an apparatus that collectively bonds (bonds) the plurality of chips CPi in the i-th layer and the plurality of chips CP (i-1) in the (i-1) -th layer. It is also called a collective joining device (gang bonder).

  In the WOW bonding apparatus 50, a separation process for separating the temporary substrate WTi from the plurality of chips CPi in the i-th layer is also executed. This separation process is performed while maintaining a state in which the plurality of i-th layer chips CPi are bonded to the substrate WA side. This separation process is performed, for example, by heating the resin layer RSi of the temporary substrate WTi with a heater (heating processing unit) built in the upper stage 53 that holds the temporary substrate WTi.

<1-3. Chip Supply Device 10>
The chip supply device 10 is a device that supplies each chip CP taken out from the substrate WC by a dicing process or the like to the COW bonding device 30. The dicing process is a process of cutting the substrate WC having a plurality of electronic circuits in the vertical direction and the horizontal direction into chips.

  As shown in FIG. 2, the chip supply device 10 includes a protruding portion (protruding needle) 11, a chip transfer device 13, and the like. The chip transfer device 13 includes a die picker 131 and a chip feeder 135.

  In the chip supply device 10 (FIG. 2), a plurality of diced chips CP are placed on the dicing tape TE. In FIG. 2, each chip CP is placed on the dicing tape TE in a face-up state (the surface on which the solder bumps BU are attached faces upward).

  Then, the cut chips CP are pushed up one by one by the protruding upper portion (protruding needle) 11 (FIG. 2) of the chip supply device 10 and delivered to the die picker 131 at the position PG1. The die picker 131 sucks the chip CP at the tip (lower end) suction part, moves further upward, and then moves toward the chip transport part 39 side of the COW bonding apparatus 30, and places the chip CP on the temporary placement table 133. And evacuate. Thereafter, the chip supply unit 135 sucks the chip CP on the temporary placement table 133 and moves toward the chip transfer unit 39 side of the COW bonding apparatus 30.

  When the chip transport unit 39 receives the chip CP from the chip supplier 135 at a position PG3 (also a receiving position PR1 (FIG. 15) to be described later), the chip transport unit 39 rotates the head CP of the bonding unit 33 around the central axis AX. It is transported to a position PG5 (delivery position PR2 (FIG. 16)) directly below the section 33H (described later). The chip CP reaches the delivery position PR2 in the face-up state through such a transport operation.

  Thereafter, the bonding operation by the bonding unit 33 is further executed. The bonding operation will be described later.

  In addition, although the case where each chip CP is conveyed to the delivery position PR2 in the face-up state is illustrated here, the present invention is not limited to this. For example, as will be described later, each chip CP may be turned upside down in the middle of the transport path and transferred to the delivery position PR2 after transition from the face-up state to the face-down state (FIG. 44). reference).

<1-4. COW Bonding Device 30>
2 and 3, the COW bonding apparatus 30 includes a stage 31, a bonding unit 33, a Z direction driving unit 34, an imaging unit (camera) 35, a position recognition unit 46 (not shown), and a θ direction rotation. Part 36, θ-direction drive part 37, bearing 38, and rotary chip transport part 39.

<Bonding part 33>
The bonding part 33 is a part for placing the chip CP on the substrate WT, and is also referred to as a chip mounter.

  As shown in FIG. 3, the bonding portion 33 includes a Z-axis direction moving member 331, an upper disk member 332, a piezo actuator 333, a lower disk member 334, a mirror fixing member 336, a mirror (optical path changing member) 337, and a head portion. 33H (also referred to as a bonding head portion).

  An upper disk member 332 is fixed to the lower end of the Z-axis direction moving member 331. A lower disk member 334 is disposed below the upper disk member 332. The upper disk member 332 and the lower disk member 334 are connected via three piezo actuators 333. Further, the head portion 33H is fixed to the lower surface side of the lower disk member 334. Thus, the Z-axis direction moving member 331 is connected to the head portion 33H via the upper disk member 332, the piezo actuator 333, the lower disk member 334, and the like.

  The head portion 33H is a holding member that sucks and holds the chip CP, and is also expressed as a chip holding member (electronic component holding member).

  As shown in FIG. 11, the head portion 33 </ b> H includes a tip tool 411 and a head main body portion 413. The tip tool 411 is formed of a member (silicon (Si) or the like) that transmits photographing light (infrared light or the like). The head main body 413 is formed with a built-in ceramic heater, for example. Ceramic heaters can be subjected to rapid heat treatment (compared to coil heaters and the like). The head main body 413 has hollow portions (holes) 415 and 416 for transmitting (passing) photographing light. Each of the hollow portions 415 and 416 is a transmission portion (also referred to as a slit portion) that transmits photographing light, and is provided so as to penetrate the head main body portion 413 in the vertical direction. Specifically, each of the hollow portions 415 and 416 has an elliptical shape in a top view. The two hollow portions 415 and 416 are arranged symmetrically with respect to the axis BX in a diagonal portion of the head main body 413 having a substantially square shape when viewed from above (see also FIG. 12). In order to transmit photographing light, a hole (hollow part) is also provided in a corresponding part of the lower disk member 334 and the like.

  By controlling the degree of expansion and contraction in the Z direction of each of the three piezoelectric actuators 333 (FIG. 3), the inclination angle of the lower disk member 334 (and thus the head portion 33H) with respect to the horizontal plane is adjusted. For example, it is possible to perform a parallel adjustment operation of the lower disk member 334 (and the head portion 33H) with respect to the ground plane. Note that the three piezoelectric actuators 333 are arranged at positions (planar positions) that do not block illumination light (including reflected light) related to the imaging unit 35 (see also FIG. 5).

  Further, the upper disk member 332 (FIG. 3) is provided with a mirror (optical path changing member) 337. Specifically, the mirror 337 is fixed to the upper disk member 332 via the mirror fixing member 336, and is disposed in the gap between the upper disk member 332 and the lower disk member 334. Thus, the mirror 337 is provided connected to the Z-axis direction moving member 331. The mirror 337 has two inclined planes having an inclination angle of 45 degrees obliquely downward. The mirror 337 is an optical path changing member that changes the direction of the optical path of imaging light (illumination light (including its reflected light)) related to the imaging unit 35 using these inclined planes.

<Z direction drive unit 34>
The Z-direction drive unit (also referred to as Z-direction drive mechanism) 34 has a servo motor and a ball screw. The Z-direction drive unit 34 is provided on the upper end side of the θ-direction rotation unit 36 (rotation member 361 (described later)), and the bonding unit 33 (specifically, the Z-axis direction movement member 331) is moved in the Z direction (vertical direction). To drive. When the Z-axis direction moving member 331 is moved in the Z direction by the Z-direction drive unit 34, the head portion 33H on the lower end side of the bonding unit 33 is also moved in the Z direction along with the moving operation. That is, the head portion 33H is driven in the Z direction (also referred to as a chip stacking direction with respect to the substrate) by the Z direction driving portion 34.

<Θ direction rotation part 36>
The θ-direction rotating part 36 has a substantially cylindrical rotating member 361. The rotating member 361 is fixed in the vertical direction (Z direction) at the upper part of the main body of the COW bonding apparatus 30 (in the vicinity of the housing 30K) and can be rotated around the rotation axis BX. The rotating member 361 is rotated around the rotation axis BX by the θ-direction driving unit 37 provided in the upper housing portion of the COW bonding apparatus 30. The θ-direction drive unit (also referred to as θ-direction drive mechanism) 37 includes a servo motor and a gear mechanism.

  Further, a Z-axis direction moving member 331 of the bonding portion 33 is disposed in the internal space of the substantially cylindrical rotating member 361 via a bearing 38.

  FIG. 4 is a cross-sectional view taken along the line II of FIG. As shown also in FIG. 4, the Z-axis direction moving member 331 is a rod-shaped member (substantially octagonal prism-shaped member) having a substantially octagonal cross section. Further, the rotating member 361 having a substantially cylindrical outer peripheral surface has a substantially octagonal column-shaped hole (gap) on the inner peripheral side thereof. And the Z-axis direction moving member 331 is inserted and arrange | positioned at the said hole. Further, a bearing 38 is provided between the inner peripheral surface of the rotating member 361 and the Z-axis direction moving member 331. Specifically, the bearings 38 are respectively provided on every other four side surfaces of the eight side surfaces of the Z-axis direction moving member 331. Each bearing 38 is extended and arranged in the Z direction. With such a configuration, the Z-axis direction moving member 331 can smoothly slide in the vertical direction (Z direction) with respect to the inner peripheral surface of the rotating member 361.

  The Z-axis direction moving member 331, which is a substantially octagonal prism-shaped member, is in contact with the inner surface of the rotating member 361 via the bearing 38 on the four side surfaces, and in the horizontal direction, It does not move relative to it. Therefore, the Z-axis direction moving member 331 rotates together with the rotation member 361 in accordance with the rotation operation about the rotation axis BX of the rotation member 361. That is, the Z-axis direction moving member 331 and the rotating member 361 rotate around the rotation axis BX in synchronization. As a result, the bonding part 33 and the θ-direction rotating part 36 rotate around the rotation axis BX in synchronization.

<Imaging unit 35>
Two imaging units 35 (35a, 35b) are connected to the rotation member 361 of the θ-direction rotation unit 36. Specifically, the imaging unit 35a is connected to the rotating member 361 via the camera Z direction driving unit 363, the camera F direction driving unit 365, and the like, and the imaging unit 35b is connected to the camera Z direction driving unit 363 and the camera F. It is connected to the rotating member 361 via the direction driving unit 365 and the like.

  The imaging unit 35 (specifically, 35a and 35b) acquires an optical image related to marks MC1 and MC2 (described later) as image data. The position recognition unit 46 recognizes the position of each chip CP on the temporary substrate WTi based on the image captured by the imaging unit 35. Specifically, the position recognition unit 46 uses the marks MC1 and MC2 to determine the position of each chip in the direction parallel to the substrate plane of the temporary substrate WTi (the relationship between each chip and the substrate WTi in the plane parallel to the substrate WTi). (Relative position relationship).

  Each imaging unit 35a, 35b has an imaging sensor 351 and a lens unit 352, respectively. In addition, each of the imaging units 35a and 35b has a coaxial illumination system, and relates to reflected light of illumination light (here, infrared light) emitted from a light source (also referred to as an emission unit) of the coaxial illumination system. Get image data. Illumination light emitted in the horizontal direction from the respective coaxial illumination systems of the imaging units 35a and 35b is reflected by a mirror (optical path changing member) 337 (FIG. 3), and the traveling direction thereof is changed vertically downward. . Then, the light travels toward the photographing target portion including the chip CP (FIG. 2) held by the head portion 33H and the temporary substrate WTi disposed to face the chip CP, and is reflected by the photographing target portion. The Further, the reflected light from the imaging target portion travels upward, and then is reflected again by the mirror (optical path changing member) 337, and the traveling direction is changed to the horizontal direction, so that each of the imaging units 35a and 35b. To reach. Thereby, the image data (image data by reflected light) regarding the optical image of the imaging target portion is acquired. For example, the mark MC1 (MC1a, MC1b) arranged in the chip CP held by the head portion 33H and the mark MC2 (MC2a, MC2b) arranged in the temporary substrate WTi arranged to face the chip CP are used. Including image data is acquired. More specifically, the imaging unit 35a acquires image data including the mark MC1a and the mark MC2a, and the imaging unit 35b acquires image data including the mark MC1b and the mark MC2b.

  In this embodiment, the case where image data by reflected light is acquired is illustrated, but the present invention is not limited to this, and image data by transmitted light may be acquired.

<Z-direction synchronous movement and focus adjustment>
The imaging units 35a and 35b are respectively driven in the focus direction by the camera F direction driving unit 365 (FIG. 3), thereby adjusting the in-focus state of each captured image by the imaging units 35a and 35b.

  The imaging units 35a and 35b are each driven in the Z direction (vertical direction) by the camera Z direction driving unit 363 (FIG. 3).

  Basically, the imaging units 35a and 35b are respectively Z-axis direction moving members so that the Z-direction movement amount of the Z-axis direction moving member 331 and the Z-direction movement amounts of the imaging units 35a and 35b are the same. In synchronization with the movement of 331 in the Z direction, each camera Z direction driving unit 363 moves the camera in the Z direction. According to this, even if the Z-axis direction moving member 331 (and thus the head portion 33H) moves in the Z direction, the imaging target ranges of the imaging units 35a and 35b are unchanged before and after the movement.

<Asynchronous movement in Z direction (change of shooting range)>
However, the imaging units 35a and 35b are moved in the Z direction by the camera Z direction driving units 363 so that the Z direction movement amounts of the imaging units 35a and 35b are different from the Z direction movement amounts of the Z-axis direction moving member 331. Sometimes. According to this, the relative positions in the Z direction of the imaging units 35a and 35b and the mirror 337 change, respectively, and the shooting target ranges by the imaging units 35a and 35b are changed.

  For example, as shown in FIG. 14, when the imaging unit 35a moves a small amount in the Z direction toward a position relatively above the mirror 337, the imaging target range of the imaging unit 35a is relatively far from the central axis BX. Shift to the specified range. The same applies to the imaging unit 35b. In other words, when the imaging units 35a and 35b move relatively upward with respect to the mirror 337, the imaging ranges by the imaging units 35a and 35b are shifted relatively outward, respectively. The distance from the imaging range by the imaging unit 35a is relatively large. In FIG. 14, the optical axes of the imaging units 35 a and 35 b before movement are indicated by thin two-dot chain lines, and the optical axes of the imaging units 35 a and 35 b after movement are indicated by thin solid lines.

  Conversely, when the imaging units 35a and 35b move downward relative to the mirror 337, the imaging ranges of the imaging units 35a and 35b are shifted relatively inward (center axis BX side), and imaging is performed. The interval between the shooting range by the unit 35a and the shooting range by the imaging unit 35a is relatively small. In this way, the interval (pitch) between the two shooting ranges can be adjusted.

<Θ direction synchronous rotation>
The imaging units 35a and 35b are connected to a rotating member 361 (FIG. 3) and rotate together with the rotating member 361.

  As described above, the rotating member 361 and the Z-axis direction moving member 331 rotate in synchronization. Further, each imaging unit 35a, 35b is connected to a rotation member 361 (fixed in the θ direction), and the mirror 337 is connected (fixed) to a Z-axis direction moving member 331. Therefore, the two imaging units 35a and 35b and the mirror 337 rotate in synchronization with the rotating member 361. As a result, the relative positional relationship between the two imaging units 35a and 35b and the mirror 337 in a plane parallel to the horizontal plane is unchanged before and after the rotation operation. Therefore, an image accompanied by an optical path change by the mirror 337 (an image near the position immediately below the mirror) can be guided to the imaging units 35a and 35b before and after the rotational operation of the rotating member 361.

  Further, the hollow portions (transmission portions) 415 and 416 of the head portion 33H also rotate around the axis BX in synchronization with the rotation of the rotation member 361. According to this, it is possible to flexibly change the imaging range of each imaging unit 35a, 35b according to the shape of the chip and the like.

  For example, as shown in FIG. 12, for the chip CP having a substantially square shape (and having the marks MC1a and MC1b at the diagonal portions), the imaging units 35a and 35b are arranged on the diagonal line of the chip. Just do it. More specifically, the rotation member 361 is moved to a position where the common optical axis CX (see also FIG. 11) of the imaging units 35a and 35b is inclined by about 45 degrees with respect to a certain side of the rectangular chip CP. Rotate in the direction. Accordingly, an image including the marks MC1a and MC1b (and MC2a and MC2b) can be captured using the imaging light passing through the hollow portions 415 and 416. Note that the portion corresponding to the hollow portions 415 and 416 in the captured image is also expressed as an effective captured portion. On the other hand, a portion corresponding to other than the hollow portions 415 and 416 (portion through which the photographing light cannot be transmitted) is also expressed as an invalid photographing portion.

  Further, as shown in FIG. 13, for the chip CP having a horizontally long rectangular shape (and having the marks MC1a and MC1b at the diagonal portions), the common optical axis CX of the imaging units 35a and 35b is rectangular. The rotation member 361 is rotated in the θ direction to a position inclined at an angle shallower than 45 degrees (for example, about 25 degrees) with respect to the lateral side of the shape chip CP. Accordingly, an image including the marks MC1a and MC1b (and MC2a and MC2b) can be captured using the imaging light transmitted through the hollow portions (transmission portions) 415 and 416. The rotation angle θ of the rotation member 361 in FIG. 13 is different from the rotation angle θ of the rotation member 361 in FIG.

  Thus, it is possible to photograph each mark more appropriately by changing the rotation angle of the rotation member 361 in the θ direction according to the mark position on the chip.

  It is also conceivable to rotate the head portion 33H in the θ direction independently of the rotating member 361. However, in that case, photographing light may be blocked by portions other than the hollow portions 415 and 416. That is, it is difficult to fit each mark on the chip within an effective photographing part. On the other hand, as described above, the hollow portions (transmission portions) 415 and 416 of the head portion 33H rotate around the axis BX together with the imaging portions 35a and 35b and the mirror 337 in synchronization with the rotation of the rotating member 361. Accordingly, it is possible to relatively easily cope with marks provided at various positions on the chip while maintaining the area of the effective photographing portion.

<Stage 31>
The stage 31 (FIG. 2) is movable in the X direction and the Y direction by an XY direction driving mechanism. Thereby, the relative positional relationship between the bonding portion 33 and the stage 31 can be changed, and as a result, the position of each chip CPi on the temporary substrate WTi can be adjusted.

  6 and 7, the stage 31 includes an X direction moving unit 311, a Y direction moving unit 313, a substrate holding unit 315, an X direction driving unit (X direction driving mechanism) 321, and a Y direction driving unit (Y Direction driving mechanism) 323.

  On the base member 301 (FIG. 7) of the COW bonding apparatus 30, an X direction moving unit 311 is disposed via an X direction driving unit (X direction driving mechanism) 321. The X direction driving unit 321 includes a linear motor, a slide rail, and the like, and drives the X direction moving unit 311 with respect to the base member 301 in the X direction. In FIG. 6, two X-direction drive units 321 each extending in the X direction are provided with a predetermined distance apart in the Y direction.

  On the X direction moving unit 311, a Y direction moving unit 313 is arranged via a Y direction driving unit (Y direction driving mechanism) 323. The Y direction driving unit 323 includes a linear motor, a slide rail, and the like, and drives the Y direction moving unit 313 in the Y direction with respect to the X direction moving unit 311. 6 and 7, two Y-direction drive units 323 extending in the Y direction are provided at a predetermined distance in the X direction.

  A substrate holding unit 315 is fixed to the Y-direction moving unit 313. The substrate holding unit 315 is driven in the X direction and the Y direction according to the driving of the X direction driving unit 321 and the Y direction driving unit 323.

  Further, a rectangular hollow portion (hole portion) 312 is provided in the central portion of the X-direction moving portion 311. Similarly, a rectangular hollow portion (hole portion) 314 is provided in the central portion of the Y-direction moving portion 313. Further, a circular hollow portion (hole portion) 316 is provided at the central portion of the substrate holding portion 315. An infrared irradiation unit 318 is provided in a portion corresponding to the hollow portions 312, 314, and 316. The infrared irradiation unit 318 can heat the substrate WTi and the like by infrared irradiation.

<Chip transfer unit 39>
A chip transport unit (also referred to as a turret) 39 (FIG. 2) is a device that delivers a chip supplied from the chip supply device 10 to the bonding unit 33 (specifically, the head unit 33H).

  The chip transport unit 39 includes a plurality of (N: here, three) blade portions (plate portions) 391 (see FIG. 15). Each plate portion 391 has a thin plate shape, and has a thickness of, for example, about several mm (millimeters) (preferably about 1 mm to 2 mm or less). The plurality of plate portions 391 are arranged at equal intervals around the axis AX in a top view. Note that it is preferable that an odd number of plate portions 391 (eg, 3, 5, 7, 9, etc.) be provided.

  The chip transport unit 39 also includes a drive unit 392 that rotationally drives the plurality of plate units 391 all at once. The chip transport unit 39 can rotate the plurality of plate units 391 around a predetermined vertical axis AX using the drive unit 392.

  As shown in FIG. 15, the chip CP supplied from the chip supply device 10 is one of the three plate portions 391 (specifically, 391a, 391b, 391c) of the chip transfer unit 39 (for example, 391b). Received by. Thereafter, after the plate portion 391 rotates 180 degrees, the chip on the plate portion 391 is delivered to the bonding portion 33 (head portion 33H).

  Further, the chip transport unit 39 has a plurality of plate units 391, and the same operation is continuously repeated.

  More specifically, the chip transport unit 39 having N (here, N = 3) plate portions 391 is rotated by an angle β (here, 60 degrees (= 360 degrees / (N * 2) = 360/6)). Each time the chip CP is received from the chip supply device 10 to the plate unit 391 and the chip CP is transferred from the plate unit 391 to the bonding unit 33 (head unit 33H), the operation is alternately executed.

  For example, as shown in FIG. 15, a certain chip CP is received by the plate portion 391b at the receiving position PR1 and placed on the plate portion 391b. That is, the chip receiving operation by the plate portion 391b is executed. At this time, another chip CP is already received by the plate portion 391a and placed on the plate portion 391a, and exists at the position PR9.

  From this state, when the chip transport section 391 rotates around the axis AX (clockwise) by an angle β (60 degrees), as shown in FIG. 16, the chip CP on the plate section 391a is positioned immediately below the head section 33H ( It moves to the delivery position PR2). The head portion 33H is slightly lowered from a predetermined reference position (a position that does not interfere with the chip CP), receives the chip CP on the plate portion 391a, and sucks the chip CP at the tip portion (lower end portion) of the head portion 33H. . The head portion 33H, after sucking the chip CP on the plate portion 391a, rises slightly and returns to the original Z-direction position (reference position). Thereby, the chip CP on the plate portion 391a is transferred to the head portion 33H. In this manner, the operation of transferring the chip CP from the plate portion 391a to the head portion 33H is performed.

  At this time, the chip transport unit 391 (specifically, the plate unit 391a) is inserted between the upper chip CP and the lower substrate WT at the delivery position PR2 (the same position as the bonding position on the XY plane). In this state, the chip CP is delivered to the head portion 33H.

  Next, the rotation operation of the angle β is executed again. This time, the plate portion 391c moves to the receiving position PR1. In this state, another chip CP is received by the plate portion 391c at the receiving position PR1. At this time, the chip CP is already placed on the plate portion 391b by the above-described operation.

  By the rotation operation of this angle β, the plate portion 391a moves from a position directly below the head portion 33H, and interference between the plate portion 391a and the head portion 33H is avoided. This rotation operation is also expressed as an operation (retraction operation) in which the plate portion 391a is retracted from the bonding position (X, Y). Then, after the retracting operation, the head portion 33H is lowered in a state where the head portion 33H and the chip transfer portion 39 do not interfere with each other, and the chip CP attracted and held by the head portion 33H is lowered to the position PG7 (FIG. 2). The As a result, the chip CP adsorbed at the tip of the head portion 33H is placed at a predetermined plane position on the temporary substrate WT1 on the stage 31. At this time, an alignment operation (alignment operation), which will be described later, is executed, and the chip CP is placed at a desired position on the substrate WTi. Thereafter, the head portion 33H rises and returns to the reference position again, and interference between the plate portion 391a and the head portion 33H is avoided.

  Thereafter, when the rotation operation of the angle β is further executed, the plate portion 391b is moved to the delivery position PR2, and the delivery operation of the chip CP from the plate portion 391b to the head portion 33H is executed.

  Further, the rotation operation of the angle β is further performed, and the plate portion 391a is moved to the receiving position PR1 this time, and the chip CP receiving operation by the plate portion 391a is executed.

  Thereafter, the same operation is repeatedly executed.

  Here, odd (particularly three or more) plate portions 391 are arranged at substantially equal intervals around the axis AX (at an angle γ (= β × 2) interval), and the chip transporting portion 39 has an angle β (= [gamma] / 2) Every time it rotates, the chip receiving operation at the position PR1 and the chip delivery operation at the position PR2 can be executed alternately without interfering with each other.

  In particular, each chip CP can be supplied for each rotational movement of the angle γ by the rotary chip transport unit 39. Specifically, after a certain chip is placed, the next chip can be supplied by rotational movement at an angle β (for example, 60 degrees). Accordingly, a plurality of chips CP are sequentially supplied at a relatively small time interval as compared with the case where the chips CP are transported one by one (reciprocal transport) from the position PR1 to the position PR2 using one transfer unit. Is possible. That is, it is possible to shorten the cycle time in chip supply. In particular, the larger the number N of plate portions 391, the shorter the moving distance per time, so the supply time interval can be shortened.

<1-5. Chip position adjustment mark MC>
In this embodiment (see steps S12 and S22), each chip CP (CPi) is positioned in the horizontal direction and placed on the temporary substrate WTi using alignment marks MC1 and MC2 (see FIG. 23 and the like).

  The alignment marks MC1 and MC2 are marks for adjusting the position of the chip CP (electronic component), and are also referred to as chip position adjustment marks (or component position adjustment marks). Here, two marks MC1a and MC1b are provided as the mark MC1 for one chip CP. Similarly, two marks MC2a and MC2b are provided as a mark MC2 per chip CP. The mark MC1 is provided on the chip CP, and the mark MC2 is provided on the substrate. Further, the mark MC1 application portion of the chip CP and the mark MC2 application portion of the substrate transmit photographing light (infrared light or the like).

  The two types of marks MC1 and MC2 have different shapes (more specifically, shapes that do not overlap each other). For example, as shown in FIG. 8, a circular shape having a relatively small diameter is used as the mark MC1 (specifically, the marks MC1a and MC1b). On the other hand, as shown in FIG. 9, a circular shape having a relatively large diameter is used as the mark MC2 (specifically, the marks MC2a and MC2b).

  The mark MC1a is provided at a first reference position (planar position) (left front side in FIG. 8) in each chip CP, and the mark MC1b is a second reference position (planar position) in each chip CP (FIG. 8). Then, it is provided on the right back side. Further, the mark MC2a is provided at a regular position (planar position) corresponding to the first reference position of each chip CP on the temporary substrate WTi, and the mark MC2b is the second reference of each chip CP on the temporary substrate WTi. It is provided at a regular position (planar position) corresponding to the position. In short, the mark MC2a is provided at a position corresponding to the mark MC1a, and the mark MC2b is provided at a position corresponding to the mark MC1b. In addition, in order to satisfactorily adjust the relative angle between each chip CP and temporary substrate WTi, marks MC1a and MC1b may be provided at positions separated from each other (for example, near both ends of chip CP). preferable. The same applies to the marks MC2a and MC2b.

  The marks MC1a and MC1b are provided on the upper surface of the face CP1 in the face-up state (the surface opposite to the surface on the temporary substrate WT1 side). However, the present invention is not limited to this, and the marks MC1a and MC1b may be provided on the lower surface (surface on the temporary substrate WT1 side) of the chip CP1 in the face-up state, or inside the chip CP1. It may be provided embedded.

  In this embodiment, each chip CPi of the i-th layer (i = 1, 2,...) Has the same mark MC1 (MC1a, MC1b) at the same reference position in each chip CPi. (See FIG. 23, FIG. 27, FIG. 33, etc.). Further, the plurality of temporary substrates WTi have marks MC2 (MC2a, MC2b) corresponding to the chips CPi in the i-th layer at the same reference positions (see FIGS. 21 and 32). That is, the plurality of temporary substrates WTi are substrates on which the same plurality of marks MC2 are respectively attached to the same plurality of positions. In addition, here, a case where each temporary substrate WTi is physically different from each other is illustrated, but the present invention is not limited to this, and each temporary substrate WTi may be physically the same substrate. . In other words, one substrate may be used as each temporary substrate WTi.

<1-6. Substrate position adjustment mark MW>
As will be described later, in this embodiment (see Steps S13 and S23), both the substrates WA and WTi are positioned in the horizontal direction using the alignment marks MW1 and MW2. The alignment marks MW1 and MW2 are marks for adjusting the relative positions of the substrates WA and WTi, and are also referred to as substrate position adjustment marks.

  The substrate position adjustment marks MW1 and MW2 have different shapes (more specifically, shapes that do not overlap each other), like the above-described chip position adjustment marks MC1 and MC2. For example, a circular shape having a relatively large diameter is used as the mark MW1 (specifically, the marks MW1a and MW1b), and the mark MW2 (specifically, the marks MW2a and MW2b) has a relatively small diameter. A circular shape is used.

  The mark MW1a is provided at a first reference position (planar position) (on the left end side of the substrate WTi in FIG. 29) on the substrate WA, and the mark MW1b is a second reference position (planar position) on the substrate WA (in FIG. 29). It is provided on the right end side of the substrate WTi.

  The mark MW2a is provided on the temporary substrate WTi at a regular position (planar position) corresponding to the first reference position of the substrate WA (on the left end side of the substrate WTi in FIG. 29). The mark MW2b is provided on the temporary substrate WTi at a regular position (planar position) corresponding to the second reference position on the substrate WA (on the right end side of the substrate WTi in FIG. 29). In short, the mark MW2a is provided at a position corresponding to the mark MW1a, and the mark MW2b is provided at a position corresponding to the mark MW1b. In order to satisfactorily adjust the relative angle between the two substrates WA and WTi, the marks MW1a and MW1b are preferably provided at positions separated from each other (for example, near both ends of the substrate WA). The same applies to the marks MW2a and MW2b.

  The marks MW1a and MW1b are provided on the upper surface (surface on which each chip is fixed) of the substrate WA in the face-up state. The marks MW2a and MW2b are provided on the lower surface of the temporary substrate WTi in the face-down state (the surface on which each chip is temporarily fixed). However, the present invention is not limited to this, and each mark (MC1a, MC1b), (MW1a, MW1b) may be provided on the opposite side surface, or may be provided embedded in each substrate WA, WTi. May be.

  In this embodiment, the plurality of temporary substrates WTi have the marks MW2 (MW2a and MW2b) at the same reference position. That is, the plurality of temporary substrates WTi are the same substrates also in the sense that the same mark MW2 is attached at the same position.

<1-7. Operation details>
Next, the chip mounting operation (electronic component mounting operation) in this embodiment will be described in detail with reference to the flowcharts of FIGS. Here, a case where a plurality of chips are stacked in three layers is illustrated. However, the present invention is not limited to this, and it may be laminated in two layers, or may be laminated in four or more layers.

<1-7-1. First layer chip stacking process>
First, the first layer chip stacking operation (step S10) (see FIGS. 18 and 19) is performed as follows.

<Step S11: Preparation Step>
Specifically, first, in step S11 (FIG. 19), the resin layer RS1 is formed on the substrate WT1 (FIG. 21) which is a temporary substrate (FIG. 22). Note that marks MC2 and MW2 are preliminarily attached to the temporary substrate WT1 before the resin layer RS1 is formed. This resin layer RSi transmits light (infrared light or the like).

  Specifically, for example, a liquid thermoplastic resin (thermoplastic adhesive or the like) is applied onto the substrate WT1 by the spin coater 80, whereby the resin layer RS1 is formed on the substrate WT1. By forming the resin layer using the spin coating method, the resin layer can be formed very easily. However, the present invention is not limited to this, and the resin layer RS1 may be formed on the substrate WT1 by pasting a resin sheet on the substrate WT1. Also by this, a resin layer can be formed very easily.

  The temporary substrate WT1 on which the resin layer RS1 is formed is transferred to the COW bonding apparatus 30 by the transfer robot 71. The temporary substrate WT1 is placed on the stage 31 in the COW bonding apparatus 30 and held on the stage 31 (see FIGS. 1 and 2).

<Step S12: COW process>
Next, in step S12, the plurality of chips CP1 of the first layer are arranged in a plane on the resin layer RS1 in a face-up state and temporarily fixed (see FIGS. 23 to 27, etc.). Here, the “face-up state” of each chip CP is a state in which the bonding surface of each chip CP (for example, the surface to which the solder bumps BU are attached) faces upward. Hereinafter, step S12 will be described with reference to the timing chart of FIG.

  First, the stage 31 (specifically, the substrate holding portion 315 (see FIGS. 6 and 7) that holds the substrate WT moves in the X direction and / or the Y direction, and the bonding target portion on the bonding surface of the substrate WT is It moves to a position facing the head portion 33H (that is, a position facing the chip CP held by the head portion 33H) (time T10 to T11).

  Further, in parallel with the movement operation of the substrate WT, the transfer operation of the chip CP to the position directly below the head portion 33H is executed. Specifically, as described above, after the chip CP supplied from the chip supply device 10 is received at the position PG3 (reception position PR1) (see FIGS. 2 and 15), the chip transport unit 39 is moved to the central axis AX. The chip CP is transported to a position PG5 immediately below the head portion 33H of the bonding portion 33 by the rotation operation. More specifically, as described above, in the moving operation for each angle β, the angle β is moved from the position PR9 (see FIG. 15) (the rotational position before the angle β with respect to the delivery position PR2 (see FIG. 16)) ( From time T10 to time T12 (see FIG. 17)), the chip CP is transported to a position PG5 (delivery position PR2) immediately below the head portion 33H of the bonding portion 33.

  The head portion 33H is slightly lowered to the vicinity of the mounting position PG5 of the chip CP (time T12 to time T13), receives the chip CP from the chip transport portion 39, and receives the chip at the tip (lower end) of the head portion 33H. CP is adsorbed (time T13 to time T14), and again rises to the original position in the Z direction (reference position) (time T14 to time T15). Thereafter, the chip transport unit 39 rotates by a predetermined angle (time T15 to time T19) in order to avoid interference with the head unit 33H.

  In this state, the chip CP held by the head portion 33H is arranged at a predetermined bonding position (X, Y) in a plane (horizontal plane (XY plane)) parallel to the substrate WTi. However, some position errors still exist. In addition, the chip CP is disposed close to the substrate WTi in the Z direction. The separation distance between the chip CP and the substrate WTi is, for example, about several millimeters.

  Thereafter, the head portion 33H is lowered in a state where the head portion 33H and the chip transport portion 39 do not interfere with each other, and the chip CP attracted and held by the head portion 33H is lowered to the position PG7 (FIG. 2) (time T19 to time). T23). As a result, the chip CP adsorbed at the tip of the head portion 33H is placed at a predetermined plane position on the temporary substrate WT1 on the stage 31.

  In this descending period (time T19 to time T23), the chip CP (CP1) is positioned more accurately and mounted on the temporary substrate WT1 as described below using the alignment marks MC1 and MC2 (see FIG. 23). Placed.

  As described above, the COW bonding apparatus 30 includes the position recognition unit (also referred to as a position measurement unit) 46. The position recognition unit 46 is a processing unit that recognizes the relative position (specifically, X, Y, θ) between the chip CP and the substrate WTi in the horizontal direction.

  The positioning operation (alignment operation) between each chip CP and the temporary substrate WTi is performed by the position recognition unit 46 in two sets of marks (MC1a, MC2a), (MC1b, MC2b) attached to each chip CP and the temporary substrate WTi. ) Is executed by recognizing the position. This alignment operation is executed during a part of the descending period (for example, time T21 to time T22). In particular, the alignment operation is performed in a state where the chip CP and the substrate WTi (specifically, the resin layer RSi thereof) are very close to each other (the distance between the two is, for example, several tens of micrometers to several micrometers). It is preferable.

  As shown in FIG. 23, the position recognizing unit 46 has the light sources (emissions) of the imaging units 35a and 35b having the coaxial illumination system in a state where each chip CP (CP1) held by the head unit 33H faces the temporary substrate WT1. The position of the chip CP on the substrate WT1 is recognized using image data relating to the reflected light of illumination light (here, infrared light) emitted from the substrate WT1. Note that FIG. 23 conceptually shows that the imaging units 35a and 35b photograph the chip or the like from above the chip CP on the upper side of the substrate WTi. Here, the optical axes of the imaging units 35a and 35b are shown to be arranged in the vertical direction. However, as described above, there is actually a mirror 337 that is an optical path changing member, and the imaging units 35a and 35b are arranged. The optical axis CX of 35b is arranged in the horizontal direction.

  As shown also in FIG. 11, the light emitted from the light source of the imaging unit 35a is reflected by the mirror 337, and then the hollow portion 415 of the head portion 33H, the chip tool 411 made of silicon (Si), the chip (silicon chip). ) It penetrates CP and resin layer RSi. On the other hand, the light is reflected by the marks MC1a and MC2a, and the reflected light is received by the imaging device of the imaging unit 35a along a reverse path. Thereby, an image including an optical image (optical image by infrared light (reflected light) of each mark portion) regarding each chip and the substrate WTi is acquired as image data Ga. That is, a captured image Ga obtained by simultaneously reading the two types of marks MC1a and MC2a is acquired. The position recognizing unit 46 recognizes the position of a certain set of marks (MC1a, MC2a) attached to each chip and the substrate WTi based on the captured image Ga, and also detects the position of the set of marks MC1a, MC2a. A positional shift amount (Δxa, Δya) between them is obtained (see FIG. 10).

  Similarly, after the light emitted from the light source of the imaging unit 35b is reflected by the mirror 337, the hollow part 416 of the head part 33H, the chip tool 411 made of silicon (Si), the chip (silicon chip) CP, and the resin layer Transmits RSi and the like. On the other hand, the light is reflected by the marks MC1b and MC2b, and the reflected light is received by the imaging element of the imaging unit 35b along a reverse path. Thereby, an image including an optical image (optical image by infrared light (reflected light) of each mark portion) regarding each chip and the substrate WTi is acquired as the image data Gb. That is, a captured image Gb obtained by simultaneously reading the two types of marks MC1b and MC2b is acquired. The position recognizing unit 46 recognizes the position of a certain set of marks (MC1b, MC2b) attached to each chip and the substrate WTi based on the captured image Gb, and the position of the set of marks MC1b, MC2b. A positional shift amount (Δxb, Δyb) between them is obtained.

  The position recognition unit 46, based on the positional deviation amounts (Δxa, Δya), (Δxb, Δyb) of these two sets of marks, each chip CP and the temporary substrate WT in the horizontal direction (X direction, Y direction, and θ direction). Relative positional deviation amounts (Δx, Δy, Δθ) are calculated. Here, the value Δx is the relative positional deviation between the two CPs and WT in the X direction, and the value Δy is the relative positional deviation between the two CPs and WT in the Y direction. Further, the value Δθ is a relative positional shift (also referred to as a relative posture error) of both CP and WT in the θ direction (rotation direction). The relative positional deviation amounts (Δx, Δy, Δθ) between the two CPs and WT are also expressed as relative positional errors between the two CPs and WT.

  The stage 31 is driven in two translation directions (X direction and Y direction) (translation drive) and rotated in the θ direction so that the relative shift amount recognized by the position recognition unit 46 is reduced. The part 36 and the bonding part 33 are driven (rotated) in the θ direction. As a result, the temporary substrate WTi and the chip CP are relatively moved, and the above-described positional deviation amount is corrected.

  In this way, the alignment operation of the chip CP1 (with respect to the X direction, the Y direction, and the θ direction) is performed.

  Thereafter, the head portion 33H holding one chip CP1 of the first layer is further lowered, and the chip CP1 is placed at a predetermined horizontal position of the resin layer RS of the temporary substrate WT1 (time T23 to T26 in FIG. 17). (See also FIG. 24).

  In this way, the position recognition operation (position displacement measurement operation) and the alignment driving operation (position displacement correction operation) are performed on the chip CP1 and the substrate WT, and the chip CP1 is positioned with respect to the temporary substrate WT1. To be placed.

  Further, the mounting operation of the second and subsequent chips of the first layer is performed in the same manner (FIGS. 25 and 26). Thereby, as shown in FIG. 27, the plurality of chips CP1 of the first layer are positioned and arranged at predetermined plane positions on the temporary substrate WT1. As described above, by using the two types of marks MC1 and MC2, each of the plurality of chips CP1 in the first layer is positioned in a direction (X, Y, θ) parallel to the substrate plane (main plane) of the temporary substrate WT1. Then, each of the plurality of chips CP1 in the first layer is placed on the resin layer RS1 on the temporary substrate WT1.

  Here, when a thermoplastic resin is used as the resin layer RS, for example, the thermoplastic resin is reduced to a temperature T2 (for example, 150 ° C.) lower than a temperature T1 (for example, 200 ° C.) at which the resin layer RS is completely fluidized ( Each chip is placed in a state in which the resin is softened (semi-cured) by heating (using an infrared irradiation unit 318 or the like). The temperature T2 is preferably lower than the melting point of the solder so that the solder bumps of each chip do not melt. Thereafter, the resin layer RS1 is cured by cooling the resin layer RS1 (such as cooling by stopping the heating of the infrared irradiation unit 318 and / or the head unit 33H). Thereby, each chip is temporarily fixed to the resin layer RS1.

<Step S13: WOW process>
Thereafter, the process of step S13 is executed.

  In step S13, first, the substrate WT1 is held by the transfer robot 71. The transfer robot 71 turns the substrate WT1 upside down and transfers the substrate WT1 to the WOW bonding apparatus 50 (see FIG. 28). Then, the inverted substrate WT1 is held on the upper stage 53 of the WOW bonding apparatus 50 (see FIG. 29). At this time, the plurality of chips CP1 temporarily fixed to the substrate WT1 are held in a face-down state.

  On the other hand, the substrate WA transferred by the transfer robot 71 is held in advance on the lower stage 51 of the WOW bonding apparatus 50.

  In the WOW bonding apparatus 50, both the substrates WA and WT1 are held with their bonding surfaces facing each other.

  Next, using the alignment marks MW1 and MW2, both the substrates WA and WT1 are positioned as described below.

  As described above, the WOW bonding apparatus 50 includes the position recognition unit (also referred to as a position measurement unit) 56. The position recognition unit 56 is a processing unit that recognizes the relative position (specifically, X, Y, θ) between the substrate WA and the substrate WTi in the horizontal direction.

  The positioning operation (alignment operation) between the substrate WA and the temporary substrate WTi (here, WT1) is performed by the position recognition unit 56 with two sets of marks (MW1a, MW2a), ( It is executed by recognizing the position of MW1b, MW2b).

  As shown in FIG. 29, the position recognizing unit 56 includes the imaging units 55a and 55b having a coaxial illumination system in a state where the substrate WA held by the lower stage 51 and the substrate WT1 held by the upper stage 53 face each other. The positions of the substrates WA and WTi are recognized using image data relating to the reflected light of illumination light (here, infrared light) emitted from a light source (also referred to as an emission unit).

  Specifically, light (infrared light) emitted from the light source of the imaging unit 55a passes through the hollow portion of the lower stage 51, the silicon substrate WA, the resin layer RS, and the like. On the other hand, the light is reflected by the marks MW1a and MW2a, and the reflected light is received by the imaging element of the imaging unit 55a. Thereby, an image including a light image (light image by infrared light (reflected light)) regarding each mark (MW1a, MW2a) portion on both substrates WA, WTi is acquired as image data Gc. That is, the captured image Gc obtained by simultaneously reading the two types of marks MW1a and MW2a is acquired. The position recognizing unit 56 recognizes the position of a certain set of marks (MW1a, MW2a) attached to both the substrates WA, WTi based on the captured image Gc, and the pair of marks MW1a, MW2a. The amount of misalignment (Δxc, Δyc) is obtained.

  Similarly, light (infrared light) emitted from the light source of the imaging unit 55a passes through the hollow portion of the lower stage 51, the silicon substrate WA, the resin layer RS, and the like. On the other hand, the light is reflected by the marks MW1b and MW2b, and the reflected light is received by the imaging element of the imaging unit 55b. Thereby, an image including a light image (light image by infrared light (reflected light)) regarding each mark (MW1b, MW2b) portion on both substrates WA, WTi is acquired as image data Gd. That is, the captured image Gd obtained by simultaneously reading the two types of marks MW1b and MW2b is acquired. The position recognizing unit 56 recognizes the position of a certain set of marks (MW1b, MW2b) attached to both the substrates WA, WTi based on the captured image Gd, and reciprocally connects the one set of marks MW1b, MW2b. A positional deviation amount (Δxd, Δyd) is obtained.

  The imaging units 55a and 55b are movable in the X direction, the Y direction, and the Z direction, respectively, and can be adjusted by changing the imaging range.

  Thereafter, the position recognizing unit 56 uses the substrate WA and the temporary substrate in the horizontal direction (X direction, Y direction, and θ direction) based on the positional deviation amounts (Δxc, Δyc), (Δxd, Δyd) of these two sets of marks. A relative positional deviation amount (Δx, Δy, Δθ) with respect to WTi is calculated.

  Then, the lower stage 51 is appropriately driven in two translational directions (X direction and Y direction) and a rotational direction (θ direction) so that the relative shift amount recognized by the position recognition unit 56 is reduced. The Thereby, both the substrate WA and the temporary substrate WTi are relatively moved, and the relative positional deviation amount between the two is corrected.

  In this way, the alignment operation of the substrates WA and WTi (with respect to the X direction, the Y direction, and the θ direction) is executed.

  Thereafter, the upper stage 53 is further lowered, the substrate WA and the substrate WTi relatively approach each other, and the plurality of chips CPi (here CP1) held in the face-down state on the temporary substrate WTi and the substrate WA are relatively To approach. In accordance with this approaching operation, the plurality of chips CPi in the face-down state are respectively placed at predetermined horizontal positions on the substrate WA (see FIG. 30). The “face-down state” of the chip CPi is a state in which the bonding surface of the temporary substrate WTi on which each chip CPi is temporarily fixed (for example, the surface on which the chip CPi is temporarily fixed) faces downward. It is also expressed that the temporary substrate WTi is in a face-down state.

  At this time, in order to make sure that the plurality of chips CPi temporarily fixed to the temporary substrate WTi are brought into contact with the substrate WA, a process (pressurizing process) is performed to apply a predetermined pressure between the chip CPi and the substrate WA. It is preferable.

  Thereafter, the substrate WA is heated by the heater built in the lower stage 51, and the substrate WTi is heated by the heater built in the upper stage 53. As a result, the solder bump BU of each chip CP1 is melted, and a plurality of chips CPi are bonded onto the substrate WA.

  Here, as described above, the chip CPi is accurately positioned on the substrate WTi using the marks MC1 and MC2 (step S12), and the substrate WA and the substrate WTi are accurately positioned using the marks MW1 and MW2. Positioning has been performed (step S13). Therefore, the plurality of chips CPi in the face-down state are accurately positioned and bonded to predetermined horizontal positions of the substrate WA.

<Step S14: Debonding process>
Next, in step S14, the “debonding process” is executed. Specifically, the substrate WT1 is separated from the plurality of chips CP1 while maintaining the state where the plurality of chips CP1 are respectively mounted (bonded) at predetermined positions on the substrate WA.

  More specifically, the resin layer RS1 is heated to a predetermined temperature T4 by a heater built in the upper stage 53. Then, in such a heating state, by raising the upper stage 53 while holding the temporary substrate WT1, the temporary substrate WT1 having the resin layer RS1 is peeled from the plurality of chips CP1 (see FIG. 31). FIG. 31 schematically shows the temporary substrate WT1 being peeled from the chip CP1.

  In order to prevent dripping of the thermoplastic resin in the resin layer RS1, the temperature T4 is not high enough to completely fluidize the resin layer RS1, but a temperature at which the resin layer RS1 is semi-cured (for example, 180 ° C.). It is preferable that In order to prevent the solder bump of each chip CP1 bonded to the substrate WA from being melted again, the temperature T4 is preferably lower than the melting point of the solder.

  As described above, the plurality of chips CP1 of the first layer are bonded to the predetermined position of the substrate WA in a state of being planarly arranged on the substrate WA (step S10).

<1-7-2. Second layer chip stacking process>
Next, the second layer chip stacking operation (step S20) (see FIG. 18 and FIG. 20) is performed as follows. As described above, the corresponding processes in steps S21 to S24 related to the second layer are the same processes as the processes in steps S11 to S14 related to the first layer. However, while the first layer chip CPi is directly placed on the substrate WA in steps S13 and S14, the i th in steps S23 and S24 related to the i th layer (here i = 2). The chip CPi of the layer is mounted on the chip CPi of the (i-1) th layer that has already been stacked.

  First, in step S21, the resin layer RS2 is formed on the substrate WT2 which is a temporary substrate (see FIG. 32). Specifically, resin layer RS2 is formed on temporary substrate WT2 using spin coater 80 or the like. The temporary substrate WT2 on which the resin layer RS2 is formed is placed on the stage 31 in the COW bonding apparatus 30 by the transfer robot 71 and held on the stage 31 (see FIGS. 1 and 2).

  In the next step S22, the plurality of chips CP2 in the second layer are arranged in a plane on the resin layer RS2 on the substrate WT2 in a face-up state and temporarily fixed (see FIG. 33).

  Specifically, each chip CPi (CP2 in this case) cut out from the substrate WC by the chip supply device 10 (FIG. 2) is supplied to the COW bonding device 30 by the protruding portion 11 of the chip supply device 10, the chip transfer device 13, and the like. Is transferred to the chip transfer section 39. The chip transport unit 39 transports the chip CP received at the position PG3 to a position PG5 directly below the head unit 33H of the bonding unit 33. In a state where the head unit 33H and the chip transport unit 39 do not interfere with each other, the head unit 33H is lowered, and the chip CP attracted and held by the head unit 33H is lowered from the position PG5 to the position PG7. As a result, the chip CP adsorbed at the tip of the head portion 33H is placed at a predetermined plane position on the temporary substrate WT1 on the stage 31.

  Also in step S22, as in step S12, each chip CP (CP2) is positioned and placed on the temporary substrate WT2 using the alignment marks MC1 and MC2 provided for each chip CP.

  Further, in step S23, first, the temporary substrate WT2 is held by the transfer robot 71. The transfer robot 71 turns the temporary substrate WT2 upside down and transfers the temporary substrate WT2 to the WOW bonding apparatus 50 (see FIG. 34). Then, the temporary substrate WT2 after being turned upside down is held on the upper stage 53 of the WOW bonding apparatus 50 (see FIG. 35). At this time, the plurality of chips CP2 temporarily fixed to the temporary substrate WT2 are held in a face-down state.

  On the other hand, the lower stage 51 of the WOW bonding apparatus 50 holds the substrate WA that has been subjected to the processing of step S10.

  Also in step S23, in the same manner as in step S13, the relative positions in the horizontal direction of both the substrates WA and WT2 are adjusted using the alignment marks MW1 and MW2 with the temporary substrate WT2 and the substrate WA facing each other.

  Thereafter, the upper stage 53 is further lowered to bring the temporary substrate WT2 and the substrate WA facing each other relatively close to each other, whereby the plurality of chips CP2 in the second layer in the face-down state and the first layer on the substrate WA The plurality of chips CP1 are relatively approached (see FIG. 35). Then, the plurality of i-th layer chips CPi (CP2) in the face-down state are placed and bonded at predetermined positions on the (i-1) -th layer chip CPi (CP1) already stacked on the substrate WA. (See FIG. 36).

  In this way, the substrate WA and the temporary substrate WT2 are positioned in the horizontal direction using the substrate position adjustment mark MW1 on the substrate WA and the substrate position adjustment mark MW2 on the temporary substrate WT2. As a result, the positional relationship between each of the plurality of first layer chips CP1 held on the substrate WA and each of the plurality of second layer chips CP2 held on the substrate WT2 is adjusted, and each chip CP1 is adjusted. And the corresponding chips CP2 are respectively joined.

  Here, each chip CP2 of the second layer is accurately positioned on the substrate WT2 using the marks MC1 and MC2 (step S22), and the substrate WA and the substrate WT2 are accurately positioned using the marks MW1 and MW2. (Step S23). Therefore, each chip CP2 of the second layer in the face-down state is accurately positioned and bonded to a predetermined horizontal position on the substrate WA (specifically, on each chip CP1 of the first layer of the substrate WA).

  Thereafter, in step S24, the substrate WT2 is separated from the plurality of chips CP2 in the second layer while maintaining the state in which the plurality of chips CP2 in the second layer are respectively joined to the plurality of chips CP1 in the first layer. More specifically, the temporary substrate WT2 having the resin layer RS2 is peeled from the plurality of chips CP2 by raising the upper stage 53 while holding the temporary substrate WT2 while the resin layer RS2 is heated to the temperature T4. (See FIG. 37). FIG. 37 schematically shows the temporary substrate WT2 being peeled from the chip CP2.

  As described above, the plurality of chips CP2 of the second layer are further laminated and bonded onto the plurality of chips CP1 of the first layer bonded onto the substrate WA.

  If it is determined in step S30 (FIG. 18) that the process has not yet been completed, the process returns to step S20 again. Then, in the same manner as the second layer stacking operation, the third layer and subsequent chip stacking operations are executed. If it is determined that the final layer chip stacking operation has been completed (YES in step S30), this process ends.

  For example, the stacking operation of the third-layer chip CP3 is performed as follows.

  First, in step S21, the resin layer RS3 is formed on the temporary substrate WT3, and in step S22, the plurality of chips CP3 of the third layer are temporarily arranged and fixed on the resin layer RS3 in a face-up state.

  Next, in step S23, the temporary substrate WT3 is turned upside down, and the plurality of chips CP3 in the third layer are held in the temporary substrate WT3 in a face-down state, and the substrate WA and the temporary substrate WT3 facing each other are relatively close to each other. To do. Accordingly, the plurality of chips CP3 in the third layer in the face-down state and the plurality of chips CP2 in the second layer on the substrate WA relatively approach each other, and the plurality of chips CP2 in the second layer and the third layer The plurality of chips CP3 are joined to each other.

  Then, in step S24, the temporary substrate WT3 is separated from the plurality of chips CP3 in the third layer while maintaining the state in which the plurality of chips CP3 in the third layer are respectively joined to the plurality of chips CP2 in the second layer. .

  In this way, the plurality of chips CP3 in the third layer are further stacked on the plurality of chips CP1 in the first layer and the plurality of chips CP2 in the second layer stacked on the substrate WA.

<1-8. Effects of the embodiment>
According to the above-described aspect, in steps S12 and S22, the chip CP is disposed to face the mounting surface of the substrate WTi and is disposed at a predetermined bonding position (X, Y) in the horizontal plane (XY plane). Thus, the relative position error (Δx, Δy, Δθ) of the two objects is measured by measuring the position of the chip CP from the outside of the opposite objects CP, WT (specifically, the upper surface side of the chip CP). Is measured. The upper surface of the chip CP may be one of two opposite surfaces (outer surfaces) that are opposite to the opposing surfaces (inner surfaces) of the objects CP and WT. Expressed.

  Therefore, compared with the technique described in Patent Document 1 described above, the time for inserting and removing the two-field camera is unnecessary, so that the speed can be increased.

  49 is a timing chart showing an operation according to a comparative example (a technique similar to the technique described in Patent Document 1) involving insertion and removal of the two-field camera. In this comparative example, first, in a state where the chip CP and the substrate WT are very far apart in the Z direction, the two-field camera moves and the two-field camera is inserted between the chip CP and the substrate WT. (Time T19 to Time T31). Then, two captured images relating to the first set of marks (MC1a, MC2a) are taken (time T31 to T32), and then the two-field camera is further moved so that two related to the second set of marks (MC1b, MC2b) are obtained. A captured image is captured (time T33 to T34). Further, based on the relative position error calculated based on these captured images, the chip CP and the substrate WT are relatively driven to reduce the position error, and the two-field camera is retracted (time T40). In such a comparative example, in the period from time T19 to time T40, it takes time to insert and remove the two-field camera (for example, about 1 second to 2 seconds).

  On the other hand, in the above-described embodiment (see FIG. 17), the period from time T19 to time T40 (see FIG. 49) is unnecessary. Therefore, according to the said embodiment, speeding-up can be achieved compared with the said comparative example. For example, in the comparative example, the mounting time (cycle time) per chip is about 2 to 3 seconds, whereas in the present embodiment, a cycle time of about 1 second can be realized. .

  In the above embodiment, the position measurement operation is performed in a state where the chip CP is disposed at a predetermined bonding position (X, Y) in the horizontal plane (specifically, a state where the chip CP is disposed at a substantially normal bonding position). Is done. According to this, since the movement amount in the XY direction after the position measurement is very small (value close to zero), it is possible to perform an accurate alignment operation (position alignment operation). In particular, the position of the chip CP is measured in a state where the chip CP is far away from a predetermined bonding position, and fine adjustment between the chip position and the substrate position is performed after the chip CP moves to the bonding position based on the position measurement result. It is possible to perform an accurate alignment operation compared to the case where the above is performed.

  Moreover, according to the said embodiment, compared with the technique (and comparative example) of said patent document 1, it does not perform alignment in the state in which the two-field camera was inserted between the chip | tip and the board | substrate. Therefore, the alignment is performed in a state where both the chip and the substrate are relatively close to each other. For example, in the technology according to the comparative example, the distance between the chip CP and the substrate WT is about several tens of millimeters to several hundreds of millimeters, whereas in the above embodiment, the distance between the chip CP and the substrate WT is several. It can be reduced to about millimeters (more preferably about tens of micrometers or less). Therefore, since the movement distance in the Z direction after the position measurement is reduced, the positioning accuracy of the relative positions of both can be improved. For example, while the positioning accuracy in the comparative example is about 2 micrometers, in this embodiment, it is possible to achieve a positioning accuracy of about 0.2 micrometers. In this way, it is possible to align the two with higher accuracy.

  In particular, in this embodiment, since both the objects CP and WT are close to each other, the image Ga obtained by simultaneously imaging the marks MC1a and MC2a attached to the objects by the one imaging unit 35a is obtained. It is possible to determine the relative position of the object very accurately. The same applies to the image Gb.

  In addition, two captured images Ga and Gb are simultaneously captured using the two imaging units 35a and 35b. Therefore, it is possible to capture the two captured images Ga and Gb at a higher speed than when moving the single imaging unit to capture the two captured images Ga and Gb. Therefore, the alignment operation can be speeded up.

<2. Second Embodiment>
In the first embodiment, the imaging operation is performed only from one side of the upper surface side of the chip CP (on the opposite surface side of the chip CP) and the lower surface side of the substrate WT (on the opposite surface side of the substrate WT). Although the case where the accompanying position detection operation is executed is illustrated, the present invention is not limited to this. For example, a position detection operation involving an imaging operation from both the upper surface side of the chip CP and the lower surface side of the substrate WTi may be executed. Specifically, the alignment mark MC1 attached to the chip CP is imaged from the upper surface side of the chip CP, and the alignment mark MC2 attached to the substrate WT is imaged from the lower surface side of the substrate WT. The relative position error between CP and WT may be measured.

  Such a mode will be described in the second embodiment. The second embodiment is a modification of the first embodiment, and the following description will focus on the differences.

  FIG. 39 is a cross-sectional view showing the vicinity of the stage 31 of the COW bonding apparatus 30 (30B) according to the second embodiment.

  As shown in FIG. 39, in the COW bonding apparatus 30B, an imaging unit 35c is arranged in addition to the infrared irradiation unit 318b. The imaging unit 35c has an XYθ driving unit and is appropriately moved in the X direction, the Y direction, and the θ direction. In addition, you may make it heat the board | substrate WTi by infrared light irradiation using the infrared light source of the coaxial illumination system of the imaging part 35c, without providing the infrared irradiation part 318b.

  In the second embodiment, the imaging unit 35c is used in the above steps S12, S22 and the like.

  Specifically, in steps S12 and S22, the alignment operation is performed in a state where the chip CP is disposed opposite to the mounting surface of the substrate WTi and is disposed at a predetermined bonding position (X, Y) in the horizontal plane (XY plane). Is executed. This alignment operation is executed here during a part of the descent period (time T19 to time T23 (see FIG. 17)) of the head portion 33H (for example, time T21 to time T22), as in the first embodiment. Is done. Note that the imaging operation by the upper two imaging units 35a and 35b and the imaging operation by the lower one imaging unit 35c are executed in parallel (simultaneously) in the same period (for example, time T21 to time T22).

  Specifically, two captured images including one of each of the marks MC1a and MC1b on the chip CP are simultaneously captured from the upper surface side of the chip CP by the two imaging units 35a and 35b. Specifically, a captured image including the mark MC1a is captured by the imaging unit 35a, and a captured image including the mark MC1b is captured by the imaging unit 35b. Then, the positions of the marks MC1a and MC1b are calculated based on the positions of the imaging units 35a and 35b in each coordinate system (each captured image coordinate system).

  In the second embodiment, a captured image relating to only one of the marks MC2a and MC2b (for example, the mark MC2a) on the substrate WTi is acquired from the lower surface side of the substrate WTi by the imaging unit 35c, and the captured image is used. Thus, the position of the one mark (MC2a) is obtained. More specifically, the light emitted from the light source of the imaging unit 35c is reflected by the mark MC2 (MC2a), and the reflected light is received by the imaging element of the imaging unit 35c. Thereby, an image including a light image relating to the substrate WT (light image of infrared light (reflected light) of each mark portion) is acquired. Then, the position of the mark MC2a is calculated based on the position of the imaging unit 35c in the coordinate system (captured image coordinate system).

  Further, here, assuming that no change in positional deviation in the θ direction occurs during the period in which the plurality of chips CP are arranged on the substrate WTi, only one of the two marks MC2a and MC2b (for example, only the mark MC2a) is used. Actual measurement is performed for each chip CP. That is, the position of the other of the two marks MC2a and MC2b (for example, the mark MC2b) is not actually measured.

  According to such an aspect (second embodiment), since it is not necessary to move the imaging unit 35c, it is possible to increase the speed as in the first embodiment compared to the following comparative example. Is possible. The technique according to the comparative example performs imaging of the mark MC2a and imaging of the mark MC2b at different times with the movement of the imaging unit 35c in the X direction and the Y direction, and uses the two captured images on the substrate WTi. This is a technique for measuring the positions of the marks MC2a and MC2b.

  Here, in the position measurement period regarding the plurality of chips CP, it is assumed that the θ position change of the substrate WTi is very small and the θ position of the substrate WTi does not change. A measurement result at a certain time (the θ position of the substrate WTi) can be used in common for a plurality of chips CP.

  Specifically, the θ position (attitude angle θ) of the substrate WTi at a predetermined time (reference time) before placing the first chip CP on the substrate WTi is measured once in advance. The orientation angle θ of the substrate WTi at the reference time point is two captured images obtained by sequentially imaging each of two alignment marks (for example, MW2a and MW2b (see FIG. 21)) provided on the substrate WTi by the imaging unit 35c. Based on.

  This measurement result (the orientation angle θ of the substrate WTi at the reference time) is used in common for the plurality of chips CP. Specifically, both objects are based on the attitude angle θ of the substrate WTi at the reference time point and the three captured images Ga, Gb, Gc when each of the plurality of chips CP is disposed at the bonding position of the substrate WT. Relative position errors (Δx, Δy, Δθ) are calculated. The captured image Ga is an image related to the mark MC1a of each chip CP, the captured image Gb is an image related to the mark MC1b of each chip CP, and the captured image Gc is an image related to the mark MC2 (MC2a) of the substrate WTi.

  More specifically, for example, first, the position of the mark MC2b is calculated based on the position of the mark MC2a and the posture angle θ of the substrate WTi at the reference time point. Based on the positions of the four marks MC1a, MC1b, MC2a, MC2b, the relative position errors (Δx, Δy, Δθ) of both objects are calculated. Specifically, in the same manner as in the first embodiment, the position recognizing unit 46 determines the amount of positional deviation (Δxa, Δya) between the marks MC1a and MC2a and the amount of positional deviation (Δxb) between the marks MC1b and MC2b. , Δyb), and the relative displacement (Δx, Δy, Δθ) between each chip CP and the temporary substrate WTi is calculated. It is assumed that the relationship between each coordinate system (each captured image coordinate system) of the imaging units 35a, 35b, and 35c is accurately grasped by prior calibration.

  Such an operation is similarly executed for a plurality of chips CP. Specifically, two photographed images including one of each of the marks MC1a and MC1b on each chip CP are simultaneously photographed by the two imaging units 35a and 35b from the upper surface side of each chip CP, and the lower surface side of each chip CP. A captured image including the mark MC2a on the substrate WT (mark MC2a corresponding to each chip CP) is also captured at the same time by the imaging unit 35c. According to this, the position (X, Y) of the substrate WTi and the position (X, Y, θ) of each chip CP at the time of mounting each chip CP are accurately grasped. Then, by using the posture angle θ of the substrate WTi at the reference time point, the relative positional relationship between each chip CP and the substrate WTi at the time of mounting each chip CP can be accurately grasped.

  According to the operation as described above, in steps S12 and S22, the chip CP is placed opposite to the substrate WTi and at the predetermined bonding position (X, Y) in the horizontal plane (XY plane). From the outside of the objects CP and WT, the position of the chip CP and the position of the substrate WT are measured. Specifically, the position of the chip CP is measured from the upper surface side of the chip CP, and the position of the substrate WTi is measured from the lower surface side of the substrate WTi. Based on these measurement results, the relative position errors (Δx, Δy, Δθ) of the two objects (chip CP and substrate WT) are measured. Note that the lower surface of the substrate WT is also expressed as one surface of two opposite surfaces that are surfaces opposite to the surfaces facing both the objects CP and WT.

  According to the second embodiment, it is possible to increase the speed as in the first embodiment.

  Further, according to the second embodiment, it is possible to achieve the same high precision as in the first embodiment. However, in the second embodiment, the upper imaging units 35a and 35b and the lower imaging unit 35c are provided, and in the case where the temperatures of the two are different, the degree of thermal deformation is determined by the upper imaging unit. 35a and 35b and the lower imaging unit 35c may be different from each other. At that time, a relative position change due to heat occurs between the upper imaging units 35a and 35b and the lower imaging unit 35c, and the measurement accuracy slightly decreases. Therefore, from such a viewpoint, it is preferable to employ the first embodiment rather than the second embodiment.

  In addition, in this 2nd Embodiment, although the case where the single imaging part 35c is provided in the lower side is illustrated, it is not limited to this. For example, two imaging units 35c and 35d are provided on the lower side of the substrate WT, and the captured image related to the mark MC2a and the captured image related to the mark MC2b are captured simultaneously using the two imaging units 35c and 35d. It may be.

<3. Third Embodiment>
The third embodiment is a modification of the second embodiment. Below, it demonstrates centering on difference with 2nd Embodiment.

  In the second embodiment, as in the first embodiment, the case where the alignment operation is performed in the lowering period of the head portion 33H (for example, time T21 to time T22 (see FIG. 17)) is exemplified. It is not limited to this. For example, the alignment operation may be performed in parallel with the chip CP transfer operation or the like between the bonding unit 33 (head unit 33H) and the chip transport unit 39. More specifically, the alignment operation may be performed during the retreat period of the chip transport unit 39 (specifically, the period until the retreat completion time T19). In the third embodiment, such an aspect will be described.

  FIG. 40 is a timing chart showing an alignment operation in the COW bonding apparatus 30 (30C) according to the third embodiment. The COW bonding apparatus 30 (30C) according to the third embodiment has the same configuration as the COW bonding apparatus 30 (30B) according to the second embodiment.

  As shown in FIG. 40, in the third embodiment, first, in the same manner as described above, the stage 31 moves in the X direction and / or the Y direction, and the bonding target portion of the substrate WT becomes the head portion 33H. It moves to the facing position (bonding position) of the chip CP to be held (time T10 to T11).

  Similarly to the above, the plate portion 391 of the chip transport portion 39 rotates around the central axis AX by an angle β from the position PR9 (see FIG. 15) (time T10 to time T12). The chip CP is transported to a position PG5 (delivery position PR2 (see FIG. 16)) immediately below the head portion 33H of the bonding portion 33.

  Next, the head portion 33H is slightly lowered to the vicinity of the placement position PG5 (see FIG. 2) of the chip CP (time T12 to time T13), receives the chip CP from the chip transport portion 39, and receives the tip of the head portion 33H. The chip CP is adsorbed by the portion (lower end portion) (time T13 to time T14), and again rises to the original Z-direction position (reference position) (time T14 to time T15). Thereby, the suction holding operation (chip receiving operation) of the chip CP by the head portion 33H is completed.

  Thereafter, the chip transport unit 39 rotates by a predetermined angle in order to avoid interference with the head unit 33H (time T15 to time T19). In other words, the plate portion 391 of the chip transport portion 39 is retracted from the bonding position in order to avoid interference with the head portion 33H.

  In the third embodiment, the alignment operation is performed from time T11 to time T19.

  Specifically, during the period from the time when the movement of the substrate WT to the bonding position is completed (time T11) to the time when the retreat completion time T19 of the plate portion 391 is completed (for example, times T11 to T13), the imaging unit 35c is placed on the substrate WT. A photographed image including the alignment mark MC2 (for example, MC2a) is photographed, and the position of the substrate WT (specifically, the position of the corresponding portion to the chip in the substrate WT) is measured. Here, since the imaging unit 35c images the substrate WT from the lower surface side of the substrate WT, whether or not the plate portion 391 exists above the substrate WT (specifically, between the substrate WT and the chip CP). Regardless, the alignment mark MC2 provided on the substrate WT can be imaged.

  In addition, the alignment mark on the chip CP within a period (for example, from time T17 to time T18) from the time point T15 at which the adsorption of the chip CP by the head portion 33H is completed (time point at which chip reception is completed) T15 to the time point T19 at which the plate unit 391 is retracted. Captured images including MC1 (MC1a, MC1b) are captured by the imaging units 35a, 35b, respectively. Then, the position of the chip CP is measured using the captured image.

  Here, since the imaging units 35a and 35b image the chip CP from the upper surface side of the chip CP, is there a plate unit 391 under the chip CP (specifically, between the chip CP and the substrate WT)? Regardless of whether or not, each alignment mark MC1 (MC1a, MC1b) provided on the chip CP can be imaged.

  As in the second embodiment, the relative position errors (Δx, Δy, Δθ) between the chip CP and the substrate WT are calculated based on the measurement results of the alignment marks MC1a, MC1b, MC2a. Further, the chip CP and the substrate WT are driven relatively so as to reduce the relative position error.

  In this way, the operation of imaging the mark MC2 (MC2a) attached to the substrate WT is performed during the period from the time T11 when the movement of the bonding target portion of the substrate WT to the bonding position is completed until the time T19 when the plate portion 391 is retracted. This is performed by the imaging unit 35c (for example, at times T11 to T13). Further, the operation of imaging the mark MC1 related to the chip CP by the imaging units 35a and 35b (mark MC1 imaging operation) and the operation of relatively driving the chip CP and the substrate WT (relative movement operation) are performed by the chip transport unit 39. This is performed in parallel with the chip supply operation (time T10 to time T19) to the head portion 33H. Specifically, the chip position measurement operation and the like are performed in a period immediately after the head unit 33H receives the chip CP from the chip transport unit 39 and the head unit 33H sucks the chip CP (more specifically, the chip transport unit 39 is retracted). It is performed during a part of the periods T15 to T19 (for example, times T17 to T18).

  Thereafter, the head portion 33H is lowered in a state where the head portion 33H and the chip transport portion 39 do not interfere with each other, and the chip CP attracted and held by the head portion 33H is lowered to the position PG7 (time T19 to time T23). As a result, the chip CP adsorbed at the tip of the head portion 33H is placed at a predetermined plane position on the temporary substrate WT1 on the stage 31.

  Further, the mounting operation of the second and subsequent chips of the first layer is performed in the same manner (FIGS. 25 and 26). Thereby, as shown in FIG. 27, the plurality of chips CP1 in the first layer are positioned and arranged at predetermined plane positions on the temporary substrate WTi. As described above, by using the two types of marks MC1 and MC2, each of the plurality of chips CP1 in the first layer is positioned in a direction (X, Y, θ) parallel to the substrate plane (main plane) of the temporary substrate WT1. Then, each of the plurality of chips CP1 in the first layer is placed on the resin layer RS1 on the temporary substrate WT1.

  Further, the chip stacking operation after the second layer is performed in the same manner.

  According to the above aspect, in steps S12 and S22, the chip CP is opposed to the substrate WTi and is disposed at the predetermined bonding position (X, Y) in the horizontal plane (XY plane). The position of the chip CP and the position of the substrate WTi are respectively measured from the outside of both the objects CP and WT. Specifically, the position of the chip CP is measured from the upper surface side of the chip CP, and the position of the substrate WTi is measured from the lower surface side of the substrate WTi. Then, based on these measurement results, the relative position errors (Δx, Δy, Δθ) of the two objects (chip CP and substrate WTi) are measured.

  Therefore, according to the third embodiment, it is possible to achieve the same high accuracy as in the first embodiment.

  Further, according to the third embodiment, it is possible to achieve the same high speed as in the first embodiment. In particular, in the third embodiment, the alignment operation is performed in parallel with the execution period (time T11 to time T19) of the chip CP transfer operation and the like between the bonding unit 33 (head unit 33H) and the chip transport unit 39. And the positioning of the chip CP is completed by the start time T19 of the lowering operation of the head portion 33H. Therefore, the period for aligning the chip CP and the substrate WT (alignment period) includes the chip CP supply operation periods T10 to T19 (including the retreat periods T15 to T19 of the chip transport unit 39) by the chip transport unit 39. Need not be provided separately. Therefore, the operation (bonding operation) of placing the chip CP at a predetermined position on the substrate WT can be further accelerated.

  Here, in the above-described first embodiment, during the alignment operation from time T21 (FIG. 17), a period for temporarily stopping the lowering operation of the bonding portion 33H (lowering stop period) TS (for example, 0.1 second to 0). It is also possible to provide a stop period of about 2 seconds (see also the broken line LD in FIG. 17). For example, when the chip CP and the substrate WT are close to a very small distance (for example, about several tens of micrometers) and an image including an alignment mark is captured, after the imaging operation (and / or the imaging operation) By providing the descent stop period TS in the middle), the position correction operation in the plane parallel to the XY plane may be completed more reliably before the contact between the chip CP and the substrate WT.

  On the other hand, according to the third embodiment, the alignment operation is performed by the start time T19 of the descending operation of the head portion 33H, and after the time T21, the descending stop period TS (for example, 0.1 second to 0.2 second). It is not necessary to provide a stop period of about 2 seconds). Therefore, in particular, compared to the above-described case where the descent stop period TS is provided in the first embodiment (see the broken line LD in FIG. 17), the operation of placing each chip CP at each predetermined position on the substrate WT is performed. Furthermore, the speed can be increased. More specifically, it is possible to realize a cycle time (for example, 0.8 seconds) in which the time corresponding to the descending stop period TS is shortened.

  In the third embodiment, the case where the positioning of the chip CP is completed by the start time T19 of the lowering operation of the head portion 33H is illustrated, but the present invention is not limited to this. For example, the photographing operation of the three marks MC1a, MC1b, and MC2a is completed by the start time T19 of the lowering operation of the head portion 33H, and the relative positions of the chip CP and the substrate WT by the contact time T23 between the chip CP and the substrate WT. The correction driving operation for reducing the error may be completed.

<4. Modified example>
The present invention is not limited to the above-described contents, and various modifications can be made.

<4-1. Alignment operation during contact)>
For example, in each of the above embodiments, the alignment operation between the chip CP and the substrate WT in the COW bonding apparatus 30 is before the contact time T23 between the chip CP and the substrate WT (time T12 to T15, time T19 to T23, etc.). However, the present invention is not limited to this.

  Specifically, the alignment operation (including the imaging operation) is performed while the chip CP and the substrate WT are in contact (bonding periods T23 to T26 after the chip is lowered), in other words, the chip CP is pressed against the resin layer RS. It may be executed after the placement. Specifically, after the chip CP comes into contact with the substrate WT (and preferably before the resin is cured) (for example, times T24 to T25 (FIGS. 17 and 40)), the imaging units 35a and 35b (and 35c). Thus, the relative position error between the chip CP and the substrate WT may be detected, and the relative position between the chip CP and the substrate WT may be adjusted based on the relative position error. In particular, in addition to the alignment operation (the alignment operation before the contact between the chip CP and the substrate WT) in each of the above embodiments, the alignment operation after the contact between the chip CP and the substrate WT is preferably performed. More specifically, the relative position error detection operation and the drive operation for correcting the relative position error are performed before the contact between the two CPs and WT, and then the two contact each other. After the contact, the relative position error detection operation and the drive operation for correcting the relative position error may be further performed. According to this, it is possible to further finely adjust the relative position of both CP and WT after the contact between both CP and WT. Therefore, a more accurate alignment operation (alignment operation) can be performed.

<4-2. Misalignment inspection after contact>
In addition, the relative position error (detection error based on the captured image after contact) detected after the chip CP contacts the substrate WT is not only the position correction operation between the chip CP and the substrate WT, but also the chip CP and the substrate WT. It may be used for the calculation operation of the correction amount (the offset value related to the measurement value) related to the relative position.

  For example, a displacement GP (= E2−E1) between the two relative position errors E1 and E2 before and after the contact is calculated as the offset value ST. Here, the relative position error E1 (Δx, Δy, Δθ) is based on, for example, captured images captured by the imaging units 35a, 35b, and 35c at a time T11 to T19 with respect to a certain chip CP in the third embodiment. Calculated relative position error between a certain chip CP and the substrate WT (error before contact). In addition, the relative position error E2 (Δx, Δy, Δθ) is calculated based on the captured images captured by the imaging units 35a, 35b, and 35c at the times T24 to T25 (see FIG. 40) with respect to the chip CP. This is a relative position error (error after contact) between the chip CP and the substrate WT.

  Then, this offset value ST (deviation amount GP) is used as a correction amount for the relative position error EB (Δx, Δy, Δθ) between another chip CP (the same type of chip as described above) and the substrate WT. You can do it. That is, the offset value ST related to the position measurement result of a certain chip may be reflected as a correction amount for the position measurement result related to another chip. In particular, a more accurate correction amount can be calculated by calculating an average value or the like (statistical processing result) of the deviation amounts GP regarding the plurality of chips CP as the offset value ST.

  More specifically, first, a value GP is obtained for a relatively small number (for example, 10) of chips CP. Specifically, for each chip CP, the difference GP (= E2−) between the measurement error E1 (Δx, Δy, Δθ) at times T11 to T19 and the measurement error E2 (Δx, Δy, Δθ) at times T24 to T25. E1) is obtained respectively. Then, the average value of the ten values GP is determined as the offset value ST.

  Next, for a relatively large number (for example, 1000) of different chips CP, only the relative position error E1 at times T11 to T19 is measured, and the offset value ST is reflected as a correction amount for the value E1. Thus, the relative position error E1 is corrected. For example, when the offset value ST is “+ α”, the relative position error E1 may be corrected by adding “−α” to the value E1. The relative position error E2 only needs to be measured for a relatively small number (for example, 10) of chips CP, and is not measured for a relatively large number of (for example, 1000) other chips CP.

  According to this, since the measurement operation of the relative position error E2 only needs to be performed for a relatively small number of chips, it is possible to increase the speed while suppressing an increase in alignment time.

  Alternatively, the relative position error detected after the chip CP comes into contact with the substrate WT is used for the alignment quality determination processing (alignment failure determination processing) (defective product determination processing in short) of the chip CP portion. It may be.

  Specifically, in the third embodiment, the relative position error (relative position error between the same chip CP and the substrate WT) E2 (Δx, Δy, Δθ) is measured for each chip CP at times T24 to T25. The quality of the alignment may be determined based on whether the position error E2 is within the allowable error range. Specifically, when the relative position error E2 is not within the allowable error range, it may be determined that an alignment failure has occurred.

<4-3. Head>
Further, instead of the head portion 33H (FIG. 11) in each of the above embodiments, a head portion 33Hb as shown in FIG. 41 may be provided.

  The head portion 33Hb has a head main body portion 413b and a glass tip tool 411b. The head main body 413b includes a substantially cylindrical outer peripheral member 414, a coil heater 418 wound around the outer peripheral member 414, and two disk-shaped members 417a and 417b made of glass. The disk-shaped member 417a is provided on the bottom surface portion of the cylindrical outer peripheral member 414, and the disk-shaped member 417b is provided substantially parallel to the disk-shaped member 417a, and between the disk-shaped member 417a and the disk-shaped member 417b. Is formed with a vacuum space SP for chip suction. The tip tool 411b and the disk-like members 417a and 417b are made of glass (translucent material) and transmit photographing light (visible light, infrared light, etc.).

<4-4. Position adjustment by visible light>
Moreover, in the said embodiment etc., although the case where the image for position recognition is acquired using infrared light is illustrated, it is not limited to this. For example, an image for position recognition may be acquired using visible light.

  For example, in the second embodiment or the third embodiment, the above-described head portion 33Hb (FIG. 41) may be used. The mark MC1 on the chip CP may be imaged using the head unit 33Hb and the imaging units 35a and 35b, and the mark MC2 may be imaged using the imaging unit 35c.

  Alternatively, as shown in FIG. 42, two imaging units 35 (35c, 35d) are provided on the lower side of the substrate WTi (not on the upper side of the chip CP), and the first implementation is performed by the two imaging units 35c, 35d. Similarly to the embodiment, the captured images Ga and Gb may be captured. More specifically, a translucent glass substrate that transmits visible light is used as the temporary substrate WTi, and each mark MC1 (MC1a, MC1b) is a lower surface FT of each chip CPi in the face-up state on the temporary substrate WTi side. Is provided. Then, an image obtained by simultaneously capturing optical images of the marks MC1 and MC2 obtained through the glass substrate WTi and the light-transmitting resin layer RSi that transmits visible light is acquired as a position recognition image. That's fine. More specifically, the imaging unit 35c captures a captured image Ga obtained by simultaneously reading two types of marks MC1a and MC2a, and the imaging unit 35d captures a captured image Gb obtained by simultaneously reading two types of marks MC1b and MC2b. To do.

  As the resin layer RSi, a resin layer having a light-transmitting property that transmits visible light may be employed.

<4-5. Resin layer>
Moreover, in each said embodiment etc., although the case where resin layer RS was formed with a thermoplastic resin was illustrated, it is not limited to this, Resin layer RS is formed with photocurable resin (ultraviolet curable resin etc.). You may make it do.

  When the resin layer RS is composed of a photocurable resin (such as an ultraviolet curable resin), in steps S12 and S22, the resin is cured by light irradiation (such as ultraviolet irradiation by an ultraviolet irradiation unit 319 (not shown)). Thus, each chip may be temporarily fixed to the temporary substrate WTi. In steps S14 and S24, each chip may be separated from the temporary substrate WTi by using a laser ablation technique (a technique for generating bubbles in the resin layer by irradiating a laser beam).

  The ultraviolet irradiation unit 319 may be provided in place of the infrared irradiation unit 318 (FIG. 7) in the first embodiment (or provided with the infrared irradiation unit 318). Further, the ultraviolet irradiation unit 319 may be provided in the imaging unit 35c instead of the infrared irradiation unit 318b (FIG. 39) in the second embodiment or the like (or together with the infrared irradiation unit 318b).

  Further, the resin layer RS may be formed of a thermosetting resin.

  When the resin layer RS is composed of a thermosetting resin, in steps S12 and S22, the uncured resin is heated and cured (using the infrared irradiation unit 318 and / or the head unit 33H). Thus, each chip may be temporarily fixed to the temporary substrate WTi. In steps S14 and S24, each chip may be separated from the temporary substrate WTi by using a laser ablation technique (a technique for generating bubbles in the resin layer by irradiating a laser beam).

<4-6. Chip placement on the substrate>
Further, in each of the above embodiments, the case where the stacking operation of the first layer chip is performed in the same manner as the stacking operation of the chip of each layer after the second layer is exemplified, but the present invention is not limited thereto. The plurality of chips in the first layer may be arranged in a plane on the substrate WA using other methods.

  Further, in each of the above embodiments, each chip CPi of the i-th layer (i = 1, 2,...) Is arranged face-up with respect to the temporary substrate WTi, and the temporary substrate WTi is inverted and the substrate is inverted. Although the case where a plurality of layers of chips are stacked on the substrate WA by repeating the operation of being arranged opposite to the WA is exemplified, the present invention is not limited to this. For example, the above concept may be applied when a single-layer chip is stacked on a substrate.

  In each of the above embodiments, each chip CPi is positioned and arranged on the substrate WTi with the bump surface (surface on which the bump is arranged) of each chip CPi facing upward (face-up state). However, the present invention is not limited to this. For example, the above concept is applied when each chip CPi is positioned and arranged on the substrate with the bump surface (surface on which the bump is arranged) of each chip CPi facing downward (face-down state). You may be made to do.

  More specifically, as shown in FIG. 43, each chip CPi is in a face-down state directly on a resin layer (for example, a resin layer formed of non-conductive resin (NCP)) on the substrate WA. The above-mentioned idea may be applied in the case of being positioned and arranged at a predetermined position. More specifically, each chip CP is provided with a mark MC1 (MC1a, MC1b), and a mark MC2 (MC2a, MC2b) is provided on a corresponding portion on the substrate WA (a portion corresponding to each chip CP). Then, the alignment operation between the chip CP and the substrate WA may be performed using the marks MC1 and MC2.

  In such an embodiment, as described below, as shown in FIG. 44 and the like, each chip CPi may be supplied in a face-down state.

<4-7. Chip reversal>
In each of the above embodiments, as shown in FIG. 2, the case where the face-up chip CP is supplied to the COW bonding apparatus 30 as it is is illustrated, but the present invention is not limited to this. For example, as shown in FIG. 44, the chip CP in the face-up state may be turned upside down by the die picker 131 having a reversing mechanism and supplied to the COW bonding apparatus 30 in the face-down state.

  Specifically, the chip CP (face-up state) held by the die picker 131 with the pushing-up operation by the projecting upper part (protruding needle) 11 is turned upside down by the die picker 131 having a reversing mechanism, and the chip supplier 135 is turned upside down. And is held face-down. The chip CP is received at the position PG3 (PR1) by the chip transport unit 39 in the face-down state.

  The chip transport unit 39 transports the chip CP to a position PG5 (delivery position PR2) immediately below the head unit 33H of the bonding unit 33 by a rotation operation around the central axis AX. The chip CP reaches the delivery position PR2 in a face-down state through such a transport operation.

  In each of the above embodiments, the chip supply apparatus 10 cuts out each chip from the substrate WC having each chip CP in the face-up state, and supplies each chip as it is on the temporary substrate WTi in the face-up state. However, the present invention is not limited to this.

  For example, each chip CP may be cut out and supplied from the substrate WC having each chip CP in the “face-down state”. In this case, in the chip supply device 10, the top and bottom of each chip CP cut out in the face-down state may be inverted so that each chip CP is supplied to the COW bonding device 30 in the face-up state. Alternatively, each chip CP may be supplied to the COW bonding apparatus 30 in a face-down state.

<4-8. Chip Supply Method (Chip Tray Method)>
In each of the above embodiments, a wafer pickup method (a method of directly picking up a chip from the substrate (wafer) WC) is exemplified as a chip supply method (see FIGS. 2 and 44). It is not limited. For example, as a chip supply method, a chip tray method (a method in which a chip taken out from a wafer is once arranged on the tray and a chip is picked up from the tray (chip tray) on which the chip is arranged) is adopted. It may be.

  45 and 46 are diagrams showing a part of the chip mounting system 1 (1E) adopting the chip tray system. FIG. 45 is a plan view showing the chip supply apparatus 10 (10E) and the COW bonding apparatus 30 according to the chip tray system. FIG. 46 is a side sectional view showing the vicinity of the component tray conveying portion 27.

  The chip supply device 10 includes a component tray transport unit 27 that stacks and transports chips CP as components on a tray.

  The component tray transport unit 27 has a plurality of trays 21. Each of the plurality of trays 21 can accommodate a plurality of chips CP.

  The component tray transport unit 27 has a standby position TP11, a transfer position TP12, and a discharge position TP13.

  In the standby position TP11, a plurality of trays 21 each accommodating a plurality of chips (chips as components) CP are stacked (see FIG. 46). The plurality of trays 21 stacked in the standby position TP11 are taken out one by one by a leveling mechanism (not shown), and moved in the Y direction (−Y direction) toward the transfer position TP12.

  At the transfer position TP12, an operation of individually taking out the chips CP from one conveyed tray 21 is performed. Specifically, in a state in which the position of the chip CP to be taken out is recognized by the imaging unit 24 (FIG. 46), the chip transfer device 13 (chip supply unit 135 or the like) sucks and holds the chip CP and holds the tray 21. And the chip CP is transported to the position PR1 (FIG. 45). Further, the chip CP is transferred to the position PR2 (see FIG. 16) by the chip transfer unit 39. In this way, the chip CP is supplied to the COW bonding apparatus 30. By repeating the same operation, the plurality of chips in the tray 21 are individually supplied to the COW bonding apparatus 30.

  When all the chips in the tray 21 at the transfer position TP12 are taken out from the tray 21, the tray 21 (empty tray) is transported to the discharge position TP13. The tray 21 is stacked and held together with another tray (empty tray) from which chips have been removed.

  Each chip may be supplied by such a chip tray system.

  Furthermore, the chip tray method may be employed not only in the case of stacking chips on a substrate but also in a technique for stacking chips on a chip (COC (Chip On Chip) technique). 45 illustrates the case where the tray 21 is used when supplying the chip CP as a component, but the tray 21 may be used when the multilayer chip CS as a finished product is accommodated.

  47 and 48 are diagrams showing a part of the chip mounting system 1 (1F) according to such an aspect. FIG. 47 is a plan view showing the chip supply device 10 (10F) and the COW bonding device 30. FIG. FIG. 48 is a side sectional view showing the vicinity of the finished product tray conveying portion 28.

  In addition to the component tray transport unit 27 described above, the chip supply device 10F also includes a finished product tray transport unit 28 that transports multilayer chips (finished products) CS stacked in multiple layers by the COW bonding device 30 or the like.

  In this system 1F, multilayer chips stacked in multiple layers by the COW bonding apparatus 30 and the WOW bonding apparatus 50 by using the chip CP supplied by the above-described chip tray supply method and the same method as in the first embodiment. CS is formed on the substrate WA. Then, the substrate WA having the multilayer chip CS is transferred from the WOW bonding apparatus 50 to the COW bonding apparatus 30 again. Then, each of the multiple multilayer chips CS is peeled off from the substrate WA, and this time along a reverse path, from the chip transport unit 39 of the COW bonding apparatus 30 to the finished product tray transport unit 28 of the chip supply apparatus 10. Be transported.

  The finished product tray transport unit 28 has a plurality of trays 22. Each of the plurality of trays 22 can accommodate a plurality of multilayer chips (finished products) CS.

  The finished product tray transport unit 28 has a standby position TP21, a transfer position TP22, and a discharge position TP23.

  At the standby position TP21, a plurality of trays 22 are stacked. The plurality of trays 22 stacked in the standby position TP21 are all empty. The plurality of trays 22 are taken out one by one by a spread mechanism (not shown) and moved in the Y direction (−Y direction) toward the transfer position TP22.

  In the transfer position TP22, the multilayer chip CS transferred via the chip transfer units 39 to 13 is placed on the tray 22. By repeating the same operation, a plurality of multilayer chips CS are arranged in the tray 22.

  Further, when there is no space for the multilayer chip CS in the tray 22, the tray 22 (full tray) is transported to the discharge position TP23. The trays 22 are stacked and held together with other trays 22 on which the finished product chip CS has been placed.

  With such a chip tray system, each chip CP as a part may be supplied and a multilayer chip CS as a finished product may be accommodated.

  Here, the case where the multilayer chip CS is formed on the substrate WA using the WOW bonding apparatus 50 is illustrated, but the present invention is not limited to this. For example, in a COW bonding apparatus or the like, a multilayer chip may be formed by directly laminating one or more layers of chips without using a substrate. Also in such a case, it is possible to employ each of the chip tray systems (FIGS. 45 to 48) as described above.

<4-9. Other>
Further, in each of the above-described embodiments and the like, a case where an image for position recognition is acquired using reflected light from an alignment mark is illustrated, but the present invention is not limited to this. For example, an illumination system may be disposed on one side with the alignment mark interposed therebetween, an imaging unit may be disposed on the other side, and a position recognition image may be acquired using transmitted light related to the alignment mark. More specifically, for example, the infrared light emitted from the infrared irradiation unit 318 in the first embodiment is used as an illumination light source, and a captured image by transmitted light is observed from the upper surface side of the chip CP by the imaging units 35a and 35b. You may make it acquire by (imaging).

  Further, in each of the above-described embodiments and the like, two imaging units 35a and 35b are provided, and two captured images Ga and Gb related to the marks MC1a and MC1b are simultaneously captured. However, the present invention is not limited thereto. Not. For example, by providing a single imaging unit 35a on the upper side of the chip CP and sequentially moving the imaging unit 35a along the XY plane, the captured image Ga related to the mark MC1a and the captured image Gb related to the mark MC1b are sequentially displayed. You may make it image | photograph. However, if the two captured images Ga and Gb related to the marks MC1a and MC1b are simultaneously captured by the two imaging units 35a and 35b, the position measurement operation can be performed at higher speed.

  In the first embodiment, the upper surface side of the chip CP (the surface (opposite surface) opposite to the surface (opposite surface) facing the substrate WT among the two upper and lower main surfaces of the chip CP). Although the case where the image for position recognition is acquired using two imaging parts 35a and 35b from is illustrated, it is not limited to this. For example, as shown in FIG. 42, from the lower surface side of the substrate WT (the surface on the side opposite to the surface facing the chip CP (opposite surface) of the two upper and lower main surfaces of the substrate WT). An image for position recognition including the alignment marks MC1 and MC2 is acquired using the two imaging units 35c and 35d, and the positions of the alignment marks MC1 and MC2 (and thus the positions of the chip CP and the substrate WT) are measured. May be. Note that visible light may be used as imaging light, or infrared light or the like may be used.

  In the second and third embodiments, the case where two imaging units 35a and 35b are provided on the upper surface side of the chip CP and one imaging unit 35c is provided on the lower surface side of the substrate WT is illustrated. However, it is not limited to this.

  For example, two imaging units 35a and 35b may be provided on the upper surface side of the chip CP, and two imaging units 35c and 35d may be provided on the lower surface side of the substrate WT. More specifically, an image including the alignment mark MC1a is captured by the imaging unit 35a, an image including the alignment mark MC1b is captured by the imaging unit 35b, an image including the alignment mark MC2a is captured by the imaging unit 35c, and the imaging unit 35d. Thus, an image including the alignment mark MC2b may be taken.

  In this manner, the relative position error including the relative posture error of both the objects CP and WT may be calculated using the four photographing units 35a, 35b, 35c, and 35d.

  However, according to the second embodiment and the third embodiment described above, the relative position error including the relative posture error of both the objects CP and WT can be obtained by using the three imaging units without using the four imaging units. Can be calculated. Therefore, cost can be reduced.

DESCRIPTION OF SYMBOLS 1 Chip mounting system 10 Chip supply apparatus 27 Component tray conveyance part 28 Finished product tray conveyance part 30 Bonding apparatus 31 Stage 33 Bonding part 33H Head part 35,35a, 35b, 35c, 35d Image pick-up part 36 (theta) direction rotation part 37 (theta) direction Drive unit 38 Bearing 39 Chip transfer unit 50 Bonding device 70 Transfer unit 80 Spin coater 90 Loading / unloading unit 311 X direction moving unit 313 Y direction moving unit 315 Substrate holding unit 321 X direction drive unit (X direction drive mechanism)
323 Y direction drive unit (Y direction drive mechanism)
331 Axial moving member 332 Upper disk member 333 Piezo actuator 334 Lower disk member 337 Mirror 391, 391a, 391b, 391c Plate portion 411 Chip tool CP Chip MC, MC1, MC2 Chip position adjustment mark MW, MW1, MW2 Substrate position Mark for adjustment RS resin layer WA substrate WT substrate (temporary substrate)

Claims (24)

An alignment device,
First holding means for holding a first object;
A second holding means for holding a second object;
Both the first object and the second object are arranged to face each other, and the first object is located at a predetermined bonding position in a plane parallel to the placement surface of the second object. The alignment mark related to the first object and the second object from at least one surface side of two opposite surfaces that are surfaces opposite to the opposing surfaces of the two objects. Measuring means for measuring a relative position error between the two objects by imaging an alignment mark relating to the object of
Driving means for correcting the relative position error by relatively driving the first object and the second object in a direction parallel to the placement surface;
An alignment apparatus comprising: The alignment apparatus according to claim 1,
The measuring means includes
First object side imaging means for imaging an image including an alignment mark related to the first object from the opposite surface side of the first object;
An alignment apparatus comprising: The alignment apparatus according to claim 2,
The measuring means includes
Second object side imaging means for imaging an image including an alignment mark related to the second object from the opposite surface side of the second object;
An alignment apparatus further comprising: The alignment apparatus according to claim 3, wherein
An operation of imaging an image including an alignment mark related to the first object by the first object side imaging unit and an image including an alignment mark related to the second object are captured by the second object side imaging unit. The alignment apparatus is characterized in that the operation is executed in parallel. The alignment apparatus according to claim 3, wherein
A supply means for delivering the first object to the first holding means in a state inserted between the first object and the second object at the predetermined bonding position;
Further comprising
The supply means has a thin plate shape,
The first object-side imaging unit is configured to start retreating the supply unit from the predetermined bonding position from the time when the first object is delivered from the supply unit to the first holding unit. An image including an alignment mark related to the first object within a period until,
The second object side imaging means is within a period from when the movement of the bonding target portion of the second object to the bonding position is completed until when the supply means is retracted from the predetermined bonding position. An alignment apparatus that captures an image including an alignment mark related to the second object. The alignment apparatus according to claim 3, wherein
The measuring means includes
Before the first object comes into contact with the second object, by imaging the alignment mark related to the first object and the alignment mark related to the second object, Measuring the first relative position error between each other;
After the first object comes into contact with the second object, an image of the alignment mark related to the first object and the alignment mark related to the second object is imaged so that the two objects are mutually connected. An alignment apparatus characterized by measuring a second relative position error between them. The alignment apparatus according to claim 6, wherein
The alignment device is characterized in that the measurement unit performs an alignment failure determination process based on the second relative position error. The alignment apparatus according to claim 6, wherein
The measuring device determines an amount of correction for the first relative position error related to the same type of object as the first object based on the second relative position error. The alignment apparatus according to claim 2,
The first object side imaging means captures an image including an alignment mark related to the first object and an alignment mark related to the second object from the opposite surface side of the first object. The alignment apparatus is characterized by measuring the relative position error. The alignment apparatus according to claim 9, wherein
The alignment mark portion in the first object transmits infrared light,
The first object-side imaging means captures an image including an alignment mark related to the first object and an alignment mark related to the second object using infrared light as imaging light. Alignment device. The alignment apparatus according to claim 9, wherein
The first object-side imaging means is configured to detect the second object from the opposite surface side of the first object both before and during contact of the first object with the second object. An alignment apparatus for measuring the relative position error by capturing an image including an alignment mark related to the target object and an alignment mark related to the first target object. The alignment apparatus according to claim 1,
The measuring means includes
A second object side imaging means for imaging an image including an alignment mark related to the first object and an alignment mark related to the second object from the opposite surface side of the second object;
An alignment apparatus comprising: The alignment apparatus according to claim 1 or 2,
The measuring means includes
A first imaging unit that captures a first image including a first alignment mark provided on the first object;
A second imaging unit that captures a second image including a second alignment mark provided on the first object;
Calculation means for calculating the relative position error including a relative posture error between the two objects based on the first image and the second image;
An alignment apparatus comprising: The alignment apparatus according to claim 3, wherein
The first object side imaging means includes:
A first imaging unit that captures a first image including a first alignment mark provided on the first object;
A second imaging unit that captures a second image including a second alignment mark provided on the first object;
Have
The second object side imaging means includes:
A third imaging unit that captures a third image including a third alignment mark provided on the second object;
Have
The measuring means includes
Based on the first image, the second image, the third image, and the posture angle of the second object at a reference time point, the relative position error including the relative posture error of the two objects is calculated. Calculating means for
An alignment apparatus further comprising: The alignment apparatus according to claim 14, wherein
The posture angle of the second object at the reference time point is obtained based on two captured images obtained by capturing each of the two alignment marks provided on the second object by the third imaging unit. An alignment apparatus characterized by being provided. The alignment apparatus according to claim 2,
A moving member connected to the first holding means and moving in the stacking direction of the objects;
A rotating member that rotates about a predetermined axis together with the moving member;
Further comprising
The first object-side imaging means is connected to the rotating member and rotates together with the rotating member. The alignment apparatus according to claim 16, wherein
The first object side imaging means has an imaging unit,
An optical path changing member for changing the direction of the optical path of the imaging light with respect to the imaging unit is provided connected to the moving member;
The image pickup unit and the optical path changing member rotate around the predetermined axis in synchronization with the rotation of the rotating member, respectively. The alignment apparatus according to claim 17,
The first holding means has a hollow portion that allows photographing light to pass through and is connected to the moving member,
The hollow device also rotates around the predetermined axis in synchronization with rotation of the rotating member. The alignment apparatus according to any one of claims 1 to 18,
The second object has a resin layer on its mounting surface,
The alignment apparatus includes:
A resin curing means for curing the resin layer;
An alignment apparatus further comprising: The alignment apparatus according to claim 19,
The resin layer is formed of a photocurable resin,
The alignment apparatus, wherein the resin curing unit cures the resin layer by ultraviolet irradiation by an ultraviolet irradiation unit. The alignment apparatus according to claim 19,
The resin layer is formed of a thermosetting resin,
The alignment apparatus characterized in that the resin curing means cures the resin layer by heating using a heating means. The alignment apparatus according to claim 19,
The resin layer is formed of a thermoplastic resin,
The alignment apparatus characterized in that the resin curing means softens the resin layer by heating using a heating means, and cures the resin layer by cooling accompanied by heating stop of the heating means. The alignment apparatus according to any one of claims 1 to 22,
The first object is a semiconductor chip;
The alignment apparatus, wherein the second object is a substrate. An alignment method for aligning a first object held by a first holding means and a second object held by a second holding means,
a) Both the first object and the second object are arranged opposite to each other, and the first object is set in a predetermined plane in a plane parallel to the mounting surface of the second object. With the arrangement at the bonding position, the alignment mark and the first object related to the first object from at least one of the two opposite surfaces, which are surfaces opposite to the opposite surfaces of the two objects, Measuring a relative position error between the two objects by imaging an alignment mark relating to the two objects;
b) correcting the relative position error by relatively driving the first object and the second object in the first direction;
An alignment method comprising:

Images