JP2014045011A - Substrate support system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a substrate support system including a substrate support which allows for heating of a substrate while supporting, without hindering the optical path of light used in the positioning of a chip for the substrate.SOLUTION: In a substrate support system having an optical system for positioning a chip at a predetermined position on a substrate WA by image recognition, and substrate side heating means for heating the substrate while supporting on a substrate supporting surface 501, the optical system includes a light-emitting device and a light-receiving device configured so that light is propagated while transmitting through at least the substrate side heating means in a direction substantially perpendicular to the substrate supporting surface, and an image recognition device for measuring a relative positional error of the chip and substrate, by recognizing a chip side mark put on the chip and a substrate side mark put on the substrate. The substrate side heating means includes a first transparent insulation layer 504 having the substrate supporting surface and a heater surface 502 on the front and back, and a transparent conductive layer 503 provided on the heater surface of the first transparent insulation layer and generating heat by electrification.

Description

  The present invention relates to a substrate support system having an optical system for positioning a chip at a predetermined position on a substrate by image recognition, and substrate side heating means for supporting and heating the substrate.

  In chip-on-wafer (a technique for bonding a large number of chips on a wafer), a bonding unit that holds the chips positions and bonds each chip to a predetermined bonding position on the wafer. By connecting the bumps (metal protrusions) of the chip and the corresponding metal parts of the wafer to establish electrical conductivity, electrical signals can be exchanged between the chip and the wafer. In this bonding, it is necessary to ensure sufficient electrical conductivity between the chip and the wafer by heating the bumps (metal protrusions) of the chip and sufficiently diffusing the atoms of the metal part of the chip and the wafer. It is.

  Conventionally, since metal heaters are provided on both sides of the chip and the substrate for heating, (Prior Document 1) An image recognition means for aligning the chip and the substrate is inserted between the chip and the substrate and then retracted after the alignment. The method of joining was taken. However, this method requires a distance that allows a two-field camera to be inserted between the chip and the substrate during alignment, which increases the time required for bonding per chip, and reduces the productivity. The position shift of the Z axis (perpendicular to the bonding surface of the wafer) is likely to occur until the position, which is disadvantageous in terms of accuracy.

  Therefore, as shown in the prior art document 2, there has been proposed a method for increasing the positioning accuracy during bonding while transmitting infrared rays. However, conventionally, the bump is heated by heating the chip with a heater or the like provided in the bonding portion. In this case, however, a problem may arise because the wafer is not heated. For example, even if the bumps of the chip reach a sufficient temperature, the metal part of the wafer is near room temperature, so that a temperature difference occurs between the bumps of the chip and the metal part of the wafer at the time of contact. After contact, heat flows from the bumps of the chip, causing the temperature of the metal part of the wafer to rise, but heat also diffuses to other parts of the wafer, so that the atoms in the metal part do not rise sufficiently to diffuse. There's a problem. Still further, when the heated chips contact the wafer one after another, the substrate support that supports the wafer accumulates heat, and the temperature changes gradually with time. As a result, even between chips bonded to the same wafer, for example, between the first bonded chip and the last bonded chip, the bonding strength and electrical conductivity of the interface formed by bonding are not uniform. There is a problem that occurs.

  In order to heat the wafer, it is conceivable to incorporate an electric heater in the support of the wafer. However, there may be a problem also in this case. That is, each chip must be positioned at a predetermined position on the wafer by a chip-on-wafer, and this positioning may be disturbed by an electric heater provided on the wafer support. For example, the positioning of the chip with respect to the wafer is performed by recognizing a mark provided in advance on the chip and the wafer by using light passing through the chip, the wafer and the wafer support in a direction perpendicular to the wafer surface. Is measured, and the position of the chip with respect to the wafer is determined so as to correct the relative position of these marks. In this case, the light must pass through the wafer in the vertical direction, but there is a problem that the electric heater incorporated in the wafer support obstructs the optical path of this light.

Patent Publication 2004-22949 Patent Publication 2012-138423

  In order to solve the above problems, an object of the present invention is to provide a substrate support system including a substrate support capable of heating a substrate without interfering with an optical path of light used for positioning a chip with respect to the substrate.

  In order to solve the above technical problem, a substrate support system according to the present invention includes an optical system for positioning a chip at a predetermined position on a substrate by image recognition, and a substrate support surface. A substrate side heating means for supporting and heating the substrate on the surface, and the optical system transmits light through at least the substrate side heating means in a direction substantially perpendicular to the substrate support surface. An image recognition device for measuring a relative position error between a chip and a substrate by recognizing a light-emitting device and a light-receiving device configured as described above, and a chip-side mark attached to the chip and a substrate-side mark attached to the substrate The substrate side heating means includes a first transparent insulating layer having a substrate support surface and a heater surface on the front and back, a transparent conductive layer provided on the heater surface of the first transparent insulating layer, and generating heat when energized, I prepared to Than is. According to the present invention, the chip can be positioned with respect to the substrate with high accuracy by using the light transmitted through the substrate-side heating means (substrate support) that supports and heats the substrate in a substantially vertical direction, and is a heater. By heating the substrate by heat generated by energization of the transparent conductive layer, good bonding between the chip and the substrate can be efficiently obtained.

  In the present invention, the “substrate” (also referred to as a wafer) includes a plate-shaped semiconductor, but is not limited thereto, and other than the semiconductor, a material such as glass, ceramics, metal, plastic, or a composite material thereof. It may be formed by various shapes such as a circle and a rectangle.

  In the present invention, the term “chip” is given as a broad term indicating a molded semiconductor plate-like component including a semiconductor component, an electronic component such as a packaged semiconductor integrated circuit (IC), and the like. The “chip” includes a component generally called a “die”, a component having a size smaller than that of the substrate, and a size that allows a plurality of components to be bonded to the substrate, or a small substrate. Further, the substrate and the chip may be the same size. For example, both the chip and the substrate are wafers, and positioning with respect to each other when bonding the wafers to each other is also included in the present invention. In addition to electronic components, optical components, optoelectronic components, and mechanical components are also included. Furthermore, the “chip” is not limited to a semiconductor chip, but refers to glass, a lens, or a small piece member. The substrate is not limited to a circuit board, but refers to a base member on which a chip (small piece member) is mounted.

  In the present invention, “chip” and “substrate” may be interchanged. For example, these may be represented as a first object and a second object.

  In the present invention, “transparent” of the transparent insulating layer and the transparent conductive layer is “transparent” to such an extent that the light used can sufficiently pass through the transparent insulating layer and the transparent conductive layer and further the chip for the image recognition. "Means.

  In the present invention, “light” means an electromagnetic wave having a wavelength capable of transmitting the material forming the transparent insulating layer and the transparent conductive layer, and includes visible light and infrared light. The wavelength and intensity of light are selected according to the optical characteristics of the portion through which light to be used such as the transparent insulating layer and the transparent conductive layer is transmitted.

  The substrate support system may further include a pair of electrodes provided in parallel to each other for flowing a current through the transparent conductive layer. Thereby, a board | substrate can be heated uniformly and it can maintain at a uniform temperature over the board | substrate surface.

  The substrate support system may include a substrate suction hole that penetrates the transparent conductive layer and the first transparent insulating layer. Thereby, a board | substrate can be fixed to a board | substrate support surface with high adhesiveness by vacuum suction. As a result, the efficiency of heat conduction from the substrate-side heating means to the substrate increases, and the heat conduction becomes more uniform across the substrate surface. In addition, since it is possible to prevent positional displacement of the substrates on the substrate support surface during bonding, it is possible to perform bonding while maintaining high-precision positioning.

  The substrate support system may further include a second transparent insulating layer disposed so as to sandwich the transparent conductive layer with the first transparent insulating layer. Thereby, since the intensity | strength of a board | substrate side heating means can be raised or maintained, a 1st transparent substrate can be made comparatively thin. As a result, the distance between the transparent conductive layer as a heat source and the substrate to be supported can be reduced, the substrate can be efficiently heated, and the controllability of the temperature of the substrate can be improved.

  The said board | substrate support system WHEREIN: The through-hole which connects the through-hole opened on the board | substrate support surface of a 1st transparent insulating layer, and the through-hole opened in the side surface of a 1st transparent insulating layer may be provided. Thus, a structure such as a vacuum system for adsorbing the substrate on the side surface can be arranged so as not to interfere with the structure for supporting the second transparent insulating layer and the optical path of light used for positioning.

  The substrate support system may further include a capacitance layer provided on the substrate support surface of the first transparent insulation layer, and a third transparent insulation layer provided on the capacitance layer. Good. The third transparent insulating layer directly contacts the substrate and supports the substrate. Thereby, the electrostatic capacity layer can be charged and the substrate can be adsorbed by the electrostatic chuck action. Further, since a through hole (suction hole) is not required, light used for positioning the chip can be transmitted over the entire surface of the substrate. In addition, since the through hole is not necessary, the non-uniform flow of current due to the hole penetrating the capacitance layer is eliminated, so that the first transparent insulating layer can be uniformly heated over the entire surface.

  In the above substrate support system, the bonding head is disposed on the substrate support surface side of the first transparent insulating layer, holds the chip, and is mounted on the substrate surface supported by the substrate side heating means. A bonding head having a light guide for propagating light in a substantially vertical direction may be further included. As a result, the electrical connection between the chip wafers can be reliably established after the chips are accurately positioned at predetermined positions on the substrate (wafer).

  In the substrate support system, the bonding head may be configured to heat the held chip. Thereby, since the junction part of a chip | tip and a board | substrate can be heated from both a chip | tip side and a board | substrate side, the mechanical strength and electrical conductivity in a junction part can be raised further.

  The substrate support system moves the chip and the substrate relatively to correct the relative position error between the chip side mark attached to the chip recognized by the optical system and the substrate side mark attached to the substrate. A positioning mechanism for positioning may be further provided. Thereby, the chip can be accurately positioned at a predetermined position on the substrate surface supported on the substrate side heating means (substrate support).

  According to the present invention, it is possible to position the chip with respect to the substrate at high speed and with high accuracy using light that passes through the substrate-side heating means (substrate support) in a substantially vertical direction, and to heat the substrate. As a result, it is possible to efficiently obtain good bonding between the chip and the substrate.

It is a top view which shows the structure of a chip mounting system. It is a front view which shows a chip supply apparatus. It is a front view which shows the structure of a bonding apparatus. It is a figure which shows the detailed structure of a head part. It is a figure which shows the positional relationship of the mark on a chip | tip, and the hollow part of a head part. It is sectional drawing which shows the II-II cross section in FIG. It is sectional drawing which shows the II cross section in FIG. It is a figure which shows the positional relationship of the mark on another chip | tip, and the hollow part of a head part. It is a top view which shows the structure of the stage vicinity in a COW bonding apparatus. It is a figure which shows the chip | tip for a chip position adjustment provided in the chip | tip. It is a figure which shows the mark for chip position adjustment provided in the board | substrate. It is a figure which shows the relative position shift of both the chip position adjustment marks. It is a front view of the substrate side heating means concerning a first embodiment. It is a top view of the substrate side heating means concerning a first embodiment. It is a schematic diagram of a substrate support system. It is a schematic diagram of a substrate support system. It is a front view of the board | substrate side heating means which concerns on 2nd embodiment. It is a front view of the board | substrate side heating means which concerns on 3rd embodiment. It is a top view of the substrate side heating means concerning a third embodiment. It is a front view of the board | substrate side heating means which concerns on the modification of 3rd embodiment.

  Hereinafter, embodiments of a substrate support system according to the present invention will be described with reference to the accompanying drawings. First, a chip mounting system (electronic component mounting system) in which the substrate support system is used will be described. The chip mounting system 1 is a system in which single-layer or multilayer chips are stacked and mounted at a plurality of planar positions on a substrate (substrate to be mounted on a chip).

<1. Explanation of chip mounting system>
FIG. 1 is a plan view showing a schematic configuration of the chip mounting system 1. In FIG. 1 and the like, directions and the like are shown using an XYZ orthogonal coordinate system for convenience.

  A chip mounting system 1 shown in FIG. 1 includes a chip supply device 10 that individually supplies each chip CP to be attached or bonded to a substrate, and a COW that attaches or bonds each chip CP supplied from the chip supply device 10 to a substrate. (Chip On Wafer) Bonding Device 30, WOW (Wafer On Wafer) Bonding Device 50 that Joins Chip CP Attached to the Substrate to Other Substrate by One-Time Bonding, and Chip, Substrate or Substrate Bonded Substrate Etc. from the outside to the inside of the chip mounting system, and from the inside to the outside, a chip, a substrate, etc. are connected between the COW bonding device 30, the WOW (Wafer On Wafer) bonding device 50, and the loading / unloading portion 90. It has the conveyance part 70 to convey.

  For example, the chip mounting system 1 can bond a plurality of chips CP1 in the first layer on the target substrate WA. The chip mounting system 1 can also stack and bond a plurality of second-layer chips CP2 and the like on a plurality of first-layer chips CP1 arranged on the substrate WA.

  Hereinafter, each of the chip supply device 10, the COW bonding device 30, the WOW bonding device 50, the conveyance unit 70, and the carry-in / out unit 90 included in the chip mounting system 1 will be described in more detail.

<2. Chip Supply Device 10>
A chip supply apparatus 10 shown in FIG. 2 includes a protrusion 11 that pushes up and takes out each chip CP from a diced wafer, and a die picker 131 and a die picker 131 having a reversing mechanism that temporarily holds the orientation of the taken-out chip and changes its orientation. The chip transfer device 13 is configured to receive the chip from the COW bonding device 30 and place the chip on the chip transport unit 39 extending into the chip supply device 10.

  Specifically, the chip CP (face-up state) held by the die picker 131 with the pushing-up operation by the projecting upper part (protruding needle) 11 is turned upside down by the die picker 131 having a reversing mechanism, and the chip supplier 135 is turned upside down. And is held face-down. The chip CP is received at the position PG3 by the chip transport unit 39 in the face-down state.

  Further, in each of the above embodiments, in the chip supply device 10, each chip is cut out from the chip substrate WC having each chip CP in the face-up state, and each chip is directly supplied onto the substrate WA in the face-up state. However, the present invention is not limited to this.

  For example, each chip CP may be cut out and supplied from the chip substrate WC having each chip CP in the “face-down state”. In this case, in the chip supply device 10, the top and bottom of each chip CP cut out in the face-down state may be inverted so that each chip CP is supplied to the COW bonding device 30 in the face-up state. Alternatively, each chip CP may be supplied to the COW bonding apparatus 30 in a face-down state.

<3. COW Bonding Device 30>
The COW bonding apparatus 30 shown in FIG. 2 includes a stage 31 on which a substrate is placed and having a positioning mechanism, a bonding unit 33 having a head 33H for mounting the chip CP on the substrate WA, and a chip CP supplied from the chip supply apparatus 10. 15 to the bonding unit 33, a light source 47 that is a light emitting device, an imaging unit (or camera) 35 that is a light receiving device, and an image recognition device (position recognition unit) 46 (FIG. 15 or FIG. 16).) And an optical system.

  The COW bonding apparatus 30 is an apparatus (also referred to as an alignment apparatus) that positions and arranges each of the plurality of chips CP supplied from the chip supply apparatus 10 on the substrate WA. For example, the COW bonding apparatus 30 planarly arranges (planar arrangement) a plurality of chips (electronic components) CP on the substrate WA with their bonding surfaces facing downward (face-down state).

  As shown in FIG. 2, the chip CP in the face-up state may be turned upside down by the die picker 131 having a reversing mechanism and supplied to the COW bonding apparatus 30 in the face-down state.

<3-1. Chip Transfer Unit 39>
The chip transport unit 39 receives the chip CP from the chip transport device 13 at the delivery position PG3, and transports the chip CP to a position PG5 directly below the head unit 33H of the bonding unit 33 by a rotation operation around the central axis AX. The chip CP reaches the delivery position PG5 in the face-down state through such a transport operation.

<3-2. Bonding section 33>
The bonding part 33 is a part for placing the chip CP on the substrate WA, and is also referred to as a chip mounter.

  As shown in FIG. 3, the bonding portion 33 includes a Z-axis direction moving member 331, an upper disk member 332, a piezo actuator 333, a lower disk member 334, a mirror fixing member 336, a mirror (optical path changing member) 337, and a head portion. (Also referred to as a bonding head) 33H, and further includes a Z-direction drive unit 34 (not shown), a θ-direction rotation unit 36, a θ-direction drive unit 37, a bearing 38, and the like.

  An upper disk member 332 is fixed to the lower end of the Z-axis direction moving member 331. A lower disk member 334 is disposed below the upper disk member 332. The upper disk member 332 and the lower disk member 334 are connected via three piezo actuators 333. Further, the head portion 33H is fixed to the lower surface side of the lower disk member 334. Thus, the Z-axis direction moving member 331 is connected to the head portion 33H via the upper disk member 332, the piezo actuator 333, the lower disk member 334, and the like.

<Head 33H>
The head portion 33H is a holding member that sucks and holds the chip CP, and is also referred to as a chip holding member (electronic component holding member).

  The head unit 33H may include a vacuum suction mechanism in order to hold the chip CP. For example, the head portion 33H can be configured such that a vacuum suction hole (not shown) is provided in a portion of the head portion 33H that contacts the chip CP, and the vacuum suction hole is evacuated. Thereby, the head part 33H can hold | maintain the chip | tip CP by the vacuum suction hole evacuated when the chip | tip supply apparatus 10 receives the chip | tip CP. Therefore, the head portion 33H can transport the chip CP from the chip supply device 10 to the COW bonding device 30 in a state where the chip CP is adsorbed with a sufficient force. When the chip CP is attached to the substrate WA, the head portion 33H can release the chip CP by releasing the evacuation and making the pressure in the vacuum suction hole equal to or higher than the atmospheric pressure.

  As shown in FIG. 4, the head portion 33 </ b> H includes a tip tool 411 and a head main body portion 413. The tip tool 411 is formed of a member (silicon (Si) or the like) that transmits photographing light (infrared light or the like). The head main body 413 is formed with a built-in ceramic heater, for example. Ceramic heaters can be subjected to rapid heat treatment (compared to coil heaters and the like). The head main body 413 has hollow portions (holes) 415 and 416 for transmitting (passing) photographing light. Each of the hollow portions 415 and 416 is a transmission portion (also referred to as a slit portion) that transmits photographing light, and is provided so as to penetrate the head main body portion 413 in the vertical direction. Specifically, each of the hollow portions 415 and 416 has an elliptical shape in a top view. The two hollow portions 415 and 416 are arranged point-symmetrically about the axis BX in the diagonal portion of the head body portion 413 having a substantially square shape when viewed from above (see also FIG. 5). In order to transmit photographing light, a hole (hollow part) is also provided in a corresponding part of the lower disk member 334 and the like.

  By controlling the degree of expansion and contraction in the Z direction of each of the three piezoelectric actuators 333 (FIG. 3), the inclination angle of the lower disk member 334 (and thus the head portion 33H) with respect to the horizontal plane is adjusted. For example, it is possible to perform a parallel adjustment operation of the lower disk member 334 (and the head portion 33H) with respect to the ground plane. Note that the three piezoelectric actuators 333 are arranged at positions (planar positions) that do not block the optical path of light incident on the imaging unit 35 (see also FIG. 6).

  Further, the upper disk member 332 (FIG. 3) is provided with a mirror (optical path changing member) 337. Specifically, the mirror 337 is fixed to the upper disk member 332 via the mirror fixing member 336, and is disposed in the gap between the upper disk member 332 and the lower disk member 334. Thus, the mirror 337 is provided connected to the Z-axis direction moving member 331. The mirror 337 has two inclined planes having an inclination angle of 45 degrees obliquely downward. The mirror 337 is an optical path changing member that changes the direction of the optical path of light incident on the imaging unit 35 using these inclined planes.

<Z direction drive unit 34>
The Z-direction drive unit (also referred to as Z-direction drive mechanism) 34 has a servo motor and a ball screw. The Z-direction drive unit 34 is provided on the upper end side of the θ-direction rotation unit 36 (rotation member 361 (described later)), and the bonding unit 33 (specifically, the Z-axis direction movement member 331) is moved in the Z direction (vertical direction). To drive. When the Z-axis direction moving member 331 is moved in the Z direction by the Z-direction drive unit 34, the head portion 33H on the lower end side of the bonding unit 33 is also moved in the Z direction along with the moving operation. That is, the head portion 33H is driven in the Z direction (also referred to as a chip stacking direction with respect to the substrate) by the Z direction driving portion 34.

<Θ direction rotation part 36>
The θ-direction rotating part 36 has a substantially cylindrical rotating member 361. The rotating member 361 is installed in the upper part of the main body of the COW bonding apparatus 30 so as to be fixed in the vertical direction (Z direction) and to be rotatable around the rotation axis BX. The rotating member 361 is rotated around the rotation axis BX by the θ-direction driving unit 37 provided in the upper housing portion of the COW bonding apparatus 30. The θ-direction drive unit (also referred to as θ-direction drive mechanism) 37 includes a servo motor and a gear mechanism.

  Further, a Z-axis direction moving member 331 of the bonding portion 33 is disposed in the internal space of the substantially cylindrical rotating member 361 via a bearing 38.

  7 is a cross-sectional view taken along the line II of FIG. As shown also in FIG. 7, the Z-axis direction moving member 331 is a rod-shaped member (substantially octagonal prism-shaped member) having a substantially octagonal cross section. Further, the rotating member 361 having a substantially cylindrical outer peripheral surface has a substantially octagonal column-shaped hole (gap) on the inner peripheral side thereof. And the Z-axis direction moving member 331 is inserted and arrange | positioned at the said hole. Further, a bearing 38 is provided between the inner peripheral surface of the rotating member 361 and the Z-axis direction moving member 331. Specifically, the bearings 38 are respectively provided on every other four side surfaces of the eight side surfaces of the Z-axis direction moving member 331. Each bearing 38 is extended and arranged in the Z direction. With such a configuration, the Z-axis direction moving member 331 can smoothly slide in the vertical direction (Z direction) with respect to the inner peripheral surface of the rotating member 361.

  The Z-axis direction moving member 331, which is a substantially octagonal prism-shaped member, is in contact with the inner surface of the rotating member 361 via the bearing 38 on the four side surfaces, and in the horizontal direction, It does not move relative to it. Therefore, the Z-axis direction moving member 331 rotates together with the rotation member 361 in accordance with the rotation operation about the rotation axis BX of the rotation member 361. That is, the Z-axis direction moving member 331 and the rotating member 361 rotate around the rotation axis BX in synchronization. As a result, the bonding part 33 and the θ-direction rotating part 36 rotate around the rotation axis BX in synchronization.

<3-3. Light source 47>
In FIG. 2, the light source 47, which is a light emitting device, is disposed below the stage 31, that is, on the opposite side of the bonding portion 33 with respect to the stage 31. When the bonding part 33 holding the attached chip CP is sufficiently close to the attachment position, the light emitted from the light source 47 is transmitted through the substrate WA, the chip CP, and the chip tool 411 of the head part 33H, and the bonding part is hollow. Passing through the sections (holes) 415 and 416, the light is received by the imaging sections 35a and 35b.

  The light source 47 is preferably arranged so that the optical axis of the emitted light is perpendicular to the surface (substrate support surface 501 described later) of the stage 31 that supports the substrate WA. Alternatively, the light source 47 is preferably arranged so that the optical axis is at least perpendicular to the surface direction of the substrate support surface 501 of the substrate WA to which the chip is to be attached. Thereby, the measurement accuracy of the relative position error in the direction parallel to the substrate support surface 501 between the mark on the substrate WA side and the mark on the chip CP side can be increased.

  The optical axis of the light source 47 may be set to have a predetermined angle with respect to the substrate support surface 501 of the substrate WA. For example, the substrate support between the mark MC2 on the substrate WA side and the mark MC1 on the chip CP side is arranged by arranging the light source 47 so that the optical axis forms the same angle with respect to the substrate support surface for a plurality of chips. The measurement accuracy of the relative position error in the direction parallel to the surface 501 may be increased.

  As light emitted from the light source 47, for example, visible light or infrared light can be used. When the part where the mark MC1 or the like of the chip CP is formed is made of a material that restricts transmission of visible light such as silicon (Si), it is preferable to use infrared light as the light. .

When the light used is visible light or infrared light, the transparent insulating layer may be formed of glass. For example, the transparent insulating layer may be formed of glass containing silicon dioxide (SiO ₂ ) as a main component. However, the material of the transparent insulating layer is not limited to glass. Properties such as the material and thickness of the transparent insulating layer can be appropriately selected. For example, resin or plastic can be used as the material, and the transparent insulating layer may be formed in a shape generally called a thin film as the thickness.

<3-4. Imaging unit 35>
Two imaging units 35 (35a, 35b) are connected to the rotation member 361 of the θ-direction rotation unit 36. Specifically, the imaging unit 35a is connected to the rotating member 361 via the camera Z direction driving unit 363, the camera F direction driving unit 365, and the like, and the imaging unit 35b is connected to the camera Z direction driving unit 363 and the camera F. It is connected to the rotating member 361 via the direction driving unit 365 and the like.

  The imaging unit 35 (specifically, 35a and 35b) acquires an optical image related to marks MC1 and MC2 (described later) as image data. The image recognition device (position recognition unit) 46 recognizes the position of each chip CP on the substrate WA based on the image taken by the imaging unit 35. Specifically, the position recognition unit 46 uses the marks MC1 and MC2 to determine the position of each chip in the direction parallel to the substrate plane of the substrate WA (the relationship between each chip CP and the substrate WA in the plane parallel to the substrate WA). (Relative position relationship).

  Each imaging unit 35a, 35b has an imaging sensor 351 and a lens unit 352, respectively. Thereby, the mark MC1 (MC1a, MC1b) arranged in the chip CP held by the head portion 33H and the mark MC2 (MC2a, MC2b) arranged in the substrate WA arranged to face the chip CP are obtained. Including image data is acquired. More specifically, the imaging unit 35a acquires image data including the mark MC1a and the mark MC2a, and the imaging unit 35b acquires image data including the mark MC1b and the mark MC2b. The imaging units 35a and 35b transmit the acquired image data to the position recognition unit 46, respectively.

  In this embodiment, the case where image data by transmitted light is acquired is illustrated, but the present invention is not limited to this, and image data by reflected light may be acquired. For example, each imaging unit 35a, 35b may be configured to have a coaxial illumination system. Image data relating to reflected light of illumination light (for example, infrared light) emitted from a light source (also referred to as an emission unit) of the coaxial illumination system is acquired. Illumination light emitted in the horizontal direction from the respective coaxial illumination systems of the imaging units 35a and 35b is reflected by a mirror (optical path changing member) 337 (FIG. 3), and the traveling direction thereof is changed vertically downward. . Then, the light travels toward the photographing target portion including the chip CP held by the head portion 33H and the substrate WA arranged to face the chip CP, and the photographing target portion (the substrate surface or the substrate side support surface). ) Is reflected. Further, the reflected light from the imaging target portion travels upward, and then is reflected again by the mirror (optical path changing member) 337, and the traveling direction is changed to the horizontal direction, so that each of the imaging units 35a and 35b. To reach.

<Z-direction synchronous movement and focus adjustment>
The imaging units 35a and 35b are respectively driven in the focus direction by the camera F direction driving unit 365 (FIG. 3), thereby adjusting the in-focus state of each captured image by the imaging units 35a and 35b.

  The imaging units 35a and 35b are each driven in the Z direction (vertical direction) by the camera Z direction driving unit 363 (FIG. 3).

  Basically, the imaging units 35a and 35b are respectively Z-axis direction moving members so that the Z-direction movement amount of the Z-axis direction moving member 331 and the Z-direction movement amounts of the imaging units 35a and 35b are the same. In synchronization with the movement of 331 in the Z direction, each camera Z direction driving unit 363 moves the camera in the Z direction. According to this, even if the Z-axis direction moving member 331 (and thus the head portion 33H) moves in the Z direction, the imaging target ranges of the imaging units 35a and 35b are unchanged before and after the movement.

<Asynchronous movement in Z direction (change of shooting range)>
However, the imaging units 35a and 35b are moved in the Z direction by the camera Z direction driving units 363 so that the Z direction movement amounts of the imaging units 35a and 35b are different from the Z direction movement amounts of the Z-axis direction moving member 331. Sometimes. According to this, the relative positions in the Z direction of the imaging units 35a and 35b and the mirror 337 change, respectively, and the shooting target ranges by the imaging units 35a and 35b are changed.

<Θ direction synchronous rotation>
The imaging units 35a and 35b are connected to a rotating member 361 (FIG. 3) and rotate together with the rotating member 361.

  As described above, the rotating member 361 and the Z-axis direction moving member 331 rotate in synchronization. Further, each imaging unit 35a, 35b is connected to a rotation member 361 (fixed in the θ direction), and the mirror 337 is connected (fixed) to a Z-axis direction moving member 331. Therefore, the two imaging units 35a and 35b and the mirror 337 rotate in synchronization with the rotating member 361. As a result, the relative positional relationship between the two imaging units 35a and 35b and the mirror 337 in a plane parallel to the horizontal plane is unchanged before and after the rotation operation. Therefore, an image accompanied by an optical path change by the mirror 337 (an image near the position immediately below the mirror) can be guided to the imaging units 35a and 35b before and after the rotational operation of the rotating member 361.

  Further, the hollow portions (transmission portions) 415 and 416 of the head portion 33H also rotate around the axis BX in synchronization with the rotation of the rotation member 361. According to this, it is possible to flexibly change the imaging range of each imaging unit 35a, 35b according to the shape of the chip and the like.

  For example, as shown in FIG. 5, for the chip CP having a substantially square shape (and having the marks MC1a and MC1b on the diagonal portions), the imaging units 35a and 35b are arranged on the diagonal line of the chip. Just do it. More specifically, the rotation member 361 is moved to a position where the common optical axis CX (see also FIG. 4) of the imaging units 35a and 35b is inclined by about 45 degrees with respect to a certain side of the rectangular chip CP. Rotate in the direction. Accordingly, an image including the marks MC1a and MC1b (and MC2a and MC2b) can be captured using the imaging light passing through the hollow portions 415 and 416. Note that the portion corresponding to the hollow portions 415 and 416 in the captured image is also expressed as an effective captured portion. On the other hand, a portion corresponding to other than the hollow portions 415 and 416 (portion through which the photographing light cannot be transmitted) is also expressed as an invalid photographing portion.

  Further, as shown in FIG. 8, for the chip CP having a horizontally long rectangular shape (and having the marks MC1a and MC1b on the diagonal portions), the common optical axis CX of the imaging units 35a and 35b is rectangular. The rotation member 361 is rotated in the θ direction to a position inclined at an angle shallower than 45 degrees (for example, about 25 degrees) with respect to the lateral side of the shape chip CP. Accordingly, an image including the marks MC1a and MC1b (and MC2a and MC2b) can be captured using the imaging light transmitted through the hollow portions (transmission portions) 415 and 416. The rotation angle θ of the rotation member 361 in FIG. 8 and the rotation angle θ of the rotation member 361 in FIG.

  Thus, it is possible to photograph each mark more appropriately by changing the rotation angle of the rotation member 361 in the θ direction according to the mark position on the chip.

  It is also conceivable to rotate the head portion 33H in the θ direction independently of the rotating member 361. However, in that case, photographing light may be blocked by portions other than the hollow portions 415 and 416. That is, it is difficult to fit each mark on the chip within an effective photographing part. On the other hand, as described above, the hollow portions (transmission portions) 415 and 416 of the head portion 33H rotate around the axis BX together with the imaging portions 35a and 35b and the mirror 337 in synchronization with the rotation of the rotating member 361. Accordingly, it is possible to relatively easily cope with marks provided at various positions on the chip while maintaining the area of the effective photographing portion.

<3-5. Stage 31>
As shown in FIG. 9, the stage 31 includes, as a positioning mechanism, an X direction moving unit 311, a Y direction moving unit 313, a substrate support 315, an X direction driving unit (X direction driving mechanism) 321, and a Y direction driving unit ( Y-direction drive mechanism) 323.

  The stage 31 is movable in the X direction and the Y direction by an XY direction driving mechanism. Thereby, the relative positional relationship between the bonding part 33 and the stage 31 can be changed, and as a result, the position of each chip CPi on the substrate WA can be adjusted.

  On the base member 301 (not shown) of the COW bonding apparatus 30, an X direction moving unit 311 is arranged via an X direction driving unit (X direction driving mechanism) 321. The X direction driving unit 321 includes a linear motor, a slide rail, and the like, and drives the X direction moving unit 311 with respect to the base member 301 in the X direction. In FIG. 9, two X-direction drive units 321 each extending in the X direction are provided at a predetermined distance in the Y direction.

  On the X direction moving unit 311, a Y direction moving unit 313 is arranged via a Y direction driving unit (Y direction driving mechanism) 323. The Y direction driving unit 323 includes a linear motor, a slide rail, and the like, and drives the Y direction moving unit 313 in the Y direction with respect to the X direction moving unit 311. In FIG. 9, two Y-direction drive units 323 extending in the Y direction are provided at a predetermined distance in the X direction.

  A substrate support 315 is fixed to the Y-direction moving unit 313. The substrate support 315 is driven in the X direction and the Y direction according to the driving of the X direction driving unit 321 and the Y direction driving unit 323.

  Further, a rectangular hollow portion (hole portion) 312 may be provided in the central portion of the X direction moving portion 311. Similarly, a rectangular hollow portion (hole portion) 314 may be provided at the central portion of the Y-direction moving portion 313. Furthermore, a circular hollow portion (hole portion) 316 may be provided in the central portion of the substrate support 315. The substrate support 315 is preferably formed of a material that is transparent to the light used, such as glass. Thus, when the chip CP is aligned with the substrate WA, light that passes through the substrate support 315 in a direction perpendicular to the substrate support surface can be used.

<3-6. Chip position adjustment mark MC>
The alignment marks MC1 and MC2 are marks for adjusting the position of the chip CP (electronic component), and are also referred to as chip position adjustment marks (or component position adjustment marks). Here, in order to align one chip CP, two marks MC1a and MC1b are provided as marks MC1 on each chip (FIG. 10), and two marks MC2a and MC2b are provided as marks MC2 on the substrate WA. (FIG. 10). The mark MC1 application portion of the chip CP and the mark MC2 application portion of the substrate are made of a material that transmits imaging light (eg, visible light, infrared light, etc.).

  The two types of marks MC1 and MC2 have different shapes (more specifically, shapes that do not overlap each other). For example, as shown in FIG. 10, a circular shape having a relatively small diameter is used as the mark MC1 (specifically, the marks MC1a and MC1b). On the other hand, as shown in FIG. 11, a circular shape having a relatively large diameter is used as the mark MC2 (specifically, the marks MC2a and MC2b).

  These marks may be formed by metal deposition. If the thickness of the metal deposited on the substrate WA is about several tens of μm, there is no problem in the adsorption of the substrate WA onto the substrate support surface. Since the deposited metal absorbs light, the intensity of light propagating along the optical path decreases. Therefore, the mark appears dark in the bright field image captured by the imaging unit 35.

  Alternatively, the mark may be formed by etching the surface of the substrate WA or the chip. At the level difference caused by the etching, light is irregularly reflected, and the intensity of light propagating along the optical path is reduced. Therefore, the contour of the mark corresponding to the step appears dark in the bright field image captured by the imaging unit 35.

  The mark MC1a is provided at the first reference position (planar position) (left front side in FIG. 10) in each chip CP, and the mark MC1b is the second reference position (planar position) in each chip CP (FIG. 10). Then, it is provided on the right back side. Further, the mark MC2a is provided at a normal position (planar position) corresponding to the first reference position of each chip CP on the substrate WA, and the mark MC2b is positioned at the second reference position of each chip CP on the substrate WA. It is provided at the corresponding regular position (planar position). In short, the mark MC2a is provided at a position corresponding to the mark MC1a, and the mark MC2b is provided at a position corresponding to the mark MC1b. In order to satisfactorily adjust the relative angle between each chip CP and the substrate WA, the marks MC1a and MC1b are preferably provided at positions separated from each other (for example, near both ends of the chip CP). . The same applies to the marks MC2a and MC2b.

  Further, the marks MC1a and MC1b are respectively provided on the lower surface (the surface on which the metal bumps are formed or the surface facing the substrate WA) of the chip CP in the face-down state. However, the present invention is not limited to this, and the marks MC1a and MC1b may be provided on the upper surface (the surface opposite to the surface on which the metal bumps are formed) of the chip CP in the face-down state, or Alternatively, the chip CP may be embedded in the chip CP.

<Description of each embodiment>
Hereinafter, each embodiment of a substrate support system having an optical system and means (heater) for heating the substrate in addition to the substrate support 315 will be described.

<4. First embodiment>
With reference to FIG. 13, the board | substrate side heating means (board | substrate support body) 315 (500) used for the board | substrate support system which concerns on 1st embodiment of this invention is demonstrated. FIG. 13 is a sectional view taken along line AA of FIG. 14 (described later), which is a plan view.

  A substrate support 500 used in the substrate support system according to the first embodiment of the present invention includes a transparent insulating layer 504 having a substrate support surface 501 for supporting the substrate WA and a heater surface 502 on which the transparent conductive layer 503 is provided, It has a transparent conductive layer 503 disposed on the heater surface 502 as a heater. That is, the substrate support (substrate-side heating means) 500 is configured to include a transparent conductive layer 503 that is a heater and a transparent insulating layer 504 between the transparent conductive layer and the substrate to be supported.

  Joule heat generated when a current flows through the transparent conductive layer 503 is transmitted via the substrate support 500 to the substrate WA in contact with the substrate support 500. Thereby, the substrate WA is heated.

  The transparent insulating layer 504 is preferably configured in a plate shape in which the substrate support surface 501 and the heater surface 502 are substantially parallel. Thereby, since the distance between the substrate support surface 501 and the heater surface 502 is substantially equal over the surface of the transparent insulating layer 504, heat generated in the transparent conductive layer 503 can be evenly conducted to the substrate support surface 501. . As a result, the substrate WA can be heated uniformly.

  The positioning of the chip CP on the substrate WA is performed by transmitting light in a direction substantially perpendicular to the substrate support surface 501 or the heater surface 502 of the substrate support 500. Therefore, the light needs to have a wavelength and intensity sufficient for image recognition of a mark such as a mark for positioning the chip CP with respect to a predetermined substrate support. Further, “transparent” of the transparent insulating layer 501 and the transparent conductive layer 503 means that the light used can sufficiently pass through the transparent insulating layer 501 and the transparent conductive layer 503 and further the chip CP for the image recognition. It means “transparent”. That is, the characteristics of the light used and the optical characteristics of the transparent insulating layer 501 and the transparent conductive layer 503 are determined by a relative relationship with each other.

  The plate-like transparent insulating layer 504 shown in FIG. 13 has a predetermined mechanical strength, and is used for attaching and removing the substrate support 504 to and from the substrate support system, attaching and removing the substrate WA to and from the substrate support 504, and the like. In a general process, it may be formed to have sufficient mechanical strength that does not cause problems such as deformation and breakage. For example, when the transparent insulating layer 504 is formed of glass and the dimension in the planar direction is several hundred mm, the thickness can be about 20 mm.

  The plate-like transparent insulating layer 504 has a heater surface 502 on which the electrode 503 is formed, which is the surface opposite to the substrate support surface 501 that supports the substrate WA. A transparent conductive layer 503 is formed on the heater surface 502. The transparent conductive layer 503 can be made of a material appropriately selected from various transparent conductive films or transparent conductive oxide (TCO). For example, ITO (Indium Tin Oxide (indium tin oxide or tin-doped indium oxide)) or tin oxide is preferably employed.

  The transparent conductive layer 503 can be formed under various heating and atmospheric conditions using various techniques such as sputtering, vacuum deposition, sol-gel method, cluster beam deposition, and pulsed laser deposition (PLD).

  The thickness of the transparent conductive layer 503 is preferably, for example, from several tens of nm to several μm, but is not limited thereto. The thickness of the transparent conductive layer 503 depends on conditions such as the intended heating temperature of the substrate support, the applied current voltage value, the resistivity of the material used, the area, the thermal characteristics of the transparent insulating layer and other members. Relative to each other. Depending on the thickness, the sheet resistivity can be, for example, a value from several Ω / sq to over 100 Ω / sq.

  FIG. 14 shows a plan view of the substrate support 315 (500) shown in FIG. Here, the transparent conductive layer 503 is formed on a heater surface 502 of the transparent insulating layer 504 so as to cover a sufficiently wider area than the substrate WA is attached. Furthermore, a substantially rectangular or square transparent insulating layer 504 is used, and the transparent conductive layer 503 is formed over substantially the entire heater surface 502 (the back surface in FIG. 14) of the transparent insulating layer 504. That is, the transparent conductive layer 503 is formed in a substantially rectangular or square planar shape.

  As shown in FIG. 14, a pair of electrodes 505 and 506 are formed on a pair of opposite sides of the transparent conductive layer 503, respectively. That is, the linearly formed electrodes 505 and 506 are formed in parallel or at a constant distance.

  A power source (not shown) that supplies power to the transparent conductive layer 503 is connected to the electrodes 505 and 506. The power source may be a DC power source or an AC power source. This power source is preferably configured to be able to adjust the voltage applied to the electrodes 505 and 506 and the current flowing through the electrode based on the measured temperatures of the substrate support surface 501 and the substrate WA. As a result, the heat generation amount of the transparent conductive layer 503 is adjusted, and the substrate support surface 501 or the substrate WA is heated to a predetermined temperature, or the temperature is maintained.

  By providing a pair of parallel electrodes on opposite sides of the transparent conductive layer 503, the potential between the pair of electrodes 505 and 506 is substantially constant, and the current density of the flowing current is almost the entire surface of the transparent conductive layer 503. It becomes constant. As a result, the heat generation amount per unit area of the transparent conductive layer 503 becomes substantially constant regardless of the location on the surface of the transparent conductive layer 503, so that the transparent insulating layer 504 and the substrate WA can be heated uniformly.

  In FIG. 13 or FIG. 14, the electrodes 505 and 506 are formed as a pair of parallel electrodes on the opposite sides of the transparent conductive layer 503, but are not limited thereto. When the transparent conductive layer 503 is formed with substantially the same thickness by a substance having substantially the same electrical properties, electrodes are formed so that current flows at almost the same current density in each part of the transparent conductive layer 503. It only has to be done. Or an electrode should just be formed so that substantially the same calorie | heat amount may generate | occur | produce in the unit time in each location of the transparent conductive layer 503. FIG.

  As shown in FIGS. 13 and 14, the substrate support 500 is provided with through holes 507 that penetrate the transparent insulating layer 504 and the transparent conductive layer 503, and these through holes 507 are formed on the substrate support surface 501. A connecting groove 508 is formed in a circular shape. Through this through hole 507, a vacuum system (not shown) is provided on the heater surface 502 side of the substrate support 500, and the substrate WA is fixed on the substrate support surface 501 of the transparent insulating layer 504 by vacuum suction. it can. For example, the through hole 507 is formed in a cylindrical shape having a diameter of about 1 mm by using machining or an etching method, and the groove 508 is formed in a circular shape with a width of about 1 mm and a depth of about 0.5 mm to 1 mm. ing. The vacuum system connected to the through hole 507, the groove 508, and the through hole is provided at a position that does not hinder the optical path when the image of the position of the mark is recognized in the step of attaching the chip CP to the substrate WA. preferable. The through hole 507 and the groove 508 are preferably provided at a position on the substrate support surface 501 corresponding to, for example, a region near the edge (edge) of the substrate WA to which the chip CP is not attached.

  It is preferable that a plurality of the through holes 507, which are vacuum suction holes, are arranged uniformly on the substrate support surface. As a result, the substrate WA can be fixed on the substrate support surface 501 with a uniform force by vacuum suction.

  The shape, size, and arrangement of the vacuum suction holes (through holes 507) and the grooves 508 are not limited to the arrangement shown in FIG. 14, and other arrangements may be adopted as appropriate.

  15 shows the substrate support 500 shown in FIGS. 13 and 14, the optical system for positioning the chip CP at a predetermined position on the substrate WA by image recognition, and the substrate WA on the substrate WA while transporting and heating the chip CP. It is a side view which shows typically the board | substrate support system which has the bonding part 33 comprised so that it could be attached to. 15, the optical system includes a light source 47 that is a light emitting device, a mirror 337, imaging units 35a and 35b that are light receiving devices, and a position recognition unit (image recognition device) 46 connected to the imaging units 35a and 35b. And is configured.

  It is preferable that a heater (for example, a ceramic heater) is built in the head portion 33H at the tip of the bonding portion 33. Thereby, the chip CP can be heated while the bonding part 33 holds the chip CP. For example, the chip CP can be heated while the chip CP is received from the chip supply device 10 and conveyed to the upper part of the substrate WA. By heating the chip, the temperature of the metal bump portion of the chip CP that contributes to bonding with the substrate WA can be raised.

  When the metal bump portion is formed of a tin-silver solder material, the heater is heated so that the temperature of the metal bump portion is about 215 degrees Celsius (215 ° C.). preferable.

  In the present invention, the surface of the substrate WA to which the chip CP is attached can be heated to an appropriate temperature via the substrate support 500 by the heat generated from the transparent conductive layer 503. For example, when the metal bump portion formed on the surface of the substrate WA is formed of a tin-silver solder material, it is preferably heated and maintained at a temperature of about 215 degrees Celsius (215 ° C.).

  Unlike the case where the heating of the metal bump portion is performed only by the heating of the head portion 33H, it is possible to heat the substrate WA side as well, so that both the metal bump portion to be bonded to each other and the bonding portion of the substrate are connected. By heating to an appropriate temperature before contact and bringing the heated metal bump portion and the joint portion of the substrate into contact with each other, a joint interface having good electrical conductivity can be formed.

  By using the substrate support system according to the present invention, for example, the substrate WA is a 500 μm thick silicon (Si) substrate, the transparent insulating layer 504 is 20 mm thick, the transparent conductive layer 503 is ITO, thick When the thickness is about 200 nm, the temperature of the surface of the substrate WA can reach 215 ° C. in about 5 minutes. Further, by performing feedback control while measuring the temperature of the surface of the substrate support 500, the temperature of the surface of the substrate WA can be kept within a range of about ± 0.5 ° C. Furthermore, since the electrodes 505 and 506 for supplying current to the transparent conductive layer 503 are provided in parallel to each other, the temperature variation (non-uniformity) on the surface of the substrate WA is within a range of about ± 0.5 ° C. Can keep.

<COW process>
As described above, the COW bonding apparatus 30 includes the position recognition unit 46 connected to the imaging unit 35. The position recognition unit 46 is a processing unit that recognizes the relative position (specifically, X, Y, θ) between the chip CP and the substrate WA in the horizontal direction.

  The positioning operation (alignment operation) between each chip CP and the substrate WA is performed by the position recognition unit 46 using two sets of marks (MC1a, MC2a) and (MC1b, MC2b) attached to each chip CP and the substrate WA. This is done by recognizing the position. This alignment operation is executed during a part of the descending period. In particular, it is preferable that the alignment operation is performed in a state where the chip CP and the substrate WA are very close to each other (the distance between the two is, for example, about several tens of micrometers to several micrometers).

  As shown in FIG. 15, the position recognizing unit 46 emits light emitted from a light source (also referred to as a light emitting device) 47 in a state where each chip CP (CP1) held by the head unit 33H faces the substrate WA. The position of the chip CP on the substrate WA is recognized using image data relating to transmitted light (for example, visible light and infrared light). Note that FIG. 15 conceptually shows that the imaging units 35a and 35b photograph the mark and the like attached to the chip and the substrate from above the chip CP above the substrate WA. Yes.

  As shown in FIG. 15, the light emitted from the light source 47 passes through the transparent conductive layer 503, the region including the marks of the transparent insulating layer 504, and the substrate WA, and then is bonded to the chip CP and silicon (Si) bonding portion 33. The head portion 33H is transmitted, passes through the hollow portion 415 of the bonding portion 33, and is received by the imaging elements of the imaging portions 35a and 35b. Thereby, an image including an optical image related to each chip and the substrate WA is acquired as the image data Ga. That is, a captured image Ga obtained by simultaneously reading the two types of marks MC1a and MC2a is acquired. The position recognizing unit 46 recognizes the position of a certain mark (MC1a, MC2a) and the position of the mark (MC1b, MC2b) attached to each chip and the substrate WA based on the captured image Ga. A displacement amount (Δxa, Δya) between MC1a and MC2a and a displacement amount (Δxb, Δyb) between the marks MC1b and MC2b are obtained (see FIG. 12).

  Based on the positional deviation amounts (Δxa, Δya), (Δxb, Δyb) of these two sets of marks, the position recognizing unit 46 detects each chip CP and the substrate WA in the horizontal direction (X direction, Y direction, and θ direction). Relative positional deviation amounts (Δx, Δy, Δθ) are calculated. Here, the value Δx is the relative positional deviation between the two CPs and WA in the X direction, and the value Δy is the relative positional deviation between the two CPs and WA in the Y direction. Further, the value Δθ is a relative positional shift (also referred to as a relative posture error) between both CPs and WA in the θ direction (rotation direction). The relative positional deviation amounts (Δx, Δy, Δθ) between the two CPs and WA are also expressed as relative positional errors between the two CPs and WA.

  The stage 31 is driven in two translation directions (X direction and Y direction) (translation drive) and rotated in the θ direction so that the relative shift amount recognized by the position recognition unit 46 is reduced. The part 36 and the bonding part 33 are driven (rotated) in the θ direction. As a result, the substrate WA and the chip CP are moved relative to each other, and the positional deviation amount is corrected.

  In this way, the alignment operation of the chip CP (with respect to the X direction, the Y direction, and the θ direction) is executed.

  Thereafter, the head portion 33H holding the chip CP is further lowered, and the chip CP is placed at a predetermined horizontal position on the substrate WA (FIG. 15).

  In this way, the position recognition operation (position displacement measurement operation) and the alignment driving operation (position displacement correction operation) are performed on the chip CP and the substrate WA, and the chip CP is positioned with respect to the substrate WA. Mounted or attached.

  Further, the second and subsequent chip mounting operations are executed in the same manner. As a result, as shown in FIG. 15, the plurality of chips CP are positioned and placed at predetermined plane positions on the substrate WA. As described above, by using the two types of marks MC1 and MC2, each of the plurality of chips CP is positioned in a direction (X, Y, θ) parallel to the substrate plane (main plane) of the substrate WA. Each of the CPs is placed on the substrate.

  In the above embodiment, the one-layer chip CP is attached on the substrate WA. However, the second-layer chip CP may be stacked and attached on the first-layer chip CP. It is possible to attach a stack of chips CP of the third layer, the fourth layer, etc. on the two-layer chip CP (FIG. 16).

  As shown in FIG. 16, for example, by attaching the mark of the chip CP to be attached to the mark of the substrate WA and the mark of the chip CP already attached to the substrate WA by image recognition, the chip CP to be attached is positioned. Can be positioned at a predetermined position.

  The chip CP once attached can be kept substantially at the temperature when it is attached by energizing and heating the transparent conductive layer 503. Furthermore, by heating the chip CP to be attached before attachment by the head portion 33H, the bonding surface of the already-attached chip CP and the metal bump part of the newly attached chip CP are at a suitable temperature. It becomes possible to mount or place the chip on the substrate. As a result, even if the number of layers of the chip CP to be stacked is increased, a good chip can be mounted.

  In the above embodiment, the position of the chip CP in a state where the chip CP is disposed at a predetermined bonding position (X, Y) on the surface of the substrate WA (specifically, a state where the chip CP is disposed at a substantially regular bonding position). A measurement operation is performed. According to this, since the movement amount in the XY direction after the position measurement is very small (value close to zero), it is possible to perform an accurate alignment operation (position alignment operation). In particular, the position of the chip CP is measured in a state where the chip CP is far away from a predetermined bonding position, and fine adjustment between the chip position and the substrate position is performed after the chip CP moves to the bonding position based on the position measurement result. It is possible to perform an accurate alignment operation compared to the case where the above is performed.

  An image Ga obtained by simultaneously imaging the marks MC1a and MC2a attached to both the objects CP and WA with the one imaging unit 35a in a state where the objects CP and WA are close to each other may be acquired. In this case, it is possible to determine the relative position of both objects very accurately. The same applies to the image Gb.

  In addition, two captured images Ga and Gb may be captured simultaneously using the two imaging units 35a and 35b. In this case, it is possible to capture the two captured images Ga and Gb at a higher speed than when moving one imaging unit to capture the two captured images Ga and Gb. Therefore, the alignment operation can be speeded up.

<5. Second embodiment>
FIG. 17 is a side view of a substrate support 500b used in the substrate support system according to the second embodiment of the present invention. As shown in FIG. 17, the transparent conductive layer 503 is sandwiched between these transparent insulating layers by the transparent insulating layer (first transparent insulating layer 504) that supports the substrate WA and the second transparent insulating layer 509. Are arranged as follows.

  In the present embodiment, the transparent conductive layer 503 is preferably formed on the second transparent insulating layer 509. In this case, the transparent conductive layer 503 can be formed on the relatively thick second transparent insulating layer 509, and the relatively thin first transparent insulating layer 504 can be formed on the transparent conductive layer 503. However, the method for forming the transparent conductive layer 503 is not limited to this. The transparent conductive layer 503 may be disposed between the first transparent insulating layer 504 and the second transparent insulating layer 509.

  As a result, the transparent conductive layer 503 is protected by the second transparent insulating layer 509 from contamination and oxidation due to contact with the atmosphere, and also from mechanical damage due to erroneous contact with other components.

  Furthermore, the heating characteristics of the substrate can be improved while maintaining the same mechanical strength as that of the substrate support provided by the single transparent insulating layer in the first embodiment. That is, the second transparent insulating layer 509 is made relatively thick, the first transparent insulating layer 504 is made relatively thin, and the overall thickness of the substrate support 500b is maintained. Strength can be maintained. Or since it is a composite material structure, it is also possible to raise mechanical strength, maintaining thickness. Furthermore, by adjusting these thicknesses, the overall mechanical strength of the substrate support 500b can be set to an appropriate value.

  Furthermore, the first transparent insulating layer 504 can be thinned by relaxing the limitation on the thickness due to mechanical strength. Therefore, the physical distance between the transparent conductive layer 503 that generates heat and the substrate WA to be heated can be shortened. As a result, the heating response (heating response) can be improved. Furthermore, by forming the second transparent insulating layer 509 with a material having a relatively low thermal conductivity such as glass, the amount of loss to the outside such as the atmosphere of heat generated by the transparent conductive layer 503 can be reduced. . Thereby, the substrate WA can be efficiently heated.

  By using the substrate support system according to the present invention, for example, the substrate WA is a silicon substrate having a thickness of 500 μm, the material of the first transparent insulating layer 504 is glass, the thickness is 0.5 mm, and the second transparent insulating layer 504 is When the material is glass, the thickness is 20 mm, the material of the transparent conductive layer 503 is ITO, and the thickness is 200 nm, the substrate WA is heated so that the surface temperature reaches 215 ° C. within a time of several seconds or less. be able to. By performing feedback control while measuring the temperature of the surface of the substrate support 500b for a predetermined type of substrate, the temperature of the substrate support surface 501 can be maintained in a range of about ± 0.5 ° C. Furthermore, since the electrodes for supplying current to the transparent conductive layer 503 are provided in parallel with each other, the temperature variation on the transparent insulating layer can be kept within a range of about ± 0.5 ° C.

  According to the present embodiment, as shown in FIG. 17, a through hole 507 for vacuum-adsorbing the substrate passes through the first transparent insulating layer 501 from the substrate support surface 501 of the first transparent insulating layer 501, You may provide so that it may penetrate to the side part of the 1st transparent insulating layer 501. FIG. This increases the degree of freedom in designing the space below the substrate support 500b in the substrate support system. For example, by arranging a vacuum system (not shown) on the side of the substrate support 500b, the light emitting device (light source) or the light receiving device (imaging device, camera) of the optical system can be relatively freely arranged. Can do.

<6. Third Embodiment>
FIG. 18 is a side view of a substrate support 500c used in the substrate support system according to the third embodiment of the present invention. The substrate support 500c has an electrode 510 therein. As shown in FIG. 18, a capacitance layer 510 is formed on the substrate support surface 501 of the first transparent insulating layer 504, and a dielectric transparent insulating layer (third transparent layer) is sandwiched between the capacitance layers 510. An insulating layer 512) is attached.

  In the present embodiment, the capacitance layer 510 is preferably formed on the first transparent insulating layer 509. However, the method for forming the capacitance layer 510 is not limited to this. The capacitance layer 51 may be disposed between the first transparent insulating layer 504 and the third transparent insulating layer 509.

  The capacitance layer 510 needs to be transparent to the extent that light can be sufficiently transmitted for image recognition.

  The charge accumulated in the capacitance layer 510 by applying a voltage to the electrode 511 causes an opposite charge to appear on the surface of the substrate WA formed of silicon (Si) on the substrate support side, and a pair of these charges is generated. By attracting, the substrate is adsorbed to the substrate support. That is, the substrate support 500c can function as a mechanism (electrostatic chuck) that supports the substrate by static electricity.

  FIG. 19 shows a plan view of the substrate support shown in FIG. The capacitance layer 510 does not need to be formed over the entire area of the transparent insulating layer, and may be provided at a location corresponding to the region to which the substrate is attached as shown in FIG. 18 and 19, a capacitance layer 510 composed of two electrodes is shown. By applying opposite voltages to the two electrodes, different charges are accumulated. However, the shape of the capacitance layer 510 is not limited to the shape shown in FIGS. For example, the capacitance layer 510 may be configured to include one electrode at a location corresponding to a region to which the substrate WA is attached.

  The capacitance layer 510 may be formed of metal, but may be formed using another conductive material. Moreover, it is preferable that the electrostatic capacitance layer 510 has an optical characteristic that allows light used for image recognition to sufficiently pass therethrough. For example, sufficient image recognition can be performed by forming a metal made of ITO or tin oxide as a thin film.

  According to this embodiment, it is possible to heat the substrate while fixing the substrate to the substrate support without providing a through hole such as a substrate suction hole in the substrate support.

  As another example, as shown in FIG. 20, as in the second embodiment, the transparent conductive layer 503 includes a transparent insulating layer (first transparent insulating layer 504) that supports the substrate WA, and a second transparent insulating layer 509. And may be arranged so as to be sandwiched between these transparent insulating layers. Thereby, like the second embodiment, the transparent conductive layer 503 is protected by the second transparent insulating layer 509, and the substrate can be efficiently heated.

  For example, the first transparent insulating layer 504, the second transparent insulating layer 509, and the third transparent insulating layer 512 are formed of glass, the thickness of the second transparent insulating layer 509 is 20 mm, and the first transparent insulating layer 504 and the third transparent insulating layer 509 are formed. The thickness of the transparent insulating layer 512 can be set to 0.5 mm.

  By reducing the thickness of the third transparent insulating layer 512, the adsorption force of the substrate to the substrate support due to static electricity can be increased.

  In the substrate support 500c shown in FIG. 17 and the substrate support 500d shown in FIG. 19, the capacitance layer 510 and the transparent conductive layer 503 are downward from the substrate support surface 501, that is, the substrate WA. The capacitance layer 510 and the transparent conductive layer 503 are arranged in this order in the direction away from the distance. This is because the electrostatic force exerts a high force only at a relatively short distance, and therefore the electrostatic capacitance layer 510 is preferably disposed as close to the substrate WA or the substrate support surface 501 as possible. However, the positional relationship between the capacitance layer 510 and the transparent conductive layer 503 is not limited to the above embodiment. If the substrate WA can be attracted to the substrate support 500c or 500d by a sufficient electrostatic force, the transparent conductive layer 503 and the electrostatic capacitance layer 510 are directed downward from the substrate support surface 501, that is, away from the substrate WA. May be arranged in this order.

  As mentioned above, although several embodiment and the Example of this invention were described, these embodiment and an Example demonstrate this invention exemplarily. The scope of the claims encompasses many modifications to the embodiments without departing from the technical idea of the present invention. Accordingly, the embodiments and examples disclosed herein are presented for purposes of illustration and should not be considered as limiting the scope of the present invention.

1 Chip mounting system 1
DESCRIPTION OF SYMBOLS 10 Chip supply apparatus 30 COW bonding apparatus 31 Stage 33 Bonding part 33H Head part (bonding head)
35a, 35b Imaging unit (light receiving device)
39 Chip transfer unit 46 Position recognition unit (image recognition device)
47 Light source (light emitting device)
50 WOW Bonding Device 70 Conveying Unit 71 Conveying Robot 90 Carrying In / Out Unit 131 Die Picker 135 Chip Feeder 315, 500 Substrate Support (Substrate Side Heating Unit)
337 Mirror (light path changing member)
413 Head body portion 415, 416 Hollow portion (hole)
501 Substrate support surface 502 Heater surface 503 Transparent conductive layer (heater)
504 Transparent insulating layers 505 and 506 Electrode 507 Through hole (substrate adsorption hole)
508 Groove 509 Second transparent insulating layer 510 Capacitance layer 511 Electrode 512 Third transparent insulating layer MC1, MC2 Mark

Claims (9)

A substrate support system comprising: an optical system for positioning a chip at a predetermined position on a substrate by image recognition; and a substrate side heating unit having a substrate support surface and supporting and heating the substrate on the substrate support surface. Because
The optical system is attached to a chip, a light emitting device and a light receiving device configured to transmit light through and propagate at least the substrate side heating means in a direction substantially perpendicular to the substrate support surface. An image recognition device that measures a relative position error between the chip and the substrate by recognizing the chip side mark and the substrate side mark attached to the substrate;
The substrate side heating means includes
A first transparent insulating layer having a substrate support surface and a heater surface on the front and back,
A transparent conductive layer provided on the heater surface of the first transparent insulating layer and generating heat when energized;
A substrate support system comprising:   The substrate support system according to claim 1, further comprising a pair of electrodes provided in parallel to each other, for passing a current through the transparent conductive layer.   The board | substrate support system of Claim 1 or 2 provided with the board | substrate adsorption | suction hole which penetrates a transparent conductive layer and a 1st transparent insulating layer.   The substrate support system according to claim 1, further comprising a second transparent insulating layer disposed so as to sandwich the transparent conductive layer with the first transparent insulating layer.   The through-hole which connects the through-hole opened on the said board | substrate support surface of said 1st transparent insulating layer, and the through-hole opened on the side surface of said 1st transparent insulating layer was provided. Substrate support system. A capacitance layer provided on the substrate support surface of the first transparent insulating layer;
A third transparent insulating layer provided on the capacitance layer and supporting the substrate in contact;
5. The substrate support system according to claim 1, further comprising:   A bonding head disposed on the substrate support surface side of the first transparent insulating layer, holding a chip, and mounting on the substrate surface supported by the substrate side heating means, substantially perpendicularly to the substrate support surface The substrate support system according to claim 1, further comprising a bonding head having a light guide for propagating light.   A bonding head disposed on the substrate support surface side of the first transparent insulating layer, holding a chip, and mounting on the substrate surface supported by the substrate side heating means, wherein the bonding head heats the held chip The substrate support system according to claim 1, wherein the substrate support system is configured to.   A positioning mechanism for correcting the relative position error between a chip-side mark attached to the chip recognized by the optical system and a substrate-side mark attached to the substrate by relatively moving the chip and the substrate; The substrate support system according to claim 7 or 8, further comprising:

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