JP2012028664A - Method of manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To form a mark in each of a plurality of chip regions by applying laser beams to a back surface of a semiconductor wafer.SOLUTION: A stage 20 for fixing a wafer 10 comprises: a first member; and a glass plate (a second member) 22. The space between the first member and the glass plate 22 is provided with a first space, a second space arranged around the first space, and a partition member 23 provided in between the first space and the second space. The first member comprises a plurality of vacuum holes (first openings) 25a connected to the first space and a plurality of vacuum holes (second openings) 25b connected to the second space. The wafer 10 is arranged on the stage 20 so that a mark region (a first region) 5a of a back surface 1b of the wafer 10 does not overlap with the vacuum holes 25a and 25b and the partition member 23 when the wafer 10 is fixed on the stage 20.

Description

  The present invention relates to a semiconductor device manufacturing technique, and more particularly to a technique that is effective when applied to a process of forming a mark on a back surface of a semiconductor wafer by irradiating a laser.

  Japanese Patent Application Laid-Open No. 6-326174 (Patent Document 1) describes a vacuum suction apparatus that vacuum-sucks a semiconductor wafer in a process of performing a projection exposure process on the semiconductor wafer.

  Japanese Patent Application Laid-Open No. Sho 62-221130 (Patent Document 2) describes a vacuum chuck device that covers and adsorbs a vacuum path formed in a base portion with a semiconductor wafer.

JP-A-6-326174 JP 62-221130 A

  The inventor of the present application forms an identification mark such as a product name or a model on the back surface (each chip area) of the semiconductor wafer by irradiating the laser wafer before dividing the semiconductor wafer into a plurality of semiconductor chips. The process was examined and the following problems were found.

  In the laser marking process, the mark area on the back surface of the semiconductor wafer is irradiated with laser light, the member in the irradiated area is removed, and this laser light is scanned to form an identification mark such as a product name or model. Further, in order to accurately specify the mark area provided in each of the plurality of chip areas, alignment is performed by recognizing the alignment mark formed on the surface side of the semiconductor wafer. That is, in the laser marking process, laser light is irradiated from the back surface side of the semiconductor wafer, but it is necessary to fix the alignment mark formed on the front surface side so that it can be recognized.

  However, when the vacuum suction device described in Patent Document 1 or the vacuum chuck device described in Patent Document 2 is applied to the laser marking process, either one of the back surface and the front surface of the semiconductor wafer. Is covered and hidden by the stage that holds and fixes the semiconductor wafer, making it difficult to perform laser irradiation or alignment mark recognition.

  In recent years, the demand for thinner semiconductor devices has increased, and the thickness of semiconductor wafers tends to be thinner. For this reason, warpage (warpage amount) generated in the semiconductor wafer is also increasing. It has been found that the following problems occur when the warpage generated in the semiconductor wafer increases.

  First, in the case of a structure in which the space formed on the stage is covered with a semiconductor wafer and covered, as in the vacuum suction device described in Patent Document 1 and the vacuum chuck device described in Patent Document 2, the semiconductor wafer When warping occurs, a gap is generated between the semiconductor wafer and the stage, making it difficult to attract the semiconductor wafer disposed. For this reason, the accuracy of the processing performed on the semiconductor wafer decreases.

  Also, when laser irradiation or alignment mark recognition is performed with the semiconductor wafer warped, the focal length of the laser beam or alignment mark recognition camera is within the surface of the semiconductor wafer (within the front surface or back surface). Since it is not constant, the laser processing accuracy or the alignment accuracy is lowered. In the vacuum suction device described in Patent Document 1 and the vacuum chuck device described in Patent Document 2, it is difficult to correct such warpage of the semiconductor wafer.

  The present invention has been made in view of the above problems, and an object thereof is to provide a technique capable of forming a mark on each of a plurality of chip regions by irradiating a laser on the back surface of a semiconductor wafer. .

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  That is, the method for manufacturing a semiconductor device which is one embodiment of the present invention includes a step of forming a mark by irradiating the first region on the back surface of the semiconductor wafer with a laser through a stage for fixing the semiconductor wafer. Here, the stage is opposite to the first upper surface and the first member having the first lower surface opposite to the first upper surface, the second upper surface facing the first lower surface, and the second upper surface. A second member having a second lower surface on the side. The stage is positioned between the first member and the second member, between the first member and the second member, and around the first space. And a partition member provided between the first space and the second space. The first member is formed in a region overlapping the first space in a plan view, and has a plurality of first openings connected to the first space, and a region overlapping the second space in a plan view. And a plurality of second openings connected to the second space. In the semiconductor wafer, when the semiconductor wafer is fixed to the stage, the first region of the semiconductor wafer does not overlap the plurality of first and second openings and the partition member in plan view. Furthermore, it is arranged on the stage.

  The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, according to one embodiment of the present invention, a mark can be formed in each of the plurality of chip regions by irradiating the back surface of the semiconductor wafer with a laser.

It is a top view which shows the internal structure of the surface side of the semiconductor device which is one embodiment of this invention. It is sectional drawing along the AA line of FIG. FIG. 2 is a plan view showing a structure on the back side of the semiconductor device shown in FIG. 1. It is explanatory drawing which shows typically a mode that the identification mark shown in FIG. 3 is visually recognized. It is explanatory drawing which shows the assembly flow of the semiconductor device which is one embodiment of this invention. FIG. 6 is a plan view showing a plane on the main surface side of the semiconductor wafer prepared in the semiconductor wafer preparation step shown in FIG. 5. FIG. 7 is an enlarged cross-sectional view showing a partial cross-sectional structure of the semiconductor wafer shown in FIG. 6. FIG. 8 is an enlarged cross-sectional view illustrating a state in which a rewiring layer is formed on the semiconductor wafer illustrated in FIG. 7. It is explanatory drawing which shows typically the process of grinding the semiconductor wafer shown in FIG. It is a top view which shows the back surface side of the semiconductor wafer after a back surface grinding process. It is a top view which shows the surface side of the semiconductor wafer after a back surface grinding process. It is explanatory drawing which shows typically the outline | summary of the process of forming a mark in the back surface of the semiconductor wafer shown in FIG. It is a perspective view which shows the shape of the semiconductor wafer after a back surface grinding process. It is explanatory drawing which shows schematic structure of the mark formation apparatus used for the mark formation process of this Embodiment. FIG. 15 is a cross-sectional view showing a state in which a plurality of wafers are mounted on a wafer rack arranged in the wafer rack arrangement section shown in FIG. 14. It is a top view which shows the upper surface side of the stage arrange | positioned at the mark formation part shown in FIG. It is sectional drawing along the BB line of FIG. FIG. 18 is a cross-sectional view showing a step of placing a wafer on the stage shown in FIG. 17. FIG. 19 is a cross-sectional view illustrating a state in which the back surface of the wafer illustrated in FIG. 18 is sucked and fixed to a suction hole on the inner peripheral side of the stage. FIG. 20 is a cross-sectional view showing a state where the back surface of the wafer shown in FIG. 19 is attracted and fixed to the suction term on the outer peripheral side. It is a top view which shows the state which saw through the wafer from the lower surface side of the stage shown in FIG. FIG. 21 is a cross-sectional view showing a step of recognizing an alignment mark on the surface of the wafer shown in FIG. 20. It is sectional drawing which shows the state which has irradiated the laser beam to the back surface side of the wafer shown in FIG. FIG. 24 is an enlarged cross-sectional view illustrating the periphery of the back surface side of the wafer illustrated in FIG. It is an expanded sectional view which shows the state which mounted the solder ball in the land part formed in the surface side of the wafer in which the mark was formed in the back surface. FIG. 26 is an enlarged cross-sectional view illustrating a state where the wafer illustrated in FIG. 25 is cut along a dicing region. It is explanatory drawing which shows typically the outline | summary of the process of forming a mark in the back surface of the semiconductor wafer of other embodiment of this invention which is a modification of FIG. FIG. 16 is a cross-sectional view illustrating a modified example of FIG. 15 in which a plurality of wafers are mounted on a wafer rack disposed in the wafer rack placement section illustrated in FIG. 14. It is sectional drawing which shows the modification of FIG. It is sectional drawing which shows the modification of FIG. It is sectional drawing which shows the modification of FIG. It is a top view which shows the modification of FIG. It is sectional drawing which shows the modification of FIG. It is sectional drawing which shows the modification of FIG. It is a top view which shows the 1st modification of the several suction hole shown in FIG.

(Description format, basic terms, usage in this application)
In the present application, the description of the embodiment will be divided into a plurality of sections for convenience, if necessary, but these are not independent from each other unless otherwise specified. Regardless of the front and rear, each part of a single example, one is a part of the other, or a part or all of the modifications. In principle, repeated description of similar parts is omitted. In addition, each component in the embodiment is not indispensable unless specifically stated otherwise, unless it is theoretically limited to the number, and obviously not in context.

  Similarly, in the description of the embodiment, etc., regarding the material, composition, etc., “X consisting of A” etc. is an element other than A unless specifically stated otherwise and clearly not in context. It does not exclude things that contain. For example, as for the component, it means “X containing A as a main component”. For example, “silicon member” is not limited to pure silicon, but includes a SiGe (silicon-germanium) alloy, other multi-component alloys containing silicon as a main component, and other additives. Needless to say, it is also included. Moreover, even if it says gold plating, Cu layer, nickel / plating, etc., unless otherwise specified, not only pure materials but also members mainly composed of gold, Cu, nickel, etc. Shall be included.

  In addition, when a specific number or quantity is mentioned, a numerical value exceeding that specific number will be used unless specifically stated otherwise, unless theoretically limited to that number, or unless otherwise clearly indicated by the context. There may be a numerical value less than the specific numerical value.

  Moreover, in each figure of embodiment, the same or similar part is shown with the same or similar symbol or reference number, and description is not repeated in principle.

  In the accompanying drawings, hatching or the like may be omitted even in a cross section when it becomes complicated or when the distinction from the gap is clear. In relation to this, when it is clear from the description etc., the contour line of the background may be omitted even if the hole is planarly closed. Furthermore, even if it is not a cross section, hatching or a dot pattern may be added in order to clearly indicate that it is not a void or to clearly indicate the boundary of a region.

(Embodiment 1)
In this embodiment, as an example of a semiconductor device, an embodiment applied to a so-called WPP (Wafer Process Package) type semiconductor device, which is specifically studied by the present inventor, will be described. WPP is a semiconductor package to which a rewiring technique is applied in which a rewiring layer is formed on a semiconductor chip and external terminals are formed at positions different from the positions of electrode pads in plan view. In WPP, since the process of forming the rewiring layer is performed before the semiconductor wafer is separated into pieces, a fine processing technique for forming a semiconductor element or the like can be applied. For this reason, it is advantageous in terms of downsizing and thinning of the flat area as compared with a semiconductor package in which a semiconductor chip is mounted on a wiring board or a lead frame and these are electrically connected. Such a semiconductor device is called WPP or WL-CSP (Wafer Level Chip Scale Package) because a rewiring layer is formed before the semiconductor wafer is separated.

<Overall structure of semiconductor device>
1 is a plan view showing an internal structure on the surface side of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a semiconductor shown in FIG. It is a top view which shows the structure of the back surface side of an apparatus. FIG. 4 is an explanatory diagram schematically showing how the identification mark shown in FIG. 3 is visually recognized.

  The WPP 1 that is the semiconductor device of the present embodiment has a front surface 1a shown in FIG. 1 and a back surface 1b shown in FIG. The WPP 1 has a semiconductor chip 2 disposed on the back surface 1b side and a rewiring layer 3 disposed on the front surface 1a side. The semiconductor chip 2 includes a surface 2a, a plurality of pads (bonding pads, chip electrodes) 2c formed on the surface 2a, and a back surface 2b (the same surface as the back surface 1b of the WPP 1) located on the opposite side of the surface 2a. Yes. The planar shapes of the WPP 1 and the semiconductor chip 2 are, for example, quadrangular as shown in FIG. In the present embodiment, a plurality of pads 2c are formed on the surface 2a of the semiconductor chip 2 along each side of the surface 2a.

  As shown in FIG. 2, the semiconductor chip 2 has a semiconductor substrate 2d which is a base material made of, for example, silicon (Si). A semiconductor element formation region is disposed on the main surface 2e of the semiconductor substrate 2d, and a plurality of semiconductor elements such as transistors and diodes are formed in the semiconductor element formation region. These semiconductor elements are each electrically connected to the plurality of pads 2c via wiring layers (first wiring layer, chip wiring layer) 2f formed on the main surface 2e. Specifically, the semiconductor element is connected via a plurality of internal wirings (not shown) formed in the wiring layer 2f and a plurality of surface wirings (wiring, uppermost layer wiring) 2g formed in the uppermost layer of the wiring layer 2f. Are electrically connected to the pad 2c. The pad 2c is formed integrally with the surface wiring 2g. The internal wiring formed in the wiring layer 2f is a buried wiring made of, for example, copper (Cu), and a groove or hole is formed in an interlayer insulating film formed in the wiring layer 2f, and copper or the like is formed in the groove or hole. After embedding a conductive metal material, the surface is polished to form a wiring, so-called damascene technology. Further, the interlayer insulating film of the wiring layer 2f is, for example, a silicon oxide film formed by plasma CVD (Chemical Vapor Deposition) using silicon oxide (SiOC) containing carbon or tetraethylorthosilicate (TEOS). Etc. The internal wiring of the wiring layer 2f forms an integrated circuit by electrically connecting a plurality of semiconductor elements, and a plurality of wiring layers 2f are stacked in order to secure a routing space for the wiring path. . The uppermost layer of the wiring layer 2f is formed with a pad 2c and a surface wiring 2g which are integrally formed with the pad 2c and electrically connect the plurality of pads 2c and the semiconductor element via the wiring layer 2f. The pad 2c and the surface wiring 2g are made of, for example, aluminum (Al), and are covered with an insulating layer 2k serving as a passivation film that protects the surface 2a. The insulating layer 2k is made of, for example, a semiconductor compound such as silicon oxide (SiO) or silicon nitride (SiN) in the same manner as the interlayer insulating film from the viewpoint of improving the adhesion between the wiring layer 2f and the interlayer insulating film. It is an inorganic insulating layer. Further, in order to use the pad 2c as an external terminal of the semiconductor chip 2, an opening is formed in the insulating layer 2k on the surface of the pad 2c, and the pad 2c is exposed from the insulating layer 2k in the opening.

  The WPP 1 has a rewiring layer (wiring layer, second wiring layer) 3 formed on the surface 2 a of the semiconductor chip 2. The rewiring layer 3 has a lower surface (main surface, back surface) 3b facing the surface 2a of the semiconductor chip 2 and an upper surface (main surface, surface) 3a opposite to the lower surface 3b (the same surface as the surface 1a of the WPP 1). is doing. A plurality of land portions (bump lands, electrode terminals) 3c are formed on the upper surface 3a, and a plurality of pads 2c of the semiconductor chip 2 are connected via a plurality of wirings (rewiring) 3d formed in the rewiring layer 3. , Each electrically connected. A solder ball 4 serving as an external terminal of the WPP 1 is joined to each land portion 3c. The solder material constituting the solder ball 4 is made of so-called lead-free solder that does not substantially contain lead (Pb). For example, only tin (Sn), tin-bismuth (Sn-Bi), or tin-copper -Silver (Sn-Cu-Ag) or the like. In this embodiment, a solder material made of tin-copper-silver (Sn-Cu-Ag) is used. Here, the lead-free solder means a lead (Pb) content of 0.1 wt% or less, and this content is defined as a standard of the RoHs (Restriction of Hazardous Substances) directive.

  In the WPP 1, the rewiring layer 3 is formed on the pad 2c to change the planar position of the solder ball 4 serving as an external terminal to a position different from that of the pad 2c. Since the position of the solder ball 4 can correspond to the arrangement of the terminal (not shown) of the mounting board on which the WPP 1 is mounted, the solder ball 4 can be connected to the terminal of the mounting board via the solder ball 4. That is, the mounting height can be reduced because the mounting board can be mounted on the mounting board without interposing a thick wiring board (interposer board) between the mounting board and the semiconductor chip 2. In addition, since the WPP 1 forms the rewiring layer 3 on the semiconductor chip 2, the planar dimension thereof can be the same as the planar dimension of the surface 2 a of the semiconductor chip 2. For this reason, the mounting area can be reduced as compared with a semiconductor device in which the semiconductor chip 2 is mounted on the interposer substrate.

  For example, the rewiring layer 3 of the present embodiment is configured as follows. That is, an insulating film (resin insulating film) 3 e made of an organic compound such as polyimide resin is formed on the insulating layer 2 k of the semiconductor chip 2. On the insulating film 3e, for example, a wiring 3d made of a conductive metal material in which a nickel film is laminated on copper is formed in a predetermined pattern. Here, the insulating film 3e is formed between the wiring 3d and the insulating layer 2k because, for example, there is a parasitic capacitance between the wiring 3d and the semiconductor element formed on the surface 2a of the semiconductor chip 2 or the surface wiring 2g. This is to prevent or suppress the formation of noise and the like, which cause deterioration of characteristics. Therefore, the insulating film 3e is preferably made of a material having a low dielectric constant. Accordingly, the insulating film 3e is made of a resin material such as polyimide resin, benzo-cyclobutene (BCB) film, or poly-benzo-oxazole (PBO) having a lower dielectric constant than the insulating layer 2k. From the viewpoint of preventing or suppressing the formation of parasitic capacitance, the insulating film 3e is preferably as thick as possible. For example, in the present embodiment, the thickness of the insulating film 3e is larger than the thickness of the insulating layer 2k disposed in the lower layer. Further, in order to electrically connect the wiring 3d and the pad 2c, at least a part of the pad 2c is exposed from the insulating film 3e. An insulating film (resin insulating film) 3f made of an organic compound such as polyimide resin is formed on the wiring 3d. The insulating film 3f is formed as a protective film that protects the wiring 3d from oxidation, corrosion, migration, short circuit, or damage. In addition, it is preferable to use a low elastic material from the viewpoint of absorbing and relaxing stress applied to the solder balls 4 that are external terminals after the WPP 1 is mounted on the mounting substrate. Therefore, in the present embodiment, the insulating film 3f is made of a resin material such as polyimide resin having lower elasticity than the insulating layer 2k. An opening is formed in a portion of the insulating film 3f that overlaps the wiring 3d, and the land 3c is exposed from the insulating film 3f in the opening. Solder balls 4 serving as external terminals of the WPP 1 are joined to the land portion 3c. That is, the wiring 3d functions as a lead wiring that changes the planar position of the external terminal of the WPP 1 to a position different from the pad 2c. The wiring 3d includes a bonding portion 3g bonded to the pad 2c, a land portion 3c bonded to the solder ball 4, and an extending portion 3h extending from the bonding portion 3g to the land portion 3c. The land portion 3c is formed with a width wider than that of the extending portion from the viewpoint of securing a large bonding area with the pad 2c and the solder ball 4 to be bonded, and improving the bonding reliability.

  As shown in FIG. 3, a mark 5 is formed on the back surface 1b of the WPP 1 as an identification mark for identifying the product name or model of the WPP 1. Since the mark 5 is an identification mark, it is preferably visible after the WPP 1 is mounted on the mounting board. For this reason, the mark 5 is formed on the back surface 1b which is the surface opposite to the front surface 1a which is the mounting surface of the WPP 1. In the present embodiment, a mark region (mark formation region) 5a (a hatched region in FIG. 3) for forming the mark 5 is arranged in the center on the back surface 1b. This is to prevent the mark 5 from being formed at the end portion of the back surface 1b and partially missing. However, as shown in FIG. 3, if the non-mark region 5b that does not form the mark 5 is provided around the mark region 5a, it is possible to prevent the mark 5 from being formed at the end of the back surface 1b. The arrangement of the mark area 5a is not limited to the central portion of the back surface 1b.

  Further, the mark 5 is configured so that the shape of the mark 5 can be visually recognized by changing the reflection state of the irradiated light by changing the surface roughness of the back surface 1 b as compared with the periphery of the mark 5. As shown in FIG. 4 which is an enlarged sectional view around the mark 5, the back surface 1b of the WPP 1 (the back surface of the semiconductor substrate 2d) is a fine uneven surface (for example, about 10 nm to 100 nm). Here, the mark 5 is formed by removing the protrusion on the back surface of the semiconductor substrate 2d and flattening it compared to the surrounding area. In other words, the flatness of the back surface 1b is higher in the region where the mark 5 is formed than in the region around the mark 5. Although details will be described later, in the present embodiment, the mark 5 is flattened by irradiating the back surface 1b with a laser and removing the convex portion on the back surface of the semiconductor substrate 2d. In this way, by flattening a part of the back surface 1b, the irradiated light 6 is less likely to be irregularly reflected in the flattened region, that is, in the region where the mark 5 is formed, as compared with the surroundings. For this reason, the amount of the reflected light 8a reaching the viewpoint 7 is smaller than the amount of the reflected light 8b reflected by the area around the mark 5, and the mark 5 appears darker (black) than the surrounding area. That is, a visible identification mark can be formed by forming the flattened region in a desired shape. As described above, in the present embodiment, the mark 5 is formed without using paint such as ink. Therefore, it is possible to prevent or suppress a part or all of the mark 5 from disappearing and becoming indistinguishable after the formation. it can. Further, from the viewpoint of improving the visibility of the mark 5 or preventing the durability of the WPP 1 from being lowered due to the depth of the mark 5 becoming too deep, the line width and depth of the mark 5 are: It is preferable to align with a predetermined dimension. The depth of the mark 5 is the height from the back surface 1b of the region where the mark 5 is formed to the apex of the convex portion formed in the region around the mark 5. In this embodiment, the line width and depth of the mark 5 are formed substantially uniformly. For example, the line width is about 30 μm to 60 μm, and the depth is about 0.01 μm to 0.5 μm.

<Manufacturing process of semiconductor device>
Next, the manufacturing process of WPP1 shown in FIGS. The WPP 1 in the present embodiment is manufactured along the assembly flow shown in FIG. FIG. 5 is an explanatory diagram showing an assembly flow of the semiconductor device of the present embodiment. Details of each step will be described below with reference to FIGS.

1. Semiconductor Wafer Preparation Step First, in the semiconductor wafer preparation step, a wafer (semiconductor wafer) 10 shown in FIGS. 6 and 7 is prepared. FIG. 6 is a plan view showing a plane on the main surface side of the semiconductor wafer prepared in the semiconductor wafer preparation step shown in FIG. FIG. 7 is an enlarged cross-sectional view showing a partial cross-sectional structure of the semiconductor wafer shown in FIG.

  The wafer 10 has a front surface 2a and a back surface 10b (see FIG. 7) located on the opposite side of the front surface 2a. The wafer 10 has a substantially circular planar shape, and the planar dimension is, for example, about 300 mm in diameter. The surface 2a of the wafer 10 corresponds to the surface 2a of the semiconductor chip 2 shown in FIG. The wafer 10 has a plurality of chip regions (device regions) 10a, and each chip region 10a corresponds to the WPP 1 shown in FIG. As shown in FIG. 7, in the plurality of chip regions 10a, the semiconductor elements included in the semiconductor chip 2, the wiring layer 2f, the surface wiring 2g, and the electrode pads (bonding pads) described with reference to FIGS. 2c is formed. Further, as shown in FIG. 6, a dicing region 10c is formed between adjacent chip regions 10a among the plurality of chip regions 10a. As shown in FIG. 6, the dicing area 10c is formed in a lattice shape, and divides the surface 2a of the wafer 10 into a plurality of chip areas 10a. Further, a direction identification unit (crystal axis direction identification unit) 10 d for identifying the crystal direction of the wafer 10 is formed at the peripheral portion of the wafer 10. FIG. 6 shows a so-called orientation flat structure in which a part of the arc of the wafer 10 having a substantially circular planar shape is removed along the string as an example of the direction identification unit 10d. The shape is not limited to this. For example, a notch (notch) may be formed in a part of the peripheral edge of the wafer 10. Further, in this stage of the process, the thickness of the wafer 10 (distance from the front surface 2a to the back surface 10b) is larger than the thickness of the semiconductor chip 2 shown in FIG. 2, for example, about 500 μm. Further, the mark 5 shown in FIG. 3 is not formed on the back surface 10b.

  The wafer 10 shown in FIG. 7 is formed as follows, for example. First, a semiconductor substrate 2d, which is a substantially circular wafer (for example, a silicon wafer) serving as a base material, is prepared, and a plurality of semiconductor elements are formed in a semiconductor element formation region of the main surface 2e. Next, a wiring layer 2f is formed on the main surface 2e, and a plurality of internal wirings and a plurality of semiconductor elements are electrically connected. Next, the surface wiring 2g and the pad 2c are formed on the upper surface of the wiring layer 2f. Since the surface wiring 2g is formed integrally with the pad 2c and is electrically connected to the plurality of internal wirings drawn to the upper surface of the wiring layer 2f, the plurality of pads 2c and the plurality of semiconductor elements are formed in this step. Electrically connected. Next, an insulating layer 2k is formed on the wiring layer 2f, and after covering the wiring layer 2f, an opening is formed by an etching method, and a part of the pad 2c is exposed from the insulating layer 2k. In the present embodiment, a configuration is shown in which the insulating layer 2k is not formed in the dicing region 10c. However, as a modification, the dicing region 10c may be covered with the insulating layer 2k.

2. Rewiring Layer Formation Step Next, as shown in FIG. 8, the rewiring layer 3 is formed on the wafer 10. FIG. 8 is an enlarged cross-sectional view showing a state in which a rewiring layer is formed on the semiconductor wafer shown in FIG.

  First, an insulating film (resin insulating film) 3 e made of, for example, a polyimide resin is formed on the surface 2 a of the wafer 10. Thereafter, an opening is formed in the insulating film 3e on the pad 2c to expose the pad 2c. Next, a conductor film (not shown) serving as a seed layer is formed on the insulating film 3e and the exposed surface of the pad 2c by, for example, sputtering. This conductor film is made of, for example, chromium (Cr) and constitutes a part of the wiring 3d. Next, after a resist film (not shown) is arranged on the conductor film and patterned, wiring (rewiring) 3d is formed by electrolytic plating in the presence of the resist film. In the present embodiment, for example, an electrolytic plating film of a copper (Cu) film and a nickel (Ni) film is sequentially formed. Thereby, the wiring 3d including the bonding portion 3g bonded to the pad 2c, the land portion 3c, and the extending portion 3h extending from the bonding portion 3g to the land portion 3c is formed. Next, unnecessary conductor films other than the region where the wiring 3d is formed are removed. Next, for example, an insulating film 3f made of an organic compound such as polyimide resin is formed. Thereafter, an opening is formed in the insulating film 3f on the land portion 3c, and the land portion 3c is exposed from the insulating film 3f. Through the above steps, the rewiring layer 3 is formed on the surface 2 a of the wafer 10 as shown in FIG. 8, and the upper surface 3 a of the rewiring layer 3 becomes the surface 1 a of the wafer 10. In the present embodiment, a configuration in which the insulating films 3e and 3f are not formed in the dicing region 10c is shown. However, as a modification, the dicing region 10c may be covered with the insulating films 3e and 3f. it can.

3. Back Surface Grinding Step Next, in the back surface grinding step, the back surface 10b (see FIG. 8) of the wafer 10 is ground. FIG. 9 is an explanatory view schematically showing a process of grinding the semiconductor wafer shown in FIG. FIG. 10 is a plan view showing the back side of the semiconductor wafer after the back grinding step, and FIG. 11 is a plan view showing the front side of the semiconductor wafer after the back grinding step.

  In this step, the back side is ground until the thickness of the wafer 10 reaches the thickness of WPP 1 shown in FIG. 2 (for example, 200 μm). As a method of reducing the thickness of the WPP 1, a semiconductor element, a wiring layer, and a rewiring layer thereon are formed on a semiconductor substrate in which the thickness of a wafer serving as a base material (a silicon wafer in the present embodiment) is thinned in advance. A method of sequentially forming the layers is also conceivable. However, in this case, if it is made extremely thin, in each process of forming a semiconductor element or the like on the wafer as a base material, the handling property is lowered, and the wafer is damaged. Therefore, in the present embodiment, in each process until the rewiring layer 3 is formed on the surface 2a side of the wafer 10, the wafer having a first thickness that can prevent the handling property from being deteriorated is processed. Then, the back surface 10b side is ground to a second thickness that is thinner than the first thickness. Thereby, the thickness of WPP1 obtained can be made thin, preventing the damage of the wafer in a manufacturing process.

  The grinding method in this step is not particularly limited. For example, the back surface 10b of the wafer 10 is ground using a grinding member 11 such as a grindstone as shown in FIG. For example, as shown in FIG. 9, the grinding member 11 is pressed against the back surface 10b of the wafer 10 and both the grinding member 11 and the wafer 10 are rotated to grind the entire back surface 10b. Further, as shown in FIG. 9, grinding is performed with a protective tape 14 covering the surface 1a side of the wafer 10, that is, the surface (upper surface 3a) on which the rewiring layer 3 shown in FIG. Thereby, the surface 1a side can be protected from damage due to application of external force during the grinding process. When the wafer 10 reaches a predetermined thickness (for example, 200 μm), the grinding process is finished, the protective tape 14 is peeled off from the surface 1a of the wafer 10, and then stored in a wafer rack (not shown) for the next process (this embodiment). Then, it is conveyed to a mark forming step.

  When this step is completed, the back surface 10b of the wafer 10 shown in FIG. 8 is ground, and as shown in FIG. 10, the back surface 1b in which the mark regions 5a are arranged in each of the plurality of chip regions 10a is exposed. On the other hand, on the surface 1a side shown in FIG. 11, a wafer 10 is obtained in which a plurality of land portions (electrode terminals) 3c are formed in each of a plurality of chip regions 10a. In addition, alignment marks (alignment patterns) 12 that are recognition marks for aligning the wafer 10 are formed at a plurality of locations on the front surface 1a side of the wafer 10 in a mark forming process described later. In this embodiment, since the back surface 1b of the wafer 10 is ground, even if the alignment mark 12 is formed on the back surface 10b (see FIG. 8) side, it is removed in the back surface grinding process. For this reason, the alignment mark 12 is formed on the surface 1a side. Further, in the mark formation process, if the position and direction (orientation) of the entire wafer 10 can be detected, alignment can be performed based on this. For this reason, a part of land part 3c formed in the surface 1a side can also be used as an alignment mark. Further, when the insulating films 3e and 3f (see FIG. 8) are made of a visible light transmitting material (a material that transmits visible light) such as polyimide resin as in the present embodiment, the insulating films 3e and 3f are formed in a lower layer than the insulating film 3f. The formed wiring (rewiring) 3d, the pad 2c (see FIG. 8), or the like can also be used as an alignment mark. Thus, in order to use each member formed on the surface 1a side as an alignment mark, unlike the present embodiment, the alignment mark is formed on the surface 1a side even when the back grinding process is not performed. It is preferable that As shown in FIG. 11, when the alignment mark 12 is formed at a plurality of positions different from the land portion 3c, for example, when the wiring 3d (see FIG. 8) is formed in the rewiring layer forming step described above. In addition, the alignment marks 12 made of the same conductive material as that of the wiring 3d can be collectively formed. Alternatively, in the semiconductor wafer preparation step, an alignment mark (alignment pattern) exposed from the insulating layer 2k may be formed in advance on the surface 2a of the wafer 10 shown in FIG.

4). Mark Forming Step Next, in the mark step, as shown in FIG. 12, the laser is irradiated on the back surface 1b side of the semiconductor wafer 10 to each mark area 5a (see FIG. 10) provided on the back surface 1b of the wafer 10. , Mark 5 (see FIG. 3) is formed. FIG. 12 is an explanatory view schematically showing an outline of a process of forming a mark on the back surface of the semiconductor wafer shown in FIG.

  Hereinafter, after describing the outline of the mark forming process, the structure and detailed flow of the mark forming apparatus used in the mark forming process will be described. In this step, as shown in FIG. 12, first, the stage 20 is prepared, and the wafer 10 is placed on the upper surface 20a of the stage 20 (wafer placement step shown in FIG. 5). In the present embodiment, the rear surface 1 b of the wafer 10 is disposed so as to face the upper surface 20 a of the stage 20. Subsequently, the wafer 10 was sucked and fixed on the stage 20 (wafer fixing step shown in FIG. 5: details of the suction fixing method will be described later), and the wafer 10 was formed on the surface 1a of the wafer 10 in a fixed state. The alignment mark 12 (see FIG. 11) is recognized (alignment mark recognition step shown in FIG. 5). The alignment marks are recognized by, for example, recognizing the alignment marks 12 (see FIG. 11) formed at a plurality of locations on the surface 1a of the wafer 10 using the imaging device 15 such as a CCD camera shown in FIG. The position of is detected. In the present embodiment, the alignment mark 12 (see FIG. 11) is formed on the surface 1a side as described above, and the wafer 10 is fixed in a state where the surface 1a faces upward of the stage 20. For this reason, the imaging device 15 is disposed above the stage 20 and recognizes the alignment mark 12 (see FIG. 11) from above the wafer 10. Then, based on the recognized position data of the alignment mark 12 (see FIG. 11), for example, the stage 20 to which the wafer 10 is fixed is moved to align the back surface 1b of the wafer 10 with the laser light source 16 (see FIG. 11). Wafer alignment process shown in FIG. Next, the laser beam 16a is irradiated toward the back surface 1b of the wafer 10, and the mark 5 (in the mark region 5a formed in each of the plurality of chip regions 10a on the back surface 1b of the wafer 10 shown in FIG. (See FIG. 3) is formed (laser irradiation step shown in FIG. 5). In the present embodiment, as shown in FIG. 12, since the back surface 1b of the wafer 10 is fixed so as to face the upper surface 20a of the stage 20, the laser light 16a is transmitted (transmitted) through the stage 20. The back surface 1b of the wafer 10 is irradiated. For this reason, the laser light source 16 is disposed below the stage 20.

  As shown in FIG. 12, when the front surface 1a and the back surface 1b of the wafer 10 form a substantially flat surface, the plurality of chip regions 10a on the back surface 1b of the wafer 10 shown in FIG. The marks 5 (see FIG. 3) can be formed substantially uniformly in the mark regions 5a formed in each. However, a thin plate material such as the wafer 10 undergoes so-called warpage deformation that deforms in the out-of-plane direction of the front surface 1a and the back surface 1b, as shown in FIG. FIG. 13 is a perspective view showing the shape of the semiconductor wafer after the back grinding process.

  In the wafer 10 of the present embodiment, one surface (surface 1a) is covered with an insulating film (for example, insulating films 3e and 3f shown in FIG. 8) having a linear expansion coefficient larger than that of the semiconductor substrate, and the opposite surface. The semiconductor substrate is exposed on the (back surface 1b). Thus, when only one surface of the wafer 10 is covered with a film made of a material having a different linear expansion coefficient, the amount of warpage of the wafer 10 increases. Further, when the back surface 10b of the wafer 10 is ground as in the present embodiment, the warpage amount of the wafer 10 after the back surface grinding process is further increased than before the back surface grinding process. If the height difference between the lowest point of the back surface 1b and the highest point of the back surface 1b shown in FIG. 13 is defined as the amount of warpage, for example, the wafer 10 of this embodiment having a diameter of about 300 mm and a thickness of about 200 μm. The amount of warpage is about 2 mm to 4 mm. This is because stress that causes warping deformation is generated in the wafer 10 before the back surface grinding process is performed. By reducing the thickness of the wafer 10, the wafer 10 cannot withstand the stress, and the amount of warping is increased. It is thought to increase. Further, when the insulating films 3e and 3f (see FIG. 8) covering the surface 1a have a larger linear expansion coefficient than the semiconductor substrate 2d (see FIG. 8) as in the present embodiment, the deformation direction of the warp deformation is as shown in FIG. As shown in FIG. That is, when the surface 1a of the wafer 10 is disposed facing upward, each of the cross sections along one center line (virtual line) 13 passing through the center of the surface 1a is closer to the center side than the end side. The wafer 10 is warped and deformed so as to form a concave shape arranged at a low position.

  Thus, it has been found that when the identification mark is formed on the warped wafer 10 by laser irradiation, the following problems occur. First, in the case of a structure in which the space formed on the stage is covered with a semiconductor wafer and covered, such as the vacuum suction device described in Patent Document 1 and the vacuum chuck device described in Patent Document 2, the wafer 10 A gap is created between the stage 10 and the stage, making it difficult to suck the wafer 10 disposed. For this reason, the wafer 10 moves on the stage, and the alignment accuracy decreases. In addition, since the accuracy of the position irradiated with the laser is lowered, it becomes difficult to correctly form the identification mark at a predetermined position. That is, the accuracy of processing performed on the wafer 10 is reduced.

  Further, when the above-described laser irradiation process or alignment mark recognition process is performed in a state where the wafer 10 is warped, the focal length of the laser beam 16a and the imaging device 15 shown in FIG. In the inner surface or the rear surface 1b), the laser processing accuracy or the alignment accuracy is deteriorated. For example, when the alignment mark recognition process is performed on the wafer 10 shown in FIG. 13, when the focal length of the imaging device 15 is adjusted to an area near the center line 13, the focus is adjusted near the end away from the center line 13. This will cause a recognition failure of the alignment mark. Conversely, when the focal length of the imaging device 15 is adjusted to the vicinity of the end away from the center line 13, the focus is not achieved in the area near the center line 13, which causes alignment mark recognition failure. Further, for example, when the laser irradiation process is performed on the wafer 10 shown in FIG. 13, if the focal length of the laser beam 16 a (see FIG. 12) is adjusted to the vicinity of the end away from the center line 13, In the region, the processing energy of the laser beam 16a is insufficient, the line width of the mark 5 shown in FIG. 4 is narrowed, and the depth of the mark 5 is shallow. As a result, the difference in surface roughness of the back surface 1b cannot be made sufficiently as compared with the periphery of the mark 5, which causes the visibility of the mark 5 to deteriorate. Conversely, when the focal length of the laser beam 16a (see FIG. 12) is adjusted to the region near the center line 13, the processing energy of the laser beam 16a becomes excessively large near the end away from the center line 13. As a result, the depth of the mark 5 shown in FIG. 4 becomes deeper than necessary, causing the wafer 10 to be damaged.

  From the viewpoint of solving the above problems, firstly, a technique capable of firmly adsorbing and fixing the wafer 10 on the stage 20 is required before performing the alignment mark recognition process. Secondly, a technique is required that can correct the wafer 10 in which warp deformation has occurred and flatten it along the upper surface 20 a of the stage 20. Based on these, the mark forming process of the present embodiment will be described in detail below. FIG. 14 is an explanatory diagram showing a schematic configuration of a mark forming apparatus used in the mark forming process of the present embodiment. FIG. 15 is a cross-sectional view showing a state in which a plurality of wafers are mounted on the wafer rack arranged in the wafer rack arrangement section shown in FIG.

  A mark forming apparatus 30 shown in FIG. 14 includes a wafer rack placement unit 31 that serves as a loader unit or unloader unit of the wafer 10. In the present embodiment, from the viewpoint of improving the processing efficiency of the wafer 10, a plurality (three in FIG. 14) of wafer rack placement units 31 are provided. For example, as shown in FIG. 15, a wafer rack (wafer cassette) 32 in which a plurality of shelves are stacked in the height direction is arranged in the wafer rack placement unit 31. A plurality of wafers 10 subjected to the grinding process on the back surface side in the back surface grinding process described above are mounted on the wafer rack 32 and conveyed to the mark forming apparatus 30 (loading process shown in FIG. 5). Each of the plurality of wafers 10 is stacked on the wafer rack 32 with the surface 1a facing upward.

  Further, the mark forming apparatus 30 includes a handler (conveying jig) 35 that is a wafer conveying unit that conveys the wafer 10 in the mark forming apparatus 30. The handler 35 includes a holding unit 35 a that holds the wafer 10 by suction, for example, and includes a transfer mechanism that transfers the held wafer 10 between the wafer rack placement unit 31, the pre-aligner 33, and the mark forming unit 34. Yes.

  In addition, the mark forming apparatus 30 includes a pre-aligner (positioning unit) 33 that recognizes the direction identification unit 10d (see FIG. 6) of the wafer 10 and aligns the handler 35 and the wafer 10. For example, the wafers 10 taken out one by one from the wafer rack 32 are transferred to the pre-aligner 33 by the handler 35 and placed on a stage (pre-aligned stage) 33a. The position of the direction identification unit 10d (see FIG. 6) of the wafer 10 is detected by the position detection unit 33b arranged on the stage 33a of the pre-aligner 33 (pre-alignment step shown in FIG. 5). As a result, the planar positional relationship between the wafer 10 and the handler 35 (specifically, the holding portion 35a of the handler 35) can be aligned, so that the wafer 10 is transferred from the pre-aligner 33 onto the stage 20 of the mark forming portion 34, When the wafers 10 are arranged, the wafer 10 can be arranged in a predetermined positional relationship described later.

  Further, the mark forming apparatus 30 includes a mark forming unit 34 that forms the mark 5 (see FIG. 3) by irradiating the laser beam 16a (see FIG. 12) from the back surface 1b (see FIG. 12) of the wafer 10. ing. The mark forming unit 34 is a dark room, and a stage (laser marking stage) 20 for fixing the wafer 10 is disposed in the dark room. The stage 20 is fixed to a table (XY table) 36 that can move in the horizontal direction (XY direction).

  Here, details of the stage 20 will be described. 16 is a plan view showing the upper surface side of the stage disposed in the mark forming portion shown in FIG. 14, and FIG. 17 is a cross-sectional view taken along the line BB in FIG.

  As shown in FIG. 17, the stage 20 is configured by arranging two glass plates (members) 21 and 22 to face each other through a hollow space (a plurality of chambers). The glass plate 21 disposed in the upper stage has an upper surface that is the upper surface 20a of the stage 20, and a lower surface 21b opposite to the upper surface 20a. Moreover, the glass plate 22 arrange | positioned at the lower stage has the upper surface 22a facing the lower surface 21b of the glass plate 21, and the lower surface 22b on the opposite side to the upper surface 22a. For example, a partition member 23 made of a glass material is arranged between the glass plates 21 and 22, and the glass plates 21 and 22 are partitioned into a plurality of chambers (spaces) 24. In the present embodiment, between the glass plates 21 and 22, two chambers comprising a chamber (space) 24 a disposed at a substantially central portion of the stage 20 and a chamber (space) 24 b disposed around the chamber 24 a. 24 is provided. A frame body (frame portion) 26 made of, for example, a resin material or a glass material and holding the glass plates 21 and 22 is disposed on the outer peripheral side of the chamber 24b. The outer edge of the chamber 24b is defined by the frame body 26. Has been. In the present embodiment, each of the glass plates 21 and 22 has a circular shape in plan view, and the size thereof is larger than that of the wafer 10 (see FIG. 12). For example, the diameter of the glass plates 21 and 22 is about 301 mm to 400 mm with respect to the wafer 10 having a diameter of about 300 mm. In the present embodiment, although not shown, since the positioning (alignment) is performed when the wafer 10 is placed on the stage 20, the diameters of the glass plates 21 and 22 are substantially the same as the diameter of the wafer 10. It may be.

  Further, as shown in FIG. 16, a plurality of suction holes (openings) 25 are formed in the glass plate 21. Specifically, in plan view, a plurality of suction holes 25 a are formed in a region overlapping the chamber 24 a of the glass plate 21, and a plurality of suction holes 25 b are formed in a region overlapping the chamber 24 b of the glass plate 21. These suction holes 25 are formed from one surface to the other surface of the upper surface 20a and the lower surface 21b of the glass plate 21, and are formed so as to penetrate the glass plate 21 in the thickness direction. Therefore, the plurality of suction holes 25a are connected to the chamber 24a, and the plurality of suction holes 25b are connected to the chamber 24b. The plurality of suction holes 25 of the present embodiment have a cylindrical shape with a diameter of about 1 mm, for example. The chamber 24 is connected to a suction path 27 that serves as an exhaust path for sucking the gas in the chamber 24 and decompressing the chamber 24. Specifically, the chamber 24a is connected to a suction path 27a connected to a pump (vacuum pump) P1 via a pipe L1 and a valve V1. On the other hand, the chamber 24b is connected to a suction path 27b connected to a pump (vacuum pump) P2 via a suction path different from the suction path 27a, for example, a pipe L2 and a valve V2. That is, the chambers 24a and 24b have a structure that can be decompressed independently.

  Next, each process performed on the stage 20 shown in FIGS. 16 and 17, that is, the wafer placement process, the wafer fixing process, the alignment mark recognition process, the wafer alignment process, and the laser irradiation process shown in FIG. 5 will be described in order. . FIG. 18 is a cross-sectional view showing a process of placing a wafer on the stage shown in FIG. 19 is a sectional view showing a state in which the back surface of the wafer shown in FIG. 18 is sucked and fixed to the suction hole on the inner peripheral side of the stage. FIG. 20 is a suction term in which the back surface of the wafer shown in FIG. It is sectional drawing which shows the state adsorbed and fixed to. FIG. 21 is a plan view showing a state where the wafer is seen through from the lower surface side of the stage shown in FIG. In FIG. 21, in order to make it easy to see the planar positional relationship between the mark region 5a on the back surface 1b of the wafer 10, the plurality of suction holes 25 formed in the stage 20, and the partition member 23, the suction holes 25 and the partition member are shown. 23 is shown with a dot pattern.

  After the alignment of the handler 35 shown in FIG. 14 is performed in the pre-alignment step, the wafer 10 is held by the holding portion 35a of the handler 35 and transferred onto the stage 20 as shown in FIG. In this embodiment, the wafer 10 is arranged on the stage 20 so that the upper surface 20a of the stage 20 and the back surface 1b of the wafer 10 face each other (wafer arrangement process). At this time, the mark region 5a (see FIG. 21) on the back surface 1b of the wafer 10 is arranged so as not to overlap the plurality of suction holes 25 and the partition member 23 in plan view. Specifically, as shown in FIG. 21, when the wafer 10 is fixed to the stage 20, the plurality of mark regions 5 a on the back surface 1 b of the wafer 10 do not overlap with the plurality of suction holes 25 and the partition member 23 in plan view. To place. In the present embodiment, in the pre-alignment step, the direction identification unit 10d (see FIG. 6) of the wafer 10 is detected. Further, on the back surface 1b of the wafer 10, the mark areas 5a are regularly arranged. For this reason, when transported onto the stage 20 and placed on the stage 20, the control unit 30a (see FIG. 14) of the mark forming apparatus 30 (see FIG. 14) stores the position data of the plurality of mark regions 5a on the wafer 10. It can be calculated from the position data of the direction identification unit 10d. Then, the wafer 10 can be placed at a predetermined position on the stage 20 by moving the wafer 10 via the handler 35 based on the calculated position data of the mark area 5a. That is, when the wafer 10 is fixed to the stage 20, the plurality of mark regions 5 a on the back surface 1 b of the wafer 10 can be arranged so as not to overlap the plurality of suction holes 25 and the partition member 23 in plan view.

  Next, as shown in FIG. 20, the back surface 1b side of the wafer 10 is sucked through the plurality of suction holes 25, and the wafer 10 is fixed to the upper surface 20a of the stage 20 (wafer fixing step). Here, as shown in FIG. 18, the warp deformation of the wafer 10 is not corrected only by placing the wafer 10 on the stage 20. For this reason, a gap of about 2 mm to 4 mm is generated between the back surface 1 b of the wafer 10 and the upper surface 20 a of the stage 20 in the vicinity of the peripheral edge of the wafer 10. In this state, among the plurality of suction holes 25 formed in the stage 20, the gap between the suction hole 25 b arranged on the outer peripheral side and the back surface 1 b of the wafer 10 is wide. It is difficult to firmly adsorb and fix.

  Therefore, in the present embodiment, a plurality of suction holes 25a are formed inside the suction holes 25b. Since the warpage amount of the warpage deformation generated in the wafer 10 increases toward the peripheral portion of the wafer 10 as described above, the warpage amount becomes smaller as the center of the wafer 10 is approached. For this reason, the gap between the suction hole 25 a and the back surface 1 b of the wafer 10 is smaller than the gap between the suction hole 25 b and the back surface 1 b of the wafer 10, and suction is facilitated. For example, in the present embodiment, a plurality of suction holes 25a are arranged on the upper surface 20a of the stage 20 closer to the center side than the center of the area where the wafer 10 is mounted and the suction holes 25b. As described above, when the inside of the chamber 24a is depressurized by the stage 20 in which the plurality of suction holes 25a are formed inside the suction holes 25b, the back surface 1b of the wafer 10 becomes a plurality of suction holes 25a as shown in FIG. Adsorbed and fixed. At this time, the warp deformation of the wafer 10 is corrected following the upper surface 20a of the stage 20 by the suction force of the suction holes 25a. By this correction, the distance between the back surface 1b and the suction hole 25b approaches the peripheral edge of the wafer 10. When the inside of the chamber 24b is depressurized with the distance between the back surface 1b and the suction hole 25b approaching, the back surface 1b of the wafer 10 is attracted and fixed to the plurality of suction holes 25b as shown in FIG. At this time, warping deformation is corrected along the upper surface 20a of the stage 20 even in the peripheral portion of the wafer 10 by the suction force of the suction holes 25b. In other words, the warping deformation of the wafer 10 can be corrected and the back surface 1b can be flattened by this step. Thereby, the whole back surface 1b of the wafer 10 can be firmly adsorbed and fixed.

  When the wafer 10 is sucked and sucked from the opening formed in the stage 20, the suction force increases as the opening area of the opening decreases. In other words, by forming openings (suction holes 25) having a small opening area at a plurality of locations, even if a gap is formed between the back surface 1b of the wafer 10, it is possible to perform suction fixing. For example, as described above, the opening area of each of the plurality of suction holes 25 according to the present embodiment is made equal to the area of a circle having a diameter of about 1 mm. Even if there is a gap of about 0.7 mm, it can be adsorbed. Further, since the suction force of each suction hole 25 increases, the warp deformation of the wafer 10 can be corrected efficiently.

  In addition, when the suction holes 25b arranged on the outer peripheral side of the stage 20 and the suction holes 25a arranged on the inner peripheral side are connected, the inflow of gas from the suction holes 25b having a wide distance from the back surface 1b of the wafer 10. Since the amount increases, the suction force of the suction hole 25a is relatively smaller than the suction force of the suction hole 25b. As described above, in this embodiment, the partition member 23 is disposed between the chamber 24a to which the suction hole 25a is connected and the chamber 24b to which the suction hole 25b is connected. The chambers 24a and 24b are independent of each other. The pressure can be reduced. For this reason, it is possible to prevent or suppress a decrease in the suction force of the plurality of suction holes 25a.

  By the way, in this Embodiment, the chambers 24a and 24b can be pressure-reduced independently. For this reason, in addition to the embodiment in which the chambers 24a and 24b are decompressed simultaneously, the timing of decompressing the chambers 24a and 24b can be shifted. For example, the pressure in the chamber 24a can be reduced first, the back surface 1b of the wafer 10 can be adsorbed by the suction holes 25a to correct the warp deformation, and then the pressure reduction in the chamber 24b can be started. In this case, the suction order for sucking the back surface 1b of the wafer 10 can be surely set in the order of the plurality of suction holes 25a and the plurality of suction holes 25b. When the warp deformation of the wafer 10 is corrected by the suction force of the suction holes 25 as in the present embodiment, the wafer 10 may be distorted during correction. The larger the amount of deformation of the wafer 10 at the time of correction (the amount of deformation to deform so as to follow the upper surface 20a of the stage 20), the larger the amount of distortion. For this reason, for example, when the peripheral portion of the wafer 10 is first adsorbed and then the peripheral portion opposite to the adsorbed peripheral portion is adsorbed, the amount of distortion of the peripheral portion to be adsorbed later increases. Therefore, from the viewpoint of reducing the distortion amount of the wafer 10 at the time of correction, it is preferable that the suction order for sucking the back surface 1b of the wafer 10 is in order of the plurality of suction holes 25a and the plurality of suction holes 25b. That is, the pressure in the chamber 24a is first reduced, the back surface 1b of the wafer 10 is adsorbed by the suction holes 25a to correct the warp deformation, and then the pressure in the chamber 24b is started to reduce the amount of distortion generated in the wafer 10. Can be reduced. However, when the degree of warpage deformation of the wafer 10 is small and the amount of distortion of the wafer 10 generated during correction is so small that it can be ignored in terms of product reliability, the chambers 24a and 24b can be decompressed simultaneously. Even in this case, if the wafer 10 is arranged on the stage 20 so that the center of the back surface 1b of the wafer 10 is located at the lowest position, the plurality of suction holes 25a are arranged in front of the plurality of suction holes 25b. Adsorb 1b.

  In the present embodiment, each of the plurality of suction holes 25a and 25b is arranged concentrically with reference to the center of the area on the stage 20 where the wafer 10 is mounted. In other words, the plurality of suction holes 25 a are arranged along a first circle centered on the center (front surface 1 a or back surface 1 b) of the wafer 10 mounted on the stage 20. The plurality of suction holes 25b are arranged along a second circle having the center (on the front surface 1a or the back surface 1b) of the wafer 10 mounted on the stage 20 as a center and a radius larger than that of the first circle. Has been. Note that the radius of the first circle in the present embodiment is less than half of the radius of the second circle. As described above, the distance from the center of the wafer 10 to the plurality of suction holes 25a, or the distance from the center of the wafer 10 to the plurality of suction holes 25b, is approximately the same along the circle centered on the center of the wafer 10. can do. The amount of warpage of the warpage deformation occurring in the wafer 10 increases toward the peripheral edge of the wafer 10 as described above. For this reason, if the distances from the center of the wafer 10 to the plurality of suction holes 25a are made substantially the same, the distances from the suction holes 25a to the back surface 1b of the wafer 10 can be kept below a certain value. For this reason, the malfunction that the wafer 10 is not adsorbed by a part of the plurality of suction holes 25a can be prevented or suppressed. Similarly, if the distances from the center of the wafer 10 to the plurality of suction holes 25b are made approximately the same, the distance from the suction holes 25b to the back surface 1b of the wafer 10 can be kept below a certain value. For this reason, it is possible to prevent or suppress the problem that the wafer 10 is not adsorbed by a part of the plurality of suction holes 25b. Thus, each of the plurality of suction holes 25a and 25b is arranged concentrically with the center of the region where the wafer 10 of the stage 20 is mounted as a reference, so that the plurality of suction holes 25 The problem that the wafer 10 is not attracted in part can be prevented or suppressed. As a result, the wafer 10 can be firmly fixed on the stage 20 by suction. Further, the warp deformation generated in the wafer 10 can be reliably corrected, and the back surface 1b of the wafer 10 can be made a flat surface following the upper surface 20a of the stage 20.

  In the present embodiment, the embodiment has been described in which the pressure in the chambers 24a and 24b is reduced after the wafer 10 is placed on the stage 20, but the timing for reducing the pressure in the chambers 24a and 24b is not limited thereto. For example, as shown in FIG. 18, the pressure reduction in the chamber 24 a can be started before the wafer 10 is placed on the stage 20 or at the same time when the wafer 10 is placed on the stage 20. However, when the wafer 10 is placed on the stage 20, pressure reduction in the chamber 24b is started from the viewpoint of preventing a part of the back surface 1b of the wafer 10 from being sucked and fixed to the suction hole 25b first. This is preferably after the back surface 1b of the wafer 10 is adsorbed by the plurality of suction holes 25a.

  Next, in a state where the wafer 10 is fixed, the alignment mark 12 (see FIG. 11) formed on the surface 1a of the wafer 10 is recognized (alignment mark recognition step). FIG. 22 is a cross-sectional view showing a process of recognizing the alignment mark on the surface of the wafer shown in FIG. In this step, for example, as shown in FIG. 22, the illumination light 17a is irradiated from the illumination device 17 toward the surface 1a of the wafer 10, and the reflected light 17b from the wafer 10 is imaged by the imaging device 15 to perform alignment. The position and orientation of the mark 12 (see FIG. 11) are detected with higher accuracy than in the pre-alignment step. In FIG. 22, for example, as the illumination device 17, an example is shown in which ring illumination that irradiates illumination light 17 a toward the surface 1 a of the wafer 10 from an annular light source is illustrated. In this step, the position and orientation of alignment marks 12 (see FIG. 11) formed at a plurality of locations are detected on the surface 1a side of the wafer 10, respectively.

  Here, as described above, when the alignment mark recognition process is performed with the wafer 10 warped as shown in FIG. 18, for example, the focal length of the imaging device 15 shown in FIG. In the surface 1a), the detection accuracy of the position and orientation of the alignment mark is lowered because it is not constant. However, according to the present embodiment, it is possible to correct the warpage generated in the wafer 10 before the alignment mark recognition step, and therefore it is possible to prevent or suppress a decrease in detection accuracy. As a result, in the subsequent wafer alignment step, the alignment accuracy of the stage 20 to which the wafer 10 is fixed can be performed with high accuracy.

  Next, for example, the stage 20 to which the wafer 10 is fixed is moved based on the recognized position data of the alignment mark 12 (see FIG. 11) (position and orientation data of a plurality of alignment marks on the wafer 10). The back surface 1b of the wafer 10 and the laser light source 16 (see FIG. 12) are aligned (wafer alignment process). In this step, the stage 20 and the wafer 10 fixed to the stage 20 are moved to a predetermined position by moving, for example, a table (XY table) 36 to which the stage 20 shown in FIG. 14 is fixed in the horizontal direction. be able to. Further, in the alignment mark recognition step, the position accuracy of the alignment mark 12 can be improved by detecting the position data of the alignment mark 12 with high accuracy.

  Next, as shown in FIG. 23, a laser beam 16a is irradiated toward the back surface 1b of the wafer 10 to form mark areas formed in each of the plurality of chip regions 10a on the back surface 1b of the wafer 10 shown in FIG. A mark 5 (see FIG. 24) is formed in 5a (laser irradiation step). 23 is a cross-sectional view showing a state in which the laser beam is irradiated on the back surface side of the wafer shown in FIG. 22, and FIG. 24 is an enlarged cross-sectional view showing the periphery of the back surface side of the wafer shown in FIG.

  As shown in FIG. 24, the back surface 1b of the wafer 10 (the back surface of the semiconductor substrate 2d) is a fine uneven surface (for example, about 10 nm to 100 nm). In this step, the mark 5 is formed by removing a part of the convex portion on the back surface of the semiconductor substrate 2d and flattening it compared to the surroundings. Here, as described above, from the viewpoint of improving the visibility of the mark 5, or from the viewpoint of preventing the durability of the WPP 1 (see FIG. 1) from being lowered due to the depth of the mark 5 becoming too deep. The line width and depth of the mark 5 are preferably aligned with predetermined dimensions. In order to align the line width and depth of the mark 5 within predetermined dimensions, it is preferable to align the focal lengths of the laser beams 16a.

  Here, for example, when the laser beam 16a is irradiated with the wafer 10 warped as shown in FIG. 18, the focal length of the laser beam 16a is not constant in the plane of the wafer 10 (in the back surface 1b). Therefore, it becomes difficult to align the line width and depth of the mark 5 within predetermined dimensions. That is, the processing accuracy by the laser beam 16a is lowered. However, according to the present embodiment, it is possible to correct the warp generated in the wafer 10 before the laser irradiation step, and thus it is possible to prevent or suppress a decrease in processing accuracy due to the laser light 16a.

  Further, from the viewpoint of aligning the line width and depth of the mark 5 within predetermined dimensions, it is preferable to reduce the processing energy required for forming the mark 5 and to reduce the width of the processing energy variation. Hereinafter, the aspect of the present embodiment for reducing the variation width of the processing energy of the laser beam 16a forming the mark 5 will be described in more detail.

  As shown in FIG. 23, in the present embodiment, since the back surface 1b of the wafer 10 is disposed opposite to the upper surface 20a of the stage 20, the laser light 16a passes through (transmits) the stage 20 and passes through the wafer 10. The back surface 1b is irradiated. Specifically, the laser beam 16 a passes through the glass plates 21 and 22 of the stage 20 and the hollow space (chamber 24) between the glass plates 21 and 22 and is irradiated to the back surface 1 b of the wafer 10.

For this reason, at least the glass plates 21 and 22 among the constituent members of the stage 20 are made of a material that is transparent to the laser beam 16a. Here, the material transparent to the laser beam 16a is compared with a portion to be processed of the wafer 10 that does not absorb the laser beam 16a or is a processing target (specifically, for example, a semiconductor substrate made of single crystal silicon). Thus, it refers to a material with sufficiently low absorption efficiency of the laser beam 16a. In this embodiment, a glass material containing silicon oxide (SiO ₂ ) as a main material is used. In this way, when the glass plates 21 and 22 are made of a material whose absorption efficiency of the laser beam 16a is lower than that of the processed portion of the wafer 10, a part of the laser beam 16a passes through the glass plates 21 and 22. The energy of the laser beam 16a that is absorbed by the laser beam 16b and reaches the back surface 1b, that is, the variation width of the processing energy for forming the mark 5 shown in FIG. 24 can be reduced.

  Further, from the viewpoint of suppressing reflection or refraction of the laser beam 16a when passing through the glass plates 21 and 22, the upper surface 20a and the lower surface 21b of the glass plate 21, the upper surface 22a and the lower surface 22b of the glass plate 22 have high flatness. It is preferable to have. In the present embodiment, the flatness of the upper surface 20 a and the lower surface 21 b of the glass plate 21, the upper surface 22 a and the lower surface 22 b of the glass plate 22 is equal to or higher than the flatness of the back surface 1 b of the wafer 10. Thereby, since reflection or refraction of the laser beam 16a when passing through the glass plates 21 and 22 can be suppressed, the energy of the laser beam 16a reaching the back surface 1b of the wafer 10, that is, the mark 5 shown in FIG. It is possible to reduce the width of variation in the processing energy that forms.

  Similarly, from the viewpoint of suppressing reflection or refraction of the laser beam 16a when passing through the stage 20, it is preferable that the laser beam 16a does not pass through the partition member 23 or the suction hole 25. For this reason, in the present embodiment, when the wafer 10 is fixed to the stage 20 in the wafer placement step, a plurality of mark regions 5a on the back surface 1b of the wafer 10 are plural in plan view as shown in FIG. The suction hole 25 and the partition member 23 are arranged so as not to overlap. Thereby, since reflection or refraction of the laser beam 16a when passing through the stage 20 can be suppressed, the energy of the laser beam 16a reaching the back surface 1b of the wafer 10, that is, the mark 5 shown in FIG. 24 is formed. The range of variation in processing energy can be reduced.

  Moreover, in this Embodiment, the partition member 23 is comprised with the glass material. For this reason, even if the laser beam 16a passes through the partition member 23, the partition member 23 can suppress a part of the laser beam 16a from being absorbed. However, even if the partition member 23 is made of a glass material, if the laser beam 16a passes through the partition member 23, there is a concern that the energy of the laser beam 16a reaching the back surface 1b of the wafer 10 may vary due to reflection or refraction. is there. As shown in FIG. 21, if the plurality of mark regions 5a on the back surface 1b of the wafer 10 are arranged so as not to overlap the partition member 23 in plan view, this can be prevented or suppressed. As a specific mode for disposing the plurality of mark regions 5a on the back surface 1b of the wafer 10 so as not to overlap the partition member 23 in plan view, in the present embodiment, as shown in FIG. The wafer 10 is arranged on the stage 20 so that the dicing area 10c is positioned on the partition member 23. Since the plurality of mark regions 5a are respectively formed in the plurality of chip regions 10a of the wafer 10 as described above, by arranging the partition member 23 and the dicing region 10c so as to overlap, in the laser irradiation step, It is possible to prevent or suppress the laser light 16a from passing through the partition member 23.

  As shown in FIG. 16, in the stage 20, in order to connect the chamber 24a arranged inside the chamber 24b and the pipe L1 arranged outside the stage 20, the chamber 24a to the pipe L1 are connected. The drawing piping portion 24c to be used is required. It is also conceivable that the lead-out piping part 24 c is formed, for example, through the glass plate 22 shown in FIG. 23 and toward the lower surface 22 b of the glass plate 22. However, in this case, the pipe L1 (see FIG. 16) connected after being drawn out to the lower surface 22b side of the glass plate 22 may overlap the irradiation path of the laser light 16a. Therefore, in the present embodiment, as shown in FIG. 16, a lead-out piping portion 24 c that extends from the chamber 24 a through the chamber 24 b and the frame body 26 toward the side surface of the stage 20 is formed. Thus, when forming the extraction | drawer piping part 24c toward the side surface of the stage 20, depending on required suction | attraction force, the width | variety of the extraction | drawer piping part 24c may become thicker than the width | variety of the dicing area | region 10c as shown in FIG. is there. However, even in this case, the dicing region 10c is arranged so as to overlap the extraction piping portion 24c, thereby suppressing the laser light 16a (see FIG. 23) from passing through the extraction piping portion 24c in the laser irradiation process. can do. Further, from the viewpoint of reducing the risk that the laser beam 16a (see FIG. 23) passes through the extraction piping portion 24c, it is preferable to reduce the number of extraction piping portions 24c. In the present embodiment, one extraction piping portion is used. 24c is connected to the chamber 24a. On the other hand, the number of the drawing piping portions 24d connecting the chamber 24b to the piping L2 shown in FIG. 16 is not limited as the number of the drawing piping portions 24c, and can be determined according to the required suction force. For example, FIG. 16 shows a structure in which one extraction pipe portion 24d is connected to the chamber 24b. However, as a modification, a plurality of extraction pipe portions 24d can be formed.

  In the present embodiment, a so-called green laser having a wavelength in the green wavelength range (495 nm to 570 nm) is used as the laser light 16a shown in FIG. More specifically, for example, the wavelength (for example, 1064 nm) of a YAG laser using yttrium, aluminum, and garnet crystals is converted into a half wavelength by passing through a wavelength conversion element (not shown). The green laser has a wavelength of 532 nm. By setting the wavelength of the laser light 16a to a green wavelength region, the wafer 10 that is an object to be irradiated (specifically, for example, silicon, for example) compared to the case where an infrared laser (for example, a YAG laser before wavelength conversion) is used. This increases the laser light absorption efficiency of the semiconductor substrate. On the other hand, the laser light absorption efficiency of the glass plates 21 and 22 made of a glass material does not rise higher than the laser light absorption efficiency of the semiconductor substrate. For this reason, the processing energy of the laser beam 16a required for forming the mark 5 shown in FIG. 24 can be kept low. In the present embodiment, the conditions of the laser light source 16 shown in FIG. 23 are, for example, an output of 2.5 W, a frequency of 30 kHz, and a pulse width of 18 μs. Further, in order to make the shape of the mark 5 a predetermined shape as shown in FIG. 3, it is necessary to scan (scan) the laser beam 16 a on the trajectory along the shape of the mark 5 on the back surface 1 b of the wafer 10. The scan speed is 400 mm / s, for example. Thus, by irradiating a so-called green laser as the laser beam 16a, the processing energy of the laser beam 16a necessary for forming the mark 5 (see FIG. 24) can be suppressed, so the laser beam 16a. The width of the variation can be reduced.

  Through the processes described above, marks 5 having a predetermined shape as shown in FIG. 3, for example, are formed in the plurality of mark regions 5a shown in FIG. The wafer 10 on which the mark 5 is formed is transferred from the stage 20 to the wafer rack placement unit 31 by the handler 35 shown in FIG. 14 (unloading step shown in FIG. 5). And it is accommodated in the wafer rack 32 arrange | positioned at the wafer rack arrangement | positioning part 31, and is conveyed to the following process (this Embodiment ball mounting process).

5. Ball Mounting Step Next, in the ball mounting step, as shown in FIG. 25, the solder balls 4 are mounted on the land portions 3c. FIG. 25 is an enlarged cross-sectional view showing a state in which solder balls are mounted on land portions formed on the front surface side of a wafer having marks formed on the back surface.

  In this step, first, on the surface 1a of the wafer 10, the solder balls 4 formed in a substantially spherical shape are arranged on each of the plurality of land portions 3c exposed from the insulating film 3f. The diameter of the solder ball 4 is not particularly limited, but in the present embodiment, it is about 100 μm, for example. In addition, in order to join the solder ball 4 and the land part 3c reliably, the solder ball 4 is arrange | positioned on the land part 3c through the activator called a flux, for example. The flux is an activator that can improve the wettability of the solder ball 4 because it can be removed, for example, by coming into contact with an oxide film formed on the surface of the solder ball 4. Subsequently, heat treatment (reflow) is performed on the wafer 10 on which the solder balls 4 are arranged, and the plurality of solder balls 4 are melted and joined to the plurality of land portions 3c, respectively. In the reflow process, the wafer 10 is placed in a reflow furnace and heated to a temperature higher than the melting point of the solder balls 4, for example, 260 ° C. or higher. When the solder balls 4 and the land portions 3c are joined using a flux as in the present embodiment, cleaning is performed to remove the residue of the flux component after the heat treatment.

  In addition, this process can be performed before the above-mentioned mark formation process. When the ball mounting process is performed before the mark forming process, the surface 1a of the wafer 10 on which the plurality of solder balls 4 (see FIG. 25) are mounted by the handler 35 shown in FIG. Adsorption will be held. However, even when the solder balls 4 are mounted as shown in FIG. 25, the height of the solder balls 4 protruding from the surface 1a of the wafer 10 is about several tens μm to several hundreds μm (in this embodiment, For example, about 100 μm). For this reason, even if the solder ball 4 is formed, the surface 1a side can be adsorbed and held. Further, since the warp deformation generated in the wafer 10 is corrected by the suction force acting from the back surface 1b side of the wafer 10, even if a plurality of solder balls 4 are mounted on the front surface 1a side of the wafer 10, these are damaged. You can correct without having to.

  Moreover, this process can also be performed before an above described back surface grinding process. However, in the back grinding process, it is preferable to carry out after the back grinding process from the viewpoint of preventing the solder ball 4 from being damaged or the joint portion of the solder ball 4 from being peeled off.

6). Individualization Step Next, in the individualization step, the wafer 10 is divided along the dicing region 10c shown in FIG. 26, and is divided into individual chip regions 10a to obtain a plurality of WPP1. FIG. 26 is an enlarged cross-sectional view showing a state where the wafer shown in FIG. 25 is cut along the dicing area. In the present embodiment, for example, in this embodiment, a cutting jig (rotating blade) 18 such as a dicing blade is run along the dicing area 10c to cut the wafer 10 and separate it into a plurality of WPPs 1. At this time, in order to prevent the separated WPP 1 from being scattered around, cutting is performed with an adhesive tape 19 such as a dicing tape attached to the back surface 1 b of the wafer 10.

  The WPP 1 shown in FIGS. 1 to 3 is completed. Thereafter, necessary inspections such as an appearance inspection and an electrical test of the WPP 1 are performed (inspection process). Then, it is conveyed to the packaging process for shipping WPP1.

(Embodiment 2)
Next, another embodiment for manufacturing the WPP 1 described in the first embodiment will be described. In the present embodiment, the description will focus on the differences from the semiconductor device manufacturing method described in the first embodiment, and the description of the common parts will be omitted. The drawings necessary for explaining the differences from the first embodiment are also shown, and the drawings described in the first embodiment will be cited as necessary. The manufacturing method of the semiconductor device according to the second embodiment is the same as the manufacturing method of the semiconductor device described in the first embodiment, except that, in the mark forming step, the surface side of the wafer is arranged opposite to the upper surface of the stage. It is the same. FIG. 27 is an explanatory view schematically showing an outline of a process of forming a mark on the back surface of the semiconductor wafer according to the present embodiment which is a modification of FIG. FIG. 28 is a modification of FIG. 15 and is a cross-sectional view showing a state in which a plurality of wafers are mounted on a wafer rack arranged in the wafer rack arrangement section shown in FIG. FIGS. 29, 30, and 31 are cross-sectional views showing modified examples of FIGS. 18, 19, and 20, respectively. FIG. 32 is a plan view showing a modification of FIG. 33 and 34 are cross-sectional views showing modifications of FIGS. 22 and 23, respectively.

  As shown in FIG. 27, in the present embodiment, the mark forming step is performed in a state where the surface 1 a of the wafer 10 is disposed so as to face the upper surface 20 a of the stage 20. For this reason, the alignment mark recognition process described in the above embodiment is performed by the imaging device 15 disposed below the stage 20. The laser irradiation process described in the first embodiment is performed by the laser light source 16 disposed above the stage 20. Hereinafter, differences from the above-described embodiment will be described in detail with reference to FIGS. 28 to 34.

  First, as shown in FIG. 28, in the mark forming process of the present embodiment, each of the plurality of wafers 10 faces the surface 1a downward in the wafer rack 32 of the wafer rack placement unit 31 shown in FIG. It is laminated in a state. That is, the first and second embodiments are stacked in an inverted state. In this embodiment, at least in each process until the laser irradiation process is completed, the wafer 1 is transferred with the surface 1a facing downward. For this reason, in the pre-alignment process described in the second embodiment, the wafer 10 is transferred to the pre-aligner 33 shown in FIG. 14 with the front surface 1a facing downward, and is placed on the stage (pre-aligned stage) 33a. The The position of the direction identification unit 10d (see FIG. 6) of the wafer 10 is detected by the position detection unit 33b arranged on the stage 33a of the pre-aligner 33.

  In the wafer placement process of the present embodiment, as shown in FIG. 29, the holding portion 35a of the handler 35 holds the back surface 1b side of the wafer 10, and the upper surface 20a of the stage 20 and the front surface 1a of the wafer 10 are The wafer 10 is placed on the stage 20 so as to face each other. Here, the deformation direction of the warp deformation generated in the wafer 10 is the same as that in the first embodiment. That is, as shown in FIG. 13, when the surface 1a of the wafer 10 is arranged upward, each cross section along one center line (virtual line) 13 passing through the center of the surface 1a is the end side. The wafer 10 is warped and deformed so as to form a concave shape arranged at a lower position on the center side. Therefore, when the wafer 10 is placed on the stage 20, as shown in FIG. 29, the peripheral edge side of the wafer 10 abuts the upper surface 20a of the stage 20, and inside the abutted area, the surface 1a of the wafer 10 and the stage A gap is generated between the upper surfaces 20a of the twenty. At this time, the alignment mark 12 (see FIG. 11) on the surface 1a of the wafer 10 is arranged so as not to overlap the plurality of suction holes 25 and the partition member 23 in plan view. Specifically, as shown in FIG. 32, when the wafer 10 is fixed to the stage 20, the plurality of alignment marks 12 on the surface 1 a of the wafer 10 do not overlap the plurality of suction holes 25 and the partition member 23 in plan view. To place. Thus, in the alignment mark recognition process of the present embodiment shown in FIG. 33, the illumination light 17a emitted from the illumination device 17 toward the surface 1a of the wafer 10 or the reflected light 17b from the wafer 10 is sucked into the suction holes. 25 and the partition member 23 can be prevented or suppressed from lowering the detection accuracy of the alignment mark.

  As in the first embodiment, since the pre-alignment process is also performed in the second embodiment, when the wafer 10 is transferred onto the stage 20 and placed on the stage 20, the mark forming apparatus 30 (see FIG. 14). In the control unit 30a (see FIG. 14), the position data of the plurality of alignment marks 12 (see FIG. 32) on the wafer 10 can be calculated from the position data of the direction identification unit 10d. Then, based on the calculated position data of the mark area 5a, the wafer 10 is moved via the handler 35, whereby a plurality of alignment marks 12 formed at predetermined positions on the surface 1a of the wafer 10 (see FIG. 32). ) Can be arranged so as not to overlap the plurality of suction holes 25 and the partition member 23.

  Incidentally, in the second embodiment, the wafer 10 is arranged so that the surface 1a of the wafer 10 faces the upper surface 20a of the stage 20, and therefore the wafer fixing process is different from the first embodiment in the following points. That is, in the present embodiment, as shown in FIG. 29, the surface 1a side of the wafer 10 placed on the stage 20 is sucked to fix the wafer 10 and correct the warp deformation. Here, before the suction from the suction hole 25, the distance from the suction hole 25b arranged on the peripheral edge side to the surface 1a of the wafer 10 is the suction hole 25a arranged inside the suction hole 25a. Is shorter than the distance from the surface 1 a of the wafer 10. For this reason, when the decompression of the chambers 24a, 24b is started, first, the plurality of suction holes 25b adsorb the surface 1a of the wafer 10 as shown in FIG. When the surface 1a of the wafer 10 is adsorbed by the plurality of suction holes 25b, the warp deformation of the wafer 10 is corrected following the upper surface 20a of the stage 20 by the suction force of the suction holes 25b. By this correction, the distance between the surface 1a and the suction hole 25a becomes closer to the inner side (center portion) of the peripheral portion of the wafer 10. When the inside of the chamber 24a is depressurized while the distance between the surface 1a and the suction hole 25a is close, the surface 1a of the wafer 10 is adsorbed and fixed to the plurality of suction holes 25a as shown in FIG. At this time, the warp deformation is corrected in the central portion of the wafer 10 along the upper surface 20a of the stage 20 by the suction force of the suction holes 25a. In other words, the warping deformation of the wafer 10 can be corrected and the surface 1a can be flattened by this step. Thereby, the entire surface 1a of the wafer 10 can be firmly adsorbed and fixed.

  Incidentally, in the second embodiment, since the peripheral edge side of the wafer 10 contacts the upper surface 20a of the stage 20, the wafer 10 is more stable than the first embodiment. For this reason, as in the first embodiment, the suction sequence for sucking the surface 1a of the wafer 10 can be surely performed with the plurality of suction holes 25b and the plurality of suction holes without shifting the timing of decompressing the chambers 24a and 24b. The order can be 25a. Therefore, for example, the decompression of the chambers 24a and 24b can be started before the wafer placement process, simultaneously with the wafer placement process, or after the wafer placement process. However, until the warp deformation of the wafer 10 is corrected to some extent as shown in FIG. 30, the suction hole 25a does not adsorb the wafer 10 even if the chamber 24a is depressurized. From the viewpoint of reducing the energy required for depressurization. It is preferable to start depressurization in the order of the chamber 24b and the chamber 24a.

  Further, in the first embodiment, since the warp deformation of the wafer 10 is corrected from the center side to the peripheral side of the back surface 1b of the wafer 10, if the suction hole 25a is adsorbed first, it occurs during correction. The amount of distortion of the wafer 10 can be reduced. However, in the second embodiment, since the peripheral edge side of the wafer 10 is first sucked and fixed by the suction holes 25b, the distortion amount of the wafer 10 generated during correction becomes larger than that in the first embodiment. Therefore, from the viewpoint of reducing the amount of distortion during correction, in the second embodiment, it is preferable to release the reduced pressure state in the chamber 24b after the surface 1a of the wafer 10 is adsorbed by the plurality of suction holes 25a. In other words, after the surface 1a of the wafer 10 is adsorbed by the plurality of suction holes 25a, the inside of the chamber 24b is preferably pressurized (returned to the same level as the atmospheric pressure outside the chamber 24b). Thereby, since the peripheral part of the wafer 10 is released from the fixed state, the amount of distortion generated during correction can be reduced. Thereafter, if the pressure in the chamber 24b is reduced again, an increase in the amount of distortion can be suppressed, and the wafer 10 can be adsorbed and fixed by the plurality of suction holes 25b.

Next, as shown in FIG. 33, the alignment mark 12 (see FIG. 32) formed on the surface 1a of the wafer 10 is recognized with the wafer 10 fixed (alignment mark recognition step). In the second embodiment, for example, as shown in FIG. 32, the illumination light 17a is irradiated from the illumination device 17 arranged below the stage 20 toward the surface 1a of the wafer 10, and the reflected light 17b from the wafer 10 is irradiated. Is imaged by the imaging device 15, and the position and orientation of the alignment mark 12 (see FIG. 32) are detected with higher accuracy than in the pre-alignment step. For this reason, the illumination light 17 a and the reflected light 17 b pass through at least the glass plates 21 and 22 constituting the stage 20. Therefore, at least the glass plates 21 and 22 among the constituent members of the stage 20 are made of a material that is transparent to the illumination light 17a and the reflected light 17b. Here, the material transparent to the illumination light 17a and the reflected light 17b is compared with an irradiated portion of the wafer 10 that is an irradiation target (specifically, an alignment mark formed on the surface 1a of the wafer 10). A material that has a sufficiently low absorption rate of the illumination light 17a and the reflected light 17b. Further, it is preferable to use a material having a refractive index lower than that of the alignment mark 12 with respect to the illumination light 17a and the reflected light 17b. In the second embodiment, similarly to the first embodiment, a glass material containing silicon oxide (SiO ₂ ) as a main material is used. As described above, the glass plates 21 and 22 are made of a material whose absorption efficiency and refractive index with respect to the illumination light 17a and the reflected light 17b are lower than that of the irradiated portion of the wafer 10, so that the illumination light 17a and the reflected light 17b It is possible to suppress a decrease in detection accuracy of the alignment mark 12 (see FIG. 32) due to absorption or refraction when part of the glass plates 21 and 22 passes.

  Next, as shown in FIG. 34, a laser beam 16a is irradiated toward the back surface 1b of the wafer 10 to form mark areas formed in each of the plurality of chip regions 10a on the back surface 1b of the wafer 10 shown in FIG. A mark 5 (see FIG. 4) is formed in 5a (laser irradiation step). In this step, for example, as shown in FIG. 34, laser light 16a is irradiated from a laser light source 16 disposed above the stage 20. For this reason, in the present embodiment, the laser beam 16 a is irradiated to the back surface 1 b of the wafer 10 without passing through the stage 20.

  The manufacturing method of the semiconductor device of the second embodiment is the same as the semiconductor device described in the first embodiment and the manufacturing method thereof, except for the differences described above. Therefore, although the overlapping description is omitted, the invention described in the first embodiment can be applied except for the above differences. However, in the first embodiment, as a modification, it has been described that the ball mounting process can be performed before the mark forming process. However, in the second embodiment, since the surface 1a of the wafer 10 is fixed to face the upper surface of the stage 20, from the viewpoint of preventing the solder ball 4 (see FIG. 25) from being damaged or peeled off, It is preferably performed after the mark forming step. Further, since the laser irradiation process is finished with the front surface 1a of the wafer 10 facing downward, a process of inverting the front surface 1a and the back surface 1b of the wafer 10 after the laser irradiation process and before the ball mounting process is performed. Preferably it is done.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  For example, in the first embodiment and the second embodiment, the example in which the suction hole 25 having a cylindrical shape is formed as the opening for sucking the front surface 1a or the back surface 1b of the wafer 10 has been described. However, as described in the first embodiment, the suction force can be improved by reducing the opening area of the opening. Accordingly, the plurality of suction holes 25 shown in FIG. 16 can be replaced with, for example, a plurality of slits 28 in which the planar shape of the opening surface is an arc shape or a rectangle as shown in FIG. FIG. 35 is a plan view showing a modification of the plurality of suction holes shown in FIG. However, from the viewpoint of preventing the mark region 5a (see FIG. 10) or the alignment mark 12 (see FIG. 11) of the wafer 10 from overlapping the suction opening in a plan view, the opening area is the same. The plane shape of the opening surface is preferably circular. This is because if the opening shape of the suction opening is elongated, the mark region 5a or the alignment mark 12 is easily overlapped. In addition, from the viewpoint of workability when forming the opening for suction in the glass plate 21 (processing accuracy and prevention of damage to the glass plate 21 during processing), it is possible to form a plurality of suction holes 25 having a cylindrical shape. Particularly preferred.

  Further, for example, in the first embodiment and the second embodiment, the embodiment applied to the WPP type semiconductor device in which the rewiring layer is formed on the semiconductor substrate has been described. However, the embodiment is applied to other semiconductor devices. You can also. For example, the present invention can be applied to a semiconductor device in which the mark 5 as shown in FIG. 3 is formed on the back surface 2b of the semiconductor chip 2 where the rewiring layer 3 shown in FIG. 2 is not formed. In this case, the land portion 3c described in the first embodiment and the second embodiment can be applied in place of the pad (electrode terminal) 2c shown in FIG.

  The present invention is applicable to a semiconductor device that forms a mark on a back surface of a semiconductor wafer by irradiating a laser.

1 WPP (semiconductor device)
1a Front surface 1b Back surface 2 Semiconductor chip 2a Front surface 2b Back surface 2c Pad 2d Semiconductor substrate 2e Main surface 2f Wiring layer 2g Surface wiring 2k Insulating layer 3 Rewiring layer 3a Upper surface 3b Lower surface 3c Land portion 3d Wiring 3e, 3f Insulating film 3g Bonding portion 3h Extension part 4 Solder ball 5 Mark 5a Mark area 5b Non-mark area 6 Irradiation light 7 Viewpoints 8a and 8b Reflected light 10 Wafer (semiconductor wafer)
10a Chip area 10b Back surface 10c Dicing area 10d Direction identification part 11 Grinding member 12 Alignment mark (alignment pattern)
13 Centerline 14 Protective Tape 15 Imaging Device 16 Laser Light Source 16a Laser Light 17 Illumination Device 17a Illumination Light 17b Reflected Light 18 Cutting Jig (Rotating Blade)
19 Adhesive tape (dicing tape)
20 stages (laser marking stage)
20a Upper surface 21 Glass plate (upper plate)
21b Lower surface 22 Glass plate (lower plate)
22a Upper surface 22b Lower surface 23 Partition member 24, 24a, 24b Chamber (space, hollow space)
24c, 24d Drawer piping parts 25, 25a, 25b Suction holes (openings)
26 Frame 27, 27a, 27b Suction path 28 Slit 30 Mark forming device 30a Control unit 31 Wafer rack placement unit (loader unit, unloader unit)
32 Wafer rack (wafer cassette)
33 Pre-aligner 33a Stage (Pre-aligned stage)
33b Position detection unit 34 Mark formation unit 35 Handler (conveying jig)
35a holding part 36 table (XY table)
L1, L2 Piping P1, P2 Pump (vacuum pump)
V1, V2 valve

Claims (20)

A method for manufacturing a semiconductor device comprising the following steps:
(A) a first member having a first upper surface and a first lower surface opposite to the first upper surface;
A second member having a second upper surface facing the first lower surface, and a second lower surface opposite to the second upper surface;
A first space located between the first member and the second member;
A second space located between the first member and the second member and disposed around the first space;
A partition member provided between the first space and the second space;
A plurality of first surfaces formed from one surface of the first upper surface and the first lower surface of the region overlapping the first space in plan view to the other surface and connected to the first space. An opening,
A plurality of second surfaces formed from one surface of the first upper surface and the first lower surface of the region overlapping the second space in plan view to the other surface and connected to the second space. Providing a stage with an opening;
(B) preparing a semiconductor wafer on which a plurality of chip regions having a front surface, a plurality of electrode terminals formed on the front surface, and a back surface opposite to the front surface are formed;
(C) After the steps (a) and (b), the semiconductor wafer is disposed on the first upper surface of the stage so that the back surface of the semiconductor wafer faces the first upper surface of the stage. The step of:
(D) sucking the semiconductor wafer through the plurality of first and second openings and fixing the semiconductor wafer to the first upper surface of the stage;
(E) a step of recognizing an alignment mark formed on the surface side of the semiconductor wafer after the step (d);
(F) After the step (e), the first region provided on the back surface of each of the plurality of chip regions of the semiconductor wafer is irradiated with a laser through the first and second members, Forming a mark;
here,
In the step (c), when the semiconductor wafer is fixed to the stage in the step (d), the first region of the semiconductor wafer has the plurality of first and second openings and the plurality of openings in the plan view. The semiconductor wafer is placed on the stage so as not to overlap the partition member. In claim 1,
The method of manufacturing a semiconductor device, wherein the first space is connected to a first suction path, and the second space is connected to a second suction path different from the first suction path. In claim 2,
The semiconductor wafer has a dicing area between the plurality of chip areas,
In the step (c), when the semiconductor wafer is fixed to the stage in the step (d), the semiconductor wafer is placed on the first upper surface of the stage so that the dicing region is positioned on the partition member. A method for manufacturing a semiconductor device, comprising: disposing the semiconductor device. In claim 3,
In the step (c),
(C1) recognizing a direction identifying portion formed on the semiconductor wafer and aligning the semiconductor wafer with a transfer jig for transferring the semiconductor wafer;
(C2) After the step (c1), a step of transferring the semiconductor wafer to the first upper surface of the stage by the transfer jig;
A method for manufacturing a semiconductor device, comprising: In claim 4,
The method for manufacturing a semiconductor device, wherein the plurality of first openings and the plurality of second openings are arranged concentrically with a center of a semiconductor wafer mounting region of the stage as a reference. In claim 1,
In the step (b),
(B1) forming the plurality of electrode terminals on the surface of the semiconductor wafer;
(B2) a step of forming an insulating film covering the surface of the semiconductor wafer after the step (b1);
(B3) a step of polishing the back surface of the semiconductor wafer after the step (b2);
A method for manufacturing a semiconductor device, comprising: In claim 6,
A method of manufacturing a semiconductor device, wherein a linear expansion coefficient of the insulating film covering the surface of the semiconductor wafer is larger than a linear expansion coefficient of a semiconductor substrate having the back surface of the semiconductor wafer. In claim 1,
In the step (d),
(D1) sucking the semiconductor wafer through the plurality of first openings and adsorbing the back surface of the semiconductor wafer to the plurality of first openings;
(D2) After the step (d1), the step of sucking the semiconductor wafer through the plurality of second openings and adsorbing the back surface of the semiconductor wafer to the plurality of second openings,
A method for manufacturing a semiconductor device, comprising: In claim 1,
The plurality of first openings are arranged along a first circle with the center of the semiconductor wafer mounted on the stage as the center,
The plurality of second openings are arranged along a second circle having the center of the semiconductor wafer as a center and a radius larger than the first circle,
A method of manufacturing a semiconductor device, wherein the radius of the first circle is less than half of the radius of the second circle. In claim 1,
The method of manufacturing a semiconductor device, wherein the laser irradiated to the semiconductor wafer in the step (f) has a wavelength of 495 nm to 570 nm. A method for manufacturing a semiconductor device comprising the following steps:
(A) a first member having a first upper surface and a first lower surface opposite to the first upper surface;
A second member having a second upper surface facing the first lower surface, and a second lower surface opposite to the second upper surface;
A first space located between the first member and the second member;
A second space located between the first member and the second member and disposed around the first space;
A partition member provided between the first space and the second space;
A plurality of first surfaces formed from one surface of the first upper surface and the first lower surface of the region overlapping the first space in plan view to the other surface and connected to the first space. An opening,
A plurality of second surfaces formed from one surface of the first upper surface and the first lower surface of the region overlapping the second space in plan view to the other surface and connected to the second space. Providing a stage with an opening;
(B) preparing a semiconductor wafer on which a plurality of chip regions having a front surface, a plurality of electrode terminals formed on the front surface, and a back surface opposite to the front surface are formed;
(C) After the steps (a) and (b), the semiconductor wafer is disposed on the first upper surface of the stage so that the surface of the semiconductor wafer faces the first upper surface of the stage. The step of:
(D) sucking the semiconductor wafer through the plurality of first and second openings and fixing the semiconductor wafer to the first upper surface of the stage;
(E) After the step (d), the plurality of alignment marks formed on the surface side of the semiconductor wafer are irradiated with illumination light through the first and second members, and the plurality of alignment marks Recognizing
(F) After the step (e), a step of irradiating a first region provided on the back surface of each of the plurality of chip regions of the semiconductor wafer to form a mark;
here,
In the step (c), when the semiconductor wafer is fixed to the stage in the step (d), the plurality of alignment marks of the semiconductor wafer have the plurality of first and second openings and The semiconductor wafer is placed on the stage so as not to overlap the partition member. In claim 11,
The method of manufacturing a semiconductor device, wherein the first space is connected to a first suction path, and the second space is connected to a second suction path different from the first suction path. In claim 12,
The plurality of alignment marks are formed in the plurality of chip regions,
The semiconductor wafer has a dicing area between the plurality of chip areas,
In the step (c), when the semiconductor wafer is fixed to the stage in the step (d), the semiconductor wafer is placed on the first upper surface of the stage so that the dicing region is positioned on the partition member. A method of manufacturing a semiconductor device, comprising: arranging the semiconductor device. In claim 13,
In the step (c),
(C1) recognizing a direction identifying portion formed on the semiconductor wafer and aligning the semiconductor wafer with a transfer jig for transferring the semiconductor wafer;
(C2) After the step (c1), a step of transferring the semiconductor wafer to the first upper surface of the stage by the transfer jig;
A method for manufacturing a semiconductor device, comprising: In claim 14,
The method for manufacturing a semiconductor device, wherein the plurality of first openings and the plurality of second openings are arranged concentrically with a center of a semiconductor wafer mounting region of the stage as a reference. In claim 11,
In the step (b),
(B1) forming the plurality of electrode terminals on the surface of the semiconductor wafer;
(B2) a step of forming an insulating film covering the surface of the semiconductor wafer after the step (b1);
(B3) a step of polishing the back surface of the semiconductor wafer after the step (b2);
A method for manufacturing a semiconductor device, comprising: In claim 16,
A method of manufacturing a semiconductor device, wherein a linear expansion coefficient of the insulating film covering the surface of the semiconductor wafer is larger than a linear expansion coefficient of a semiconductor substrate having the back surface of the semiconductor wafer. In claim 11,
In the step (d),
(D1) sucking the semiconductor wafer through the plurality of second openings, and sucking the back surface of the semiconductor wafer to the second openings;
(D2) After the step (d1), the step of sucking the semiconductor wafer through the plurality of first openings and adsorbing the back surface of the semiconductor wafer to the plurality of first openings,
(D3) A step of pressurizing the second space after the step (d2),
(D4) After the step (d3), sucking the semiconductor wafer through the plurality of second openings, and again adsorbing the back surface of the semiconductor wafer to the plurality of second openings,
A method for manufacturing a semiconductor device, comprising: In claim 11,
The plurality of first openings are arranged along a first circle with the center of the semiconductor wafer mounted on the stage as the center,
The plurality of second openings are arranged along a second circle having the center of the semiconductor wafer as a center and a radius larger than the first circle,
A method of manufacturing a semiconductor device, wherein the radius of the first circle is less than half of the radius of the second circle. In claim 11,
The method of manufacturing a semiconductor device, wherein the laser irradiated to the semiconductor wafer in the step (f) has a wavelength of 495 nm to 570 nm.

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