JP2016503242A5 - - Google Patents

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Publication number
JP2016503242A5
JP2016503242A5 JP2015552852A JP2015552852A JP2016503242A5 JP 2016503242 A5 JP2016503242 A5 JP 2016503242A5 JP 2015552852 A JP2015552852 A JP 2015552852A JP 2015552852 A JP2015552852 A JP 2015552852A JP 2016503242 A5 JP2016503242 A5 JP 2016503242A5
Authority
JP
Japan
Prior art keywords
solder ball
mold
grooves
row
solder balls
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2015552852A
Other languages
English (en)
Japanese (ja)
Other versions
JP2016503242A (ja
JP6019252B2 (ja
Filing date
Publication date
Priority claimed from US13/777,298 external-priority patent/US9313881B2/en
Application filed filed Critical
Publication of JP2016503242A publication Critical patent/JP2016503242A/ja
Publication of JP2016503242A5 publication Critical patent/JP2016503242A5/ja
Application granted granted Critical
Publication of JP6019252B2 publication Critical patent/JP6019252B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2015552852A 2013-01-11 2014-01-13 成形レーザパッケージ（ｍｌｐ）パッケージ上のモールド貫通ビアの軽減溝 Expired - Fee Related JP6019252B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201361751313P 2013-01-11 2013-01-11
US61/751,313 2013-01-11
US13/777,298 2013-02-26
US13/777,298 US9313881B2 (en) 2013-01-11 2013-02-26 Through mold via relief gutter on molded laser package (MLP) packages
PCT/US2014/011230 WO2014110482A1 (en) 2013-01-11 2014-01-13 Through mold via relief gutter on molded laser package (mlp) packages

Publications (3)

Publication Number Publication Date
JP2016503242A JP2016503242A (ja) 2016-02-01
JP2016503242A5 true JP2016503242A5 (enExample) 2016-07-21
JP6019252B2 JP6019252B2 (ja) 2016-11-02

Family

ID=51164316

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2015552852A Expired - Fee Related JP6019252B2 (ja) 2013-01-11 2014-01-13 成形レーザパッケージ（ｍｌｐ）パッケージ上のモールド貫通ビアの軽減溝

Country Status (6)

Country Link
US (1) US9313881B2 (enExample)
EP (1) EP2943977A1 (enExample)
JP (1) JP6019252B2 (enExample)
KR (1) KR101674155B1 (enExample)
CN (1) CN104919587B (enExample)
WO (1) WO2014110482A1 (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20140139332A (ko) * 2013-05-27 2014-12-05 삼성전자주식회사 반도체 패키지 및 그 제조 방법
JP6544354B2 (ja) * 2014-06-27 2019-07-17 ソニー株式会社 半導体装置の製造方法
US10032652B2 (en) * 2014-12-05 2018-07-24 Advanced Semiconductor Engineering, Inc. Semiconductor package having improved package-on-package interconnection
US10090241B2 (en) * 2015-05-29 2018-10-02 Taiwan Semiconductor Manufacturing Co., Ltd. Device, package structure and method of forming the same
CN106872575B (zh) * 2017-01-05 2020-01-14 航天科工防御技术研究试验中心 一种塑封器件分层缺陷的分级风险评价方法
TW201837420A (zh) * 2017-04-14 2018-10-16 雙鴻科技股份有限公司 均溫板
US10629536B2 (en) 2018-04-05 2020-04-21 Micron Technology, Inc. Through-core via
CN111112835A (zh) * 2018-10-31 2020-05-08 东莞新科技术研究开发有限公司 一种激光分束装置和激光焊接方法
KR102688571B1 (ko) 2019-06-20 2024-07-25 삼성전자주식회사 반도체 패키지
US12027467B2 (en) * 2021-01-29 2024-07-02 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same

Family Cites Families (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4706167A (en) * 1983-11-10 1987-11-10 Telemark Co., Inc. Circuit wiring disposed on solder mask coating
US4996391A (en) * 1988-09-30 1991-02-26 Siemens Aktiengesellschaft Printed circuit board having an injection molded substrate
US5386627A (en) * 1992-09-29 1995-02-07 International Business Machines Corporation Method of fabricating a multi-layer integrated circuit chip interposer
US5784782A (en) 1996-09-06 1998-07-28 International Business Machines Corporation Method for fabricating printed circuit boards with cavities
US6329605B1 (en) * 1998-03-26 2001-12-11 Tessera, Inc. Components with conductive solder mask layers
JP3446825B2 (ja) * 1999-04-06 2003-09-16 沖電気工業株式会社 半導体装置およびその製造方法
JP2001053111A (ja) * 1999-08-10 2001-02-23 Matsushita Electric Works Ltd フリップチップ実装構造
US20020093089A1 (en) 1999-12-01 2002-07-18 Dau-Tsyong Lu Compliant mounting interface for electronic devices
US6562656B1 (en) * 2001-06-25 2003-05-13 Thin Film Module, Inc. Cavity down flip chip BGA
US6854633B1 (en) * 2002-02-05 2005-02-15 Micron Technology, Inc. System with polymer masking flux for fabricating external contacts on semiconductor components
JP3819806B2 (ja) * 2002-05-17 2006-09-13 富士通株式会社 バンプ電極付き電子部品およびその製造方法
US6787443B1 (en) * 2003-05-20 2004-09-07 Intel Corporation PCB design and method for providing vented blind vias
TWI230994B (en) * 2004-02-25 2005-04-11 Via Tech Inc Circuit carrier
WO2008062647A1 (fr) 2006-11-02 2008-05-29 Nec Corporation Système à plusieurs processeurs, procédé de configuration de système dans un système à plusieurs processeurs, et programme associé
US20090071707A1 (en) * 2007-08-15 2009-03-19 Tessera, Inc. Multilayer substrate with interconnection vias and method of manufacturing the same
JP2009302505A (ja) * 2008-05-15 2009-12-24 Panasonic Corp 半導体装置、および半導体装置の製造方法
KR20110070987A (ko) * 2008-10-21 2011-06-27 아토테크더치랜드게엠베하 기판 상에 땜납 용착물을 형성하는 방법
WO2010100706A1 (ja) 2009-03-05 2010-09-10 パナソニック株式会社 半導体装置
JP5379527B2 (ja) * 2009-03-19 2013-12-25 パナソニック株式会社 半導体装置
US8222538B1 (en) * 2009-06-12 2012-07-17 Amkor Technology, Inc. Stackable via package and method
JP5481724B2 (ja) * 2009-12-24 2014-04-23 新光電気工業株式会社 半導体素子内蔵基板
KR101680082B1 (ko) * 2010-05-07 2016-11-29 삼성전자 주식회사 웨이퍼 레벨 패키지 및 웨이퍼 레벨 패키지의 형성방법
CN102237330B (zh) * 2010-05-07 2015-08-05 三星电子株式会社 晶片级封装
US8492896B2 (en) * 2010-05-21 2013-07-23 Panasonic Corporation Semiconductor apparatus and semiconductor apparatus unit
KR101719630B1 (ko) 2010-12-21 2017-04-04 삼성전자 주식회사 반도체 패키지 및 그를 포함하는 패키지 온 패키지

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