JP2016051875A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2016051875A JP2016051875A JP2014178040A JP2014178040A JP2016051875A JP 2016051875 A JP2016051875 A JP 2016051875A JP 2014178040 A JP2014178040 A JP 2014178040A JP 2014178040 A JP2014178040 A JP 2014178040A JP 2016051875 A JP2016051875 A JP 2016051875A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 181
- 239000000758 substrate Substances 0.000 claims abstract description 62
- 230000002093 peripheral effect Effects 0.000 claims description 28
- 230000015572 biosynthetic process Effects 0.000 claims description 8
- 230000000052 comparative effect Effects 0.000 description 30
- 238000000034 method Methods 0.000 description 26
- 238000010586 diagram Methods 0.000 description 21
- 238000004088 simulation Methods 0.000 description 16
- 230000007423 decrease Effects 0.000 description 12
- 230000000694 effects Effects 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000006185 dispersion Substances 0.000 description 2
- 230000000295 complement effect Effects 0.000 description 1
- 230000006835 compression Effects 0.000 description 1
- 238000007906 compression Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
- G11C5/146—Substrate bias generators
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5286—Arrangements of power or ground buses
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
- H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
- H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Engineering & Computer Science (AREA)
- Geometry (AREA)
- Semiconductor Integrated Circuits (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Ceramic Engineering (AREA)
Abstract
Description
図1は、開示の技術の実施形態に係る半導体装置10のフロアプランの一例を示す図である。半導体装置10は、一例として、半導体基板上に集積回路が形成された矩形形状の半導体チップとして構成されている。半導体装置10は、その外縁を画定する4つの辺に沿って設けられた入出力回路(I/O回路)11を有する。また、半導体装置10は、入出力回路(I/O回路)11の内側に、一例として、チャージポンプ12、ロジックセル13、SRAM(Static Random Access Memory)14およびアナログマクロ15などの複数の回路を有する。
以下の説明では、正極性と負極性のバックバイアス電圧VAの両方を含めて説明するため、特に正極性・負極性の区別が無い限り、バックバイアス電圧VAの電圧値に関して記述した部分はバックバイアス電圧VAの絶対値について記述しているものとする。すなわち負極性のバックバイアス電圧VAの場合、バックバイアス電圧VAに電圧ドロップが生ずるとは負極性のバックバイアス電圧VAが浅くなることを意味する。
図17Aは、電源電圧VBの分布に偏りが生じた状態を示す図である。図17Aには、電源配線20の中心点から左上方向にずれた位置に電源電圧VBが相対的に小さい領域が存在している場合が例示されている。このような電源電圧VBの分布の偏りは、電源電圧VBが供給される各回路による消費電力が、半導体基板上において不均一である場合に起こり得る。すなわち、消費電力が相対的に大きい領域では、電源電圧VBのドロップが大きくなり、当該領域における電源電圧VBは相対的に小さくなり、電源電圧VBの分布に偏りが生じる。
半導体基板に設けられ、前記半導体基板に供給される基板電圧によって閾値電圧が制御される半導体素子を各々が含む複数の回路と、
外周部の複数箇所に供給される電源電圧を、前記複数の回路の各々に供給するメッシュ状の第1の配線と、
配線層に設けられ、前記基板電圧の供給を受けるメッシュ状の第2の配線と、
前記第2の配線が設けられた配線層とは異なる配線層に設けられ、外周部が前記第2の配線の外周部に接続され、前記基板電圧を前記半導体基板に供給するメッシュ状の第3の配線と、
を含む半導体装置。
前記基板電圧は、前記第2の配線の中央部に供給されている
付記1に記載の半導体装置。
前記第2の配線および前記第3の配線は、前記回路による消費電力が前記半導体装置内で相対的に大きい第1の領域に対応する部分における前記基板電圧の絶対値のドロップが、前記回路による消費電力が前記第1の領域より小さい第2の領域に対応する部分における前記基板電圧の絶対値のドロップよりも大きくなるように構成されている
付記1または付記2に記載の半導体装置。
前記第2の配線および前記第3の配線は、それぞれの外周部において複数のビアを介して互いに接続され、
前記第1の領域に対応する部分における前記ビアの形成密度が、前記第2の領域に対応する部分における前記ビアの形成密度よりも小さい
付記3に記載の半導体装置。
前記第3の配線は、前記第1の領域に対応する部分における配線幅が、前記第2の領域に対応する部分における配線幅よりも小さい
付記3または付記4に記載の半導体装置。
前記基板電圧を生成する電圧生成部を更に含む、
付記1から付記5のいずれか1つに記載の半導体装置。
前記第2の配線および前記第3の配線は、それぞれの外周部において複数のビアを介して互いに接続されている
付記1または付記2に記載の半導体装置。
前記複数のビアは、等間隔に配置されている
付記7に記載の半導体装置。
11 入出力回路(I/O回路)
12 チャージポンプ
20 電源配線
30 バックバイアス配線
31 上層メッシュ配線
32 下層メッシュ配線
39 ビア
100 CMOS回路
110 P−MOSトランジスタ
120 N−MOSトランジスタ
111 N−ウェル領域
121 P−ウェル領域
130 半導体基板
Claims (6)
- 半導体基板に設けられ、前記半導体基板に供給される基板電圧によって閾値電圧が制御される半導体素子を各々が含む複数の回路と、
外周部の複数箇所に供給される電源電圧を、前記複数の回路の各々に供給するメッシュ状の第1の配線と、
配線層に設けられ、前記基板電圧の供給を受けるメッシュ状の第2の配線と、
前記第2の配線が設けられた配線層とは異なる配線層に設けられ、外周部が前記第2の配線の外周部に接続され、前記基板電圧を前記半導体基板に供給するメッシュ状の第3の配線と、
を含む半導体装置。 - 前記基板電圧は、前記第2の配線の中央部に供給されている
請求項1に記載の半導体装置。 - 前記第2の配線および前記第3の配線は、前記回路による消費電力が前記半導体装置内で相対的に大きい第1の領域に対応する部分における前記基板電圧の絶対値のドロップが、前記回路による消費電力が前記第1の領域より小さい第2の領域に対応する部分における前記基板電圧の絶対値のドロップよりも大きくなるように構成されている
請求項1または請求項2に記載の半導体装置。 - 前記第2の配線および前記第3の配線は、それぞれの外周部において複数のビアを介して互いに接続され、
前記第1の領域に対応する部分における前記ビアの形成密度が、前記第2の領域に対応する部分における前記ビアの形成密度よりも小さい
請求項3に記載の半導体装置。 - 前記第3の配線は、前記第1の領域に対応する部分における配線幅が、前記第2の領域に対応する部分における配線幅よりも小さい
請求項3または請求項4に記載の半導体装置。 - 前記基板電圧を生成する電圧生成部を更に含む、
請求項1から請求項5のいずれか1項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2014178040A JP6384210B2 (ja) | 2014-09-02 | 2014-09-02 | 半導体装置 |
US14/821,187 US9871027B2 (en) | 2014-09-02 | 2015-08-07 | Semiconductor device having mesh-patterned wirings |
CN201510543909.6A CN105390493B (zh) | 2014-09-02 | 2015-08-28 | 半导体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
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JP2014178040A JP6384210B2 (ja) | 2014-09-02 | 2014-09-02 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2016051875A true JP2016051875A (ja) | 2016-04-11 |
JP6384210B2 JP6384210B2 (ja) | 2018-09-05 |
Family
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JP2014178040A Expired - Fee Related JP6384210B2 (ja) | 2014-09-02 | 2014-09-02 | 半導体装置 |
Country Status (3)
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US (1) | US9871027B2 (ja) |
JP (1) | JP6384210B2 (ja) |
CN (1) | CN105390493B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200141971A (ko) * | 2017-11-15 | 2020-12-21 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 2차원 비아 필러 구조물들 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6966686B2 (ja) * | 2016-10-21 | 2021-11-17 | 株式会社ソシオネクスト | 半導体装置 |
US10090227B1 (en) * | 2017-07-13 | 2018-10-02 | Globalfoundries Inc. | Back biasing in SOI FET technology |
US10664642B1 (en) | 2018-11-30 | 2020-05-26 | International Business Machines Corporation | Constructing via meshes for high performance routing on silicon chips |
Citations (4)
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JPH10284690A (ja) * | 1997-04-07 | 1998-10-23 | Toshiba Corp | 半導体集積回路装置及びその電源配線方法 |
JP2007088151A (ja) * | 2005-09-21 | 2007-04-05 | Sharp Corp | 半導体集積回路の電源配線方法 |
JP2007287908A (ja) * | 2006-04-17 | 2007-11-01 | Nec Electronics Corp | 半導体集積回路及び半導体集積回路の設計方法 |
JP2013258266A (ja) * | 2012-06-12 | 2013-12-26 | Fujitsu Semiconductor Ltd | 半導体装置 |
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JPS63153852A (ja) | 1986-12-17 | 1988-06-27 | Mitsubishi Electric Corp | 半導体記憶装置 |
US6127845A (en) * | 1998-05-11 | 2000-10-03 | Quicklogic Corporation | Field programmable gate array having internal logic transistors with two different gate insulator thicknesses |
US6734472B2 (en) * | 2002-04-25 | 2004-05-11 | Synplicity, Inc. | Power and ground shield mesh to remove both capacitive and inductive signal coupling effects of routing in integrated circuit device |
JP4401621B2 (ja) * | 2002-05-07 | 2010-01-20 | 株式会社日立製作所 | 半導体集積回路装置 |
US7943436B2 (en) * | 2002-07-29 | 2011-05-17 | Synopsys, Inc. | Integrated circuit devices and methods and apparatuses for designing integrated circuit devices |
US7739624B2 (en) * | 2002-07-29 | 2010-06-15 | Synopsys, Inc. | Methods and apparatuses to generate a shielding mesh for integrated circuit devices |
JP2004152975A (ja) * | 2002-10-30 | 2004-05-27 | Renesas Technology Corp | 半導体装置の製造方法および半導体装置 |
JPWO2004077556A1 (ja) * | 2003-02-26 | 2006-06-08 | 三洋電機株式会社 | 半導体集積回路装置及びその電源配線方法 |
JP4200926B2 (ja) * | 2004-03-10 | 2008-12-24 | ソニー株式会社 | 半導体集積回路 |
US7346869B2 (en) * | 2004-10-29 | 2008-03-18 | Synopsys, Inc. | Power network analyzer for an integrated circuit design |
JP2006351633A (ja) | 2005-06-13 | 2006-12-28 | Matsushita Electric Ind Co Ltd | 半導体集積回路装置、電子部品実装基板および半導体集積回路装置のレイアウト設計方法 |
JP4636077B2 (ja) * | 2007-11-07 | 2011-02-23 | ソニー株式会社 | 半導体集積回路 |
JP2009140999A (ja) * | 2007-12-04 | 2009-06-25 | Toshiba Corp | 半導体集積回路 |
US8443306B1 (en) * | 2012-04-03 | 2013-05-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Planar compatible FDSOI design architecture |
-
2014
- 2014-09-02 JP JP2014178040A patent/JP6384210B2/ja not_active Expired - Fee Related
-
2015
- 2015-08-07 US US14/821,187 patent/US9871027B2/en active Active
- 2015-08-28 CN CN201510543909.6A patent/CN105390493B/zh not_active Expired - Fee Related
Patent Citations (4)
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JPH10284690A (ja) * | 1997-04-07 | 1998-10-23 | Toshiba Corp | 半導体集積回路装置及びその電源配線方法 |
JP2007088151A (ja) * | 2005-09-21 | 2007-04-05 | Sharp Corp | 半導体集積回路の電源配線方法 |
JP2007287908A (ja) * | 2006-04-17 | 2007-11-01 | Nec Electronics Corp | 半導体集積回路及び半導体集積回路の設計方法 |
JP2013258266A (ja) * | 2012-06-12 | 2013-12-26 | Fujitsu Semiconductor Ltd | 半導体装置 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20200141971A (ko) * | 2017-11-15 | 2020-12-21 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 2차원 비아 필러 구조물들 |
KR102344709B1 (ko) | 2017-11-15 | 2021-12-31 | 타이완 세미콘덕터 매뉴팩쳐링 컴퍼니 리미티드 | 2차원 비아 필러 구조물들 |
Also Published As
Publication number | Publication date |
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US9871027B2 (en) | 2018-01-16 |
JP6384210B2 (ja) | 2018-09-05 |
US20160064369A1 (en) | 2016-03-03 |
CN105390493A (zh) | 2016-03-09 |
CN105390493B (zh) | 2018-04-27 |
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