JP2016015484A - 半導体装置、該半導体装置の作製方法および該半導体装置を含む電子機器 - Google Patents
半導体装置、該半導体装置の作製方法および該半導体装置を含む電子機器 Download PDFInfo
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- JP2016015484A JP2016015484A JP2015116331A JP2015116331A JP2016015484A JP 2016015484 A JP2016015484 A JP 2016015484A JP 2015116331 A JP2015116331 A JP 2015116331A JP 2015116331 A JP2015116331 A JP 2015116331A JP 2016015484 A JP2016015484 A JP 2016015484A
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Abstract
【解決手段】第1の酸化物半導体膜と、第1の酸化物半導体膜上の第2の酸化物半導体膜と、第2の酸化物半導体膜と接するソース電極と、第2の酸化物半導体膜と接する領域を有するドレイン電極と、第2の酸化物半導体膜上、ソース電極上およびドレイン電極上の金属酸化物膜と、金属酸化物膜上のゲート絶縁膜と、ゲート絶縁膜上のゲート電極と、を有し、金属酸化物膜は、M(Mは、Ti、Ga、Y、Zr、La、Ce、NdまたはHf)とZnを含み、金属酸化物膜は、ターゲットが有するMとZnの原子数比をM:Zn=x:yとしたとき、x/(x+y)は、0.67より大きく0.99以下である部分を有する。
【選択図】図1
Description
本実施の形態では、本発明の一態様である半導体装置、およびその作製方法について図面を参照して説明する。半導体装置の一例としてトランジスタを用いて説明する。
実施の形態1に示すトランジスタ150は、酸化物半導体膜が2層であったが、これに限られず、酸化物半導体膜が単層、3層以上であってもよい。図4に酸化物半導体膜が単層の場合、図5に酸化物半導体膜が3層の場合について図示する。
図6(A)乃至図6(C)に、半導体装置が有するトランジスタ150cの上面図および断面図を示す。図6(A)はトランジスタ150cの上面図であり、図6(B)は、図6(A)の一点鎖線A1−A2間の断面図であり、図6(C)は、図6(A)の一点鎖線B1−B2間の断面図である。また、図6(A)乃至図6(C)では、図の明瞭化のために一部の要素を拡大、縮小、または省略して図示している。図6(B)に示すように酸化物半導体膜101bの側面は、層113aおよび層113bと接する構造とすることができる。
また、上記構成において、図7(A)乃至図7(C)に示すようにオフセット領域を低抵抗化したセルフアライン構造とすることができる。
また、図10(A)乃至図10(C)に示すトランジスタ150dのように、ソース電極103aおよびドレイン電極103bを酸化物半導体膜101b上のみで接する構成にしてもよい。
本実施の形態では、上記実施の形態で説明した半導体装置に含まれているトランジスタにおいて、酸化物半導体膜に適用可能な一態様について説明する。
本実施の形態では、本発明の一態様のトランジスタを利用した回路の一例について図面を参照して説明する。
図12(A)に本発明の一態様の半導体装置の断面図を示す。図12(A)に示す半導体装置は、下部に第1の半導体材料を用いたトランジスタ2200を有し、上部に第2の半導体材料を用いたトランジスタ2100を有している。トランジスタ2100には先の実施の形態で説明したトランジスタを用いることができ、図12(A)ではトランジスタ2100として、トランジスタ150を適用した例を示している。なお、一点鎖線より左側がトランジスタのチャネル長方向の断面、右側がチャネル幅方向の断面である。
上記構成において、トランジスタ2100やトランジスタ2200の電極の接続構成を異ならせることにより、様々な回路を構成することができる。以下では、本発明の一態様の半導体装置を用いることにより実現できる回路構成の例を説明する。
図12(B)に示す回路図は、pチャネル型のトランジスタ2200とnチャネル型のトランジスタ2100を直列に接続し、且つそれぞれのゲートを接続した、いわゆるCMOS回路の構成を示している。
また、図12(C)に示す回路図は、トランジスタ2100とトランジスタ2200のそれぞれのソースとドレインを接続した構成を示している。このような構成とすることで、いわゆるアナログスイッチとして機能させることができる。
本発明の一態様であるトランジスタを使用し、電力が供給されない状況でも記憶内容の保持が可能で、かつ、書き込み回数にも制限が無い半導体装置(記憶装置)の一例を図13に示す。
本実施の形態では、先の実施の形態で説明したトランジスタ、または記憶装置を含むRFタグについて、図14を参照して説明する。
本実施の形態では、先の実施の形態で説明した記憶装置を含むCPUについて説明する。
本実施の形態では、本発明の一態様のトランジスタを利用した表示装置の構成例について説明する。
図17(A)は、本発明の一態様の表示装置の上面図であり、図17(B)は、本発明の一態様の表示装置の画素に液晶素子を適用する場合に用いることができる画素回路を説明するための回路図である。また、図17(C)は、本発明の一態様の表示装置の画素に有機EL素子を適用する場合に用いることができる画素回路を説明するための回路図である。
また、画素の回路構成の一例を図17(B)に示す。ここでは、一例としてVA型液晶表示装置の画素に適用することができる画素回路を示す。
画素の回路構成の他の一例を図17(C)に示す。ここでは、有機EL素子を用いた表示装置の画素構造を示す。
本実施の形態では、本発明の一態様の半導体装置を適用した表示モジュールについて、図18を用いて説明を行う。
本発明の一態様に係る半導体装置は、表示機器、パーソナルコンピュータ、記録媒体を備えた画像再生装置(代表的にはDVD:Digital Versatile Disc等の記録媒体を再生し、その画像を表示しうるディスプレイを有する装置)に用いることができる。その他に、本発明の一態様に係る半導体装置を用いることができる電子機器として、携帯電話、携帯型を含むゲーム機、携帯データ端末、電子書籍端末、ビデオカメラ、デジタルスチルカメラ等のカメラ、ゴーグル型ディスプレイ(ヘッドマウントディスプレイ)、ナビゲーションシステム、音響再生装置(カーオーディオ、デジタルオーディオプレイヤー等)、複写機、ファクシミリ、プリンタ、プリンタ複合機、現金自動預け入れ払い機(ATM)、自動販売機などが挙げられる。これら電子機器の具体例を図19に示す。
本実施の形態では、本発明の一態様に係るRFデバイスの使用例について図20を用いながら説明する。RFデバイスの用途は広範にわたるが、例えば、紙幣、硬貨、有価証券類、無記名債券類、証書類(運転免許証や住民票等、図20(A)参照)、記録媒体(DVDやビデオテープ等、図20(B)参照)、乗り物類(自転車等、図20(C)参照)、包装用容器類(包装紙やボトル等、図20(D)参照)、身の回り品(鞄や眼鏡等、図20(E)参照)、食品類、植物類、動物類、人体、衣類、生活用品類、薬品や薬剤を含む医療品、または電子機器(液晶表示装置、EL表示装置、テレビジョン装置、または携帯電話)等の物品、若しくは各物品に取り付ける荷札(図20(E)、図20(F)参照)等に設けて使用することができる。
101a 酸化物半導体膜
101b 酸化物半導体膜
101c 酸化物半導体膜
102 下地絶縁膜
103a ソース電極
103b ドレイン電極
104 ゲート絶縁膜
105 ゲート電極
107 絶縁膜
108 絶縁膜
109a 絶縁膜
109b 絶縁膜
110a 配線
110b 配線
111 金属酸化物膜
113a 層
113b 層
115a 配線
115b 配線
141 低抵抗領域
142 低抵抗領域
150 トランジスタ
150a トランジスタ
150b トランジスタ
150c トランジスタ
150d トランジスタ
700 基板
701 画素部
702 走査線駆動回路
703 走査線駆動回路
704 信号線駆動回路
710 容量配線
712 ゲート配線
713 ゲート配線
714 データ線
716 トランジスタ
717 トランジスタ
718 液晶素子
719 液晶素子
720 画素
721 スイッチング用トランジスタ
722 駆動用トランジスタ
723 容量素子
724 発光素子
725 信号線
726 走査線
727 電源線
728 共通電極
800 RFタグ
801 通信器
802 アンテナ
803 無線信号
804 アンテナ
805 整流回路
806 定電圧回路
807 復調回路
808 変調回路
809 論理回路
810 記憶回路
811 ROM
901 筐体
902 筐体
903 表示部
904 表示部
905 マイクロフォン
906 スピーカー
907 操作キー
908 スタイラス
911 筐体
912 筐体
913 表示部
914 表示部
915 接続部
916 操作キー
921 筐体
922 表示部
923 キーボード
924 ポインティングデバイス
931 筐体
932 表示部
933 リストバンド
941 筐体
942 筐体
943 表示部
944 操作キー
945 レンズ
946 接続部
951 車体
952 車輪
953 ダッシュボード
954 ライト
1189 ROMインターフェース
1190 基板
1191 ALU
1192 ALUコントローラ
1193 インストラクションデコーダ
1194 インタラプトコントローラ
1195 タイミングコントローラ
1196 レジスタ
1197 レジスタコントローラ
1198 バスインターフェース
1199 ROM
1200 記憶素子
1201 回路
1202 回路
1203 スイッチ
1204 スイッチ
1206 論理素子
1207 容量素子
1208 容量素子
1209 トランジスタ
1210 トランジスタ
1213 トランジスタ
1214 トランジスタ
1220 回路
2100 トランジスタ
2200 トランジスタ
2201 絶縁膜
2202 配線
2203 プラグ
2204 絶縁膜
2205 配線
2206 配線
2207 絶縁膜
2208 ブロック膜
2211 半導体基板
2212 絶縁膜
2213 ゲート電極
2214 ゲート絶縁膜
2215 ソース領域およびドレイン領域
3001 配線
3002 配線
3003 配線
3004 配線
3005 配線
3200 トランジスタ
3300 トランジスタ
3400 容量素子
4000 RFデバイス
8000 表示モジュール
8001 上部カバー
8002 下部カバー
8003 FPC
8004 タッチパネル
8005 FPC
8006 表示パネル
8007 バックライトユニット
8008 光源
8009 フレーム
8010 プリント基板
8011 バッテリー
Claims (13)
- 第1の酸化物半導体膜と、
前記第1の酸化物半導体膜上の第2の酸化物半導体膜と、
前記第2の酸化物半導体膜と接する領域を有するソース電極
前記第2の酸化物半導体膜と接する領域を有するドレイン電極と、
前記第2の酸化物半導体膜上、前記ソース電極上および前記ドレイン電極上の金属酸化物膜と、
前記金属酸化物膜上のゲート絶縁膜と、
前記ゲート絶縁膜上のゲート電極と、を有し、
前記金属酸化物膜は、M(Mは、Ti、Ga、Y、Zr、La、Ce、NdまたはHf)とZnを含み、
前記金属酸化物膜は、MとZnの原子数比をM:Zn=x:yとしたとき、x/(x+y)は、0.67より大きく0.99以下である部分を有することを特徴とする半導体装置。 - 第1の酸化物半導体膜と、
前記第1の酸化物半導体膜上の第2の酸化物半導体膜と、
前記第2の酸化物半導体膜と接する領域を有するソース電極
前記第2の酸化物半導体膜と接する領域を有するドレイン電極と、
前記第2の酸化物半導体膜上、前記ソース電極上および前記ドレイン電極上の金属酸化物膜と、
前記金属酸化物膜上のゲート絶縁膜と、
前記ゲート絶縁膜上で接し、前記第2の酸化物半導体膜の上面および側面に面するゲート電極と、を有し、
前記金属酸化物膜は、M(Mは、Ti、Ga、Y、Zr、La、Ce、NdまたはHf)とZnを含み、
前記金属酸化物膜は、MとZnの原子数比をM:Zn=x:yとしたとき、x/(x+y)は、0.67より大きく0.99以下である部分を有することを特徴とする半導体装置。 - 請求項1または請求項2において、
前記元素Mとして、Gaを含有することを特徴とする半導体装置。 - 請求項1乃至請求項3のいずれか一において、
前記第2の酸化物半導体膜は、複数の結晶部を有し、前記複数の結晶部において、c軸配向性を有し、かつc軸が前記第2の酸化物半導体膜の上面の法線ベクトルに平行な方向を向いていることを特徴とする半導体装置。 - 請求項1乃至請求項4のいずれか一において、
チャネル長が5nm以上200nm以下であることを特徴とする半導体装置。 - 請求項1乃至請求項5のいずれか一において、
前記第2の酸化物半導体膜の電子親和力は、前記第1の酸化物半導体膜の電子親和力よりも大きいことを特徴とする半導体装置。 - 請求項1乃至請求項6のいずれか一に記載の半導体装置を含むことを特徴とする電子機器。
- 基板上に第1の絶縁膜を形成し、
前記第1の絶縁膜上に第1の酸化物半導体膜を形成し、
前記第1の酸化物半導体膜上に第2の酸化物半導体膜を形成し、
前記第2の酸化物半導体膜上にソース電極およびドレイン電極を形成し、
前記第2の酸化物半導体膜上、前記ソース電極上および前記ドレイン電極上に金属酸化物膜を形成し、
前記金属酸化物膜上にゲート絶縁膜を形成し、
前記ゲート絶縁膜状にゲート電極を形成し、
前記金属酸化物膜は、M(Mは、Ti、Ga、Y、Zr、La、Ce、NdまたはHf)とZnを含み、
前記金属酸化物膜は、スパッタリングターゲットを用いてスパッタリング法により形成され、
前記金属酸化物膜は、スパッタリングターゲットが有するMとZnの原子数比をM:Zn=x:yとしたとき、x/(x+y)は、0.67より大きく0.99以下である部分を有することを特徴とする半導体装置の作製方法。 - 請求項8において、
前記ゲート電極上に第2の絶縁膜を形成することを特徴とする半導体装置の作製方法。 - 請求項8または請求項9において、
前記元素Mとして、Gaを含有することを特徴とする半導体装置の作製方法。 - 請求項8乃至請求項10のいずれか一において、
前記第2の酸化物半導体膜は、複数の結晶部を有し、前記複数の結晶部において、c軸配向性を有し、かつc軸が前記第2の酸化物半導体膜の上面の法線ベクトルに平行な方向を向いていることを特徴とする半導体装置の作製方法。 - 請求項8乃至請求項11のいずれか一において、
チャネル長が5nm以上200nm以下であることを特徴とする半導体装置の作製方法。 - 請求項8乃至請求項12のいずれか一において、
前記第2の酸化物半導体膜の電子親和力は、前記第1の酸化物半導体膜の電子親和力よりも大きいことを特徴とする半導体装置の作製方法。
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Also Published As
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KR102437450B1 (ko) | 2022-08-30 |
WO2015189731A1 (en) | 2015-12-17 |
TW201547030A (zh) | 2015-12-16 |
JP6630497B2 (ja) | 2020-01-15 |
TWI736038B (zh) | 2021-08-11 |
TWI680585B (zh) | 2019-12-21 |
KR20170015982A (ko) | 2017-02-10 |
TW202013748A (zh) | 2020-04-01 |
US9685563B2 (en) | 2017-06-20 |
US20160343867A1 (en) | 2016-11-24 |
US9349875B2 (en) | 2016-05-24 |
US20150364610A1 (en) | 2015-12-17 |
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