JP2016009843A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 56
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 15
- 238000000034 method Methods 0.000 claims abstract description 24
- 230000015572 biosynthetic process Effects 0.000 claims abstract description 20
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 17
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims description 40
- 238000000137 annealing Methods 0.000 claims description 10
- 230000000415 inactivating effect Effects 0.000 claims description 5
- 230000001590 oxidative effect Effects 0.000 claims description 5
- 238000005530 etching Methods 0.000 claims description 4
- 239000010410 layer Substances 0.000 abstract description 141
- 239000002344 surface layer Substances 0.000 abstract description 5
- 238000009413 insulation Methods 0.000 abstract 3
- 229910002601 GaN Inorganic materials 0.000 description 113
- 239000010408 film Substances 0.000 description 76
- 239000007789 gas Substances 0.000 description 18
- 229910002704 AlGaN Inorganic materials 0.000 description 16
- 150000001875 compounds Chemical class 0.000 description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 6
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 5
- 229910004298 SiO 2 Inorganic materials 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 239000012535 impurity Substances 0.000 description 4
- 229910021529 ammonia Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000010438 heat treatment Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910017107 AlOx Inorganic materials 0.000 description 2
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910018516 Al—O Inorganic materials 0.000 description 1
- -1 CF 4 Substances 0.000 description 1
- 229910005535 GaOx Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 230000001186 cumulative effect Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000002000 scavenging effect Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 230000005533 two-dimensional electron gas Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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Abstract
Description
本発明の第1実施形態について説明する。本実施形態では、GaNを主成分とする化合物半導体を用いたGaNデバイスを有する半導体装置として、GaN−HEMT(High electron mobility transistor:高電子移動度トランジスタ)デバイスの一つである横型のHEMTを備える半導体装置について説明する。
Si(111)やSiCおよびサファイヤなどの基板1の表面に、GaN層2およびn型のAlGaN層3が積層された構造を有する化合物半導体基板を用意する。例えば、基板1の表面に、GaN層2およびAlGaN層3をMOCVD(Metal Organic Chemical Vapor Deposition:有機金属気相成長)法や超高純度、高精度にしたMBE(Molecular Beam Epitaxy:分子線エピタキシー)法などによって形成する。
AlGaN層3の表面に、層間膜となる酸化膜10を形成した後、酸化膜10の表面に第2マスクとなるレジスト11を形成する。そして、フォトリソグラフィ工程を経てレジスト11をパターニングしたのち、このレジスト11をマスクとして酸化膜10をパターニングする。これにより、AlGaN層3の表面のうちゲート構造の形成予定位置においてレジスト11および酸化膜10が開口させられる。この後、レジスト11および酸化膜10をマスクとして用いたドライエッチング工程を行うことで、AlGaN層3の表面をリセス加工して、GaN層2の表面を露出させたリセス形状部3aを形成する。また、リセス形状部3aを形成した後、ドライエッチングのマスクとして用いたレジスト11を除去することで、ドライエッチング工程を終了する。
続いて、ゲート絶縁膜4の形成工程を行うが、上記のようにしてGaN層2の表面を露出させたのち、ゲート絶縁膜4の形成工程の前に、リセス形状部3aから露出させられたGaN層2の表面に存在するドナー元素の除去工程を行う。
ゲート絶縁膜4、ゲート電極5を覆いつつ、溝部3b、3cの形成予定領域が開口する絶縁膜およびマスクを形成する。例えば、絶縁膜については酸化膜12を形成した後、酸化膜12の表面にマスクとなるレジスト13を形成することで構成することができる。 この後、レジスト13を用いて酸化膜12およびAlGaN層3のドライエッチング工程を行うことで、AlGaN層3の表面に溝部3b、3cを形成する。この後、レジスト13を除去する。
本発明の第2実施形態について説明する。本実施形態は、第1実施形態に対して化合物半導体基板中におけるドナー元素濃度が異なっているが、その他に関しては第1実施形態と同様であるため、第1実施形態と異なる部分についてのみ説明する。
本発明は上記した実施形態に限定されるものではなく、特許請求の範囲に記載した範囲内において適宜変更が可能である。
2 GaN層
3 AlGaN層
3a リセス形状部
4 ゲート絶縁膜
5 ゲート電極
6 ソース電極
7 ドレイン電極
Claims (10)
- 半絶縁性もしくは半導体にて構成される基板(1)と、
前記基板上に形成されたGaN層(2)を含むチャネル形成層(2、3)と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜(4)が形成されていると共に、該ゲート絶縁膜を介して形成されたゲート電極(5)とを有するゲート構造と、
前記チャネル形成層上において、前記ゲート構造を挟んだ両側に配置されたソース電極(6)およびドレイン電極(7)と、を備えたGaNデバイスを含み、
前記ゲート絶縁膜と前記GaN層との界面および該界面より前記GaN層側における格子位置でのドナー元素濃度が5.0×1017cm-3以下に設定されていることを特徴とする半導体装置。 - 半絶縁性もしくは半導体にて構成される基板(1)と、
前記基板上に形成されたGaN層(2)を含むチャネル形成層(2、3)と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜(4)が形成されていると共に、該ゲート絶縁膜を介して形成されたゲート電極(5)とを有するゲート構造と、
前記チャネル形成層上において、前記ゲート構造を挟んだ両側に配置されたソース電極(6)およびドレイン電極(7)と、を備えたGaNデバイスを含み、
前記ゲート絶縁膜と前記GaN層との界面でのドナー元素濃度が5.0×1017cm-3を超えており、前記ゲート絶縁膜と前記GaN層との界面より前記GaN層側における格子位置でのドナー元素濃度が5.0×1017cm-3以下に設定されていることを特徴とする半導体装置。 - 前記ドナー元素はSiもしくはOであることを特徴とする請求項1または2に記載の半導体装置。
- 前記ドナー元素は、前記格子位置において3.5×1017cm-3以下に設定されていることを特徴とする請求項1ないし3のいずれか1つに記載の半導体装置。
- 半絶縁性もしくは半導体にて構成される基板(1)と、
前記基板上に形成されたGaN層(2)を含むチャネル形成層(2、3)と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜(4)が形成されていると共に、該ゲート絶縁膜を介して形成されたゲート電極(5)とを有するゲート構造と、
前記チャネル形成層上において、前記ゲート構造を挟んだ両側に配置されたソース電極(6)およびドレイン電極(7)と、を備えたGaNデバイスを有する半導体装置の製造方法であって、
前記基板上に前記GaN層を含むチャネル形成層を形成する工程と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜を形成する工程とを含み、
前記チャネル形成層を形成する工程の後、前記ゲート絶縁膜を形成する工程の前に、前記GaN層のうち前記ゲート絶縁膜と接する部分に存在するドナー元素を除去する工程を行い、
前記ドナー元素を除去する工程の後、前記ドナー元素を含む雰囲気に暴露することなく前記ゲート絶縁膜を形成する工程を行うことを特徴とする半導体装置の製造方法。 - 前記チャネル形成層の上に前記ゲート構造の形成予定位置が開口するマスク(10、11)を形成したのち、該マスクを用いたエッチングにより前記GaN層を露出させるリセス形状部(3a)を形成する工程を含み、
前記リセス形状部を形成する工程の後に、前記ドナー元素を除去する工程を行うことを特徴とする請求項5に記載の半導体装置の製造方法。 - 前記ドナー元素を除去する工程は、F系ガス、Cl2系ガス、H2ガス、HClガスのいずれかを用いてアニール処理を行う工程であることを特徴とする請求項5または6に記載の半導体装置の製造方法。
- 半絶縁性もしくは半導体にて構成される基板(1)と、
前記基板上に形成されたGaN層(2)を含むチャネル形成層(2、3)と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜(4)が形成されていると共に、該ゲート絶縁膜を介して形成されたゲート電極(5)とを有するゲート構造と、
前記チャネル形成層上において、前記ゲート構造を挟んだ両側に配置されたソース電極(6)およびドレイン電極(7)と、を備えたGaNデバイスを有する半導体装置の製造方法であって、
前記基板上に前記GaN層を含むチャネル形成層を形成する工程と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜を形成する工程とを含み、
前記チャネル形成層を形成する工程の後、前記ゲート絶縁膜を形成する工程の前もしくは後に、前記GaN層のうち前記ゲート絶縁膜と接する部分に存在するドナー元素を不活性化する工程を行うことを特徴とする半導体装置の製造方法。 - 前記ドナー元素を不活性化する工程は、酸化雰囲気中でのアニール処理を行う工程であることを特徴とする請求項8に記載の半導体装置の製造方法。
- 半絶縁性もしくは半導体にて構成される基板(1)と、
前記基板上に形成されたGaN層(2)を含むチャネル形成層(2、3)と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜(4)が形成されていると共に、該ゲート絶縁膜を介して形成されたゲート電極(5)とを有するゲート構造と、
前記チャネル形成層上において、前記ゲート構造を挟んだ両側に配置されたソース電極(6)およびドレイン電極(7)と、を備えたGaNデバイスを有する半導体装置の製造方法であって、
前記基板上に前記GaN層を含むチャネル形成層を形成する工程と、
前記チャネル形成層上に、前記GaN層に接するゲート絶縁膜を形成する工程とを含み、
前記チャネル形成層において前記GaN層を形成したのち、前記GaN層のうち前記ゲート絶縁膜と接する部分に存在するドナー元素が活性化する温度以下にサーマルバジェットを制限して前記GaNデバイスを形成することを特徴とする半導体装置の製造方法。
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