JP2015201620A - 埋め込みチップを作製する方法 - Google Patents
埋め込みチップを作製する方法 Download PDFInfo
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- JP2015201620A JP2015201620A JP2014250273A JP2014250273A JP2015201620A JP 2015201620 A JP2015201620 A JP 2015201620A JP 2014250273 A JP2014250273 A JP 2014250273A JP 2014250273 A JP2014250273 A JP 2014250273A JP 2015201620 A JP2015201620 A JP 2015201620A
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Abstract
【解決手段】チップソケットのハニカムアレイを入手するステップ、ハニカムアレイを下面が透明テープに載置するステップ;ダイの下面が透明テープと接触するようにフリップチップにして配置するステップ、テープを通した光学撮像を使用してチップをビアポストと位置合わせするステップ、パッキング材をチップ上及び周りに塗布し硬化してチップを埋め込むステップ、パッキング材を薄く且つ平坦化してビアの上端部を露出するステップ、透明テープを除去するステップ;導体のフィーチャ層をハニカムアレイの下面及びチップの下面に塗布して各ダイの端子を貫通ビアに結合するステップ、導体が貫通ビアから各チップ上に延伸するように導体のフィーチャ層を塗布するステップ及びアレイをダイシングして埋め込みチップを含む分離したダイを作成するステップから成る。
【選択図】図8
Description
各チップソケットが、第1ポリマーのポリマーマトリクス及び各ソケット周りにフレームワークを通る少なくとも1つのビアポストを有するフレームワークによって囲まれるような、チップソケットのアレイを入手し;
ハニカムアレイを、該アレイの下面が透明テープに接触するように、上記透明テープ上に載置し;
上記ダイの下面が上記透明テープと接触するように、チップ端子を下側にして各チップソケット内に配置し;
テープを通した光学撮像を使用して、上記チップを上記ビアポストと位置合わせし;
パッキング材を上記アレイ内で上記チップ上及び周りに塗布し、フィラーを硬化して、チップを5面で埋め込み;
パッキング材を薄く且つ平坦化して、上記ビアの上端部を、上記アレイの上面で露出し;
透明テープを除去し;
導体のフィーチャ層を、上記アレイの上記下面及び上記チップの上記下面に塗布して、各ダイの少なくとも1つの端子を、少なくとも1つの貫通ビアに結合し;
少なくとも1つの導体が、貫通ビアから、各チップ上に少なくとも部分的に延伸するように、導体のフィーチャ層を、上記アレイの上側に塗布し;
上記アレイをダイシングして、上記チップと隣接する貫通ビアに結合されるコンタクトパッドを有する少なくとも1つの埋め込みチップを含む分離したダイを作成すること
を含む方法。
犠牲キャリアを入手し;
フォトレジスト層を敷設し;
フォトレジストを銅ビアのグリッドでパターニングし;
銅ビアポストを該グリッドになるようにメッキし;
フォトレジストを剥離し;
銅ビアポストをポリマー誘電体で積層し;
銅ビアの端部を露出するように、ポリマー誘電体を薄く且つ平坦化し;
キャリアを除去し;
ポリマー誘電体内にチップソケットを機械加工することによって、作製される。
犠牲キャリアを入手し;
フォトレジスト層を敷設し;
フォトレジストを、銅ビアのグリッドで、及びソケットのアレイでパターニングし;
銅ビアポストを、グリッド及びアレイになるようにメッキし;
フォトレジストを剥離し;
銅ビアポスト及びアレイをポリマー誘電体で積層し;
銅ビア及びアレイの端部を露出するように、ポリマー誘電体を薄く且つ平坦化し;
ソケットを形成するために、銅ビアの端部を遮蔽し、アレイを選択的に溶解し;
キャリアを除去することによって、作製されることを含む。
銅クラッドポリマーマトリクスを含む基板を入手し;
ビアホールのアレイを穿孔し;
銅でビアホールに電気メッキし;
銅クラッド部を除去し;
基板を通して、ソケットを機械加工することを含む。
12 チップソケット
14、124、210 ビア
16、18、38、206 フレーム
20 パネル
21、22、23、24 ブロック
25 水平方向バー
26 垂直方向バー
27 外部フレーム
28、29 チップソケット
35、55 チップ
36、208 パッキング材
40 フレームワーク
42、43 ルーティング層
45 ダイシングツール
48 ダイパッケージ
57 半田ボール
120 グリッド
122 有機マトリクスフレーム
126 ソケット
130 テープ
132、202 ダイ
134 パッケージ材
136 銅キャリア
138 シード層
140、150 フォトレジスト層
142 導電性フィーチャ
144 エッチングバリア
146 接着性金属シード層
148 銅シード層
152 パターン
154 銅
200 構造体
204 コンタクト
Claims (20)
- 埋め込みダイパッケージを作製する方法であって、該方法は:
各チップソケットが、第1ポリマーのポリマーマトリクス及び各ソケット周りにフレームワークを通る少なくとも1つのビアポストを有するフレームワークによって囲まれるような、チップソケットのアレイを入手すること;
ハニカムアレイの下面が透明テープに接触するように、前記フレームワークを有する前記アレイを前記透明テープに載置すること;
前記ダイの下面が前記透明テープと接触するように、チップ端子を下側にして各チップソケット内に配置すること;
前記テープを通して光学撮像することによって、前記チップを前記ビアポストと位置合わせすること;
パッキング材を前記アレイ内で前記チップ上及び周りに塗布し、フィラーを硬化して、前記チップを5面で埋め込むこと;
前記パッキング材を薄く且つ平坦化して、前記ビアの上端部を、前記アレイの上面で露出すること;
前記透明テープを除去すること;
導体のフィーチャ層を、前記ハニカムアレイの前記下面及び前記チップの前記下面に塗布して、各ダイの少なくとも1つの端子を、少なくとも1つの貫通ビアに結合すること;
少なくとも1つの導体が、貫通ビアから、各チップ上に少なくとも部分的に延伸するように、導体のフィーチャ層を、前記ハニカムアレイの上側に塗布すること、及び
前記アレイをダイシングして、前記チップと隣接する貫通ビアに結合されるコンタクトパッドを有する少なくとも1つの埋め込みチップを含む分離したダイを作成すること
を含む方法。 - 前記アレイは、長方形をしたセルのアレイを含む、請求項1に記載の方法。
- 前記チップは、アナログプロセッサ、デジタルプロセッサ、センサ、フィルタ、及びメモリの中の少なくとも1つを含む、請求項1に記載の方法。
- 前記フレームワークは、前記第1ポリマーにガラス繊維強化材を含む、請求項1に記載の方法。
- 前記フレームワークは、前記第1ポリマーにガラス繊維束の織物を含む、請求項1に記載の方法。
- 前記パッキング材は、第2ポリマーマトリクスを含む、請求項1に記載の方法。
- 前記パッキング材は、成形コンパウンドを含む、請求項1に記載の方法。
- 前記パッキング材は、前記フレームワーク及びチップ上に被せられ、加熱加圧される少なくとも1枚のポリマーシートを含む、請求項1に記載の方法。
- 前記パッキング材は、粒子フィラー及び短繊維フィラーの少なくとも1つを更に含む、請求項6に記載の方法。
- 前記チップソケットのアレイは:
犠牲キャリアを入手すること;
フォトレジストの層を敷設すること;
前記フォトレジストを銅ビアのグリッドでパターニングすること;
銅ビアポストを前記グリッドになるようメッキすること;
前記フォトレジストを剥離すること;
前記銅ビアポストをポリマー誘電体で積層すること;
前記銅ビアの端部を露出するように、前記ポリマー誘電体を薄く且つ平坦化すること;
前記キャリアを除去すること;及び
前記ポリマー誘電体内にチップソケットを機械加工することによって、作製される、請求項1に記載の方法。 - 前記犠牲キャリアは、銅を溶解することによって除去される銅キャリアである、請求項10に記載の方法。
- 銅ビアを堆積する前に、前記キャリア上に耐エッチング層を塗布することを更に含む、請求項10に記載の方法。
- 銅ビアの端部を露出した状態の平坦化されたポリマー誘電体は、銅キャリアがエッチング除去される間、耐エッチング材で保護される、請求項10に記載の方法。
- 前記耐エッチング材は、フォトレジストである、請求項13に記載の方法。
- 前記ポリマー誘電体は、ガラス繊維束の織物を含み、プリプレグとして塗布され、その後硬化される、請求項11に記載の方法。
- 前記チップソケットのアレイは:
犠牲キャリアを入手すること;
フォトレジスト層を敷設すること;
前記フォトレジストを、銅ビアのグリッドで、及びソケットのアレイでパターニングすること;
銅ビアポストを、前記グリッド及び前記アレイになるようにメッキすること;
前記フォトレジストを剥離すること;
前記銅ビアポスト及び前記アレイをポリマー誘電体で積層すること;
銅ビア及びアレイの端部を露出するように、前記ポリマー誘電体を薄く且つ平坦化すること;
前記ソケットを形成するために、前記銅ビアの端部を遮蔽し、前記アレイを選択的に溶解すること;及び
前記キャリアを除去することによって、作製される、請求項1に記載の方法。 - 前記ハニカムアレイは:
銅クラッドポリマーマトリクスを含む基板を入手すること;
ビアホールのアレイを穿孔すること;
銅で前記ビアホールに電気メッキすること;
銅クラッド部を除去すること;及び
前記基板を通して、ソケットを機械加工することによって、作製する、請求項1に記載の方法。 - 前記銅クラッド部を除去するステップは、溶解、研削及びプラズマエッチングの中の少なくとも1つを含む、請求項17に記載の方法。
- 前記ポリマーマトリクスは、ガラス繊維を更に含む、請求項17に記載の方法。
- 前記ソケットを機械加工して除去するステップは、打ち抜き及びCNCの中の少なくとも1つを含む、請求項17に記載の方法。
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US14/249,282 US9240392B2 (en) | 2014-04-09 | 2014-04-09 | Method for fabricating embedded chips |
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JP (1) | JP6090295B2 (ja) |
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CN104332414B (zh) | 2017-08-29 |
TW201539699A (zh) | 2015-10-16 |
JP6090295B2 (ja) | 2017-03-08 |
CN104332414A (zh) | 2015-02-04 |
US9240392B2 (en) | 2016-01-19 |
KR101648365B1 (ko) | 2016-09-01 |
US20150294896A1 (en) | 2015-10-15 |
TWI625839B (zh) | 2018-06-01 |
KR20150117195A (ko) | 2015-10-19 |
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