TW523886B - Cavity down ball grid array carry plate structure by laser drill to enhance heat dissipation chip embedment and its manufacturing method - Google Patents

Abstract

A kind of cavity down ball grid array carrier structure for heat dissipation enhanced chip and its manufacturing method based on the metal stiffener in multi-layer are disclosed in the invention. In the invention, the application of metal stiffener to match IC package requirement is obtained, and the metal stiffener thickness can be flexibly adjusted to provide the design applications of supporting plat bending, plate warping and increasing heat dissipated power. In addition, the invented structure design can use surface finishing process of electroplated nickel/gold such that it is capable of using full body gold process without the need of electroplating wire-deposition design to perform the processing technique of surface finishing process of electroplated nickel/gold. Additionally, by using laser to drill micro-hole for increased layer to manufacture through holes, wire disposition space of electroplated conduction wire harness is decreased such that the increased space is capable of increasing the other I/O layout application requirement. Furthermore, the application of micro through-hole layout can be varied and can be completely symmetrical, or stacked, or layer-by-layer increasing type.

Description

523886 V. Description of the Invention (1) [Field of the Invention The present invention relates to a structure and a manufacturing method of laser array = enhanced heat dissipation chip embedded downward spherical array carrier board used in semiconductor packaging process, which can solve the problem of I c package. The problems of heat dissipation, temperature reduction, and trace back of the end of the plated wire cause interference noise and increase other I / O layout requirements. [Background of the Invention]: The trend of thinner and thinner: t It ^, coupled with the increasing number of functions,! = 0 the number of products also continues to increase the function of the "products are constantly updated to respond to actual needs, so Its relative closure must also be compatible with the technology of FUp Chip. Today, the latest ball grid arrays in the tier-tier products are now the current packaging system; J, and the second highest] power density ic also uses ball grids. Array side sealing master ::] This many (BGA) 1/0 package density is lower than other sealing V% ': 疋 Your ball grid array power is 1C for a long time use, you have to have a lot of high design cooling structure In order to be able to use only ^, ri ..., Ϊ, it is necessary to have the function of capturing 1G to operate normally. Know how to improve high-power 1C heat dissipation (Ceramic 0r Plastic BGA) chip = two, two organic carrier boards Heat sinks can also be provided in addition-some with loose: externally attached fin type, but because of these conventional ,,, and effective packaging, the production process makes the seal

523886 V. Description of the invention (2) ~ " The cost of mounting is increased, and the chip cannot directly contact the heat dissipation fins, so that the heat dissipation effect is not good. In addition, the world ’s largest packaging company Amk〇r / Anam launched SuperBGA and Texas Instruments ’(Star) uStarBG, similarly designed with Heat Sink and embedded downward to try to enhance its heat dissipation effect, which is basically based on BT material. PBGA, and mechanical drilling as a via (aperture Φ 2 50 ιιιι), and electroplated nickel / gold conductive wire method is needed, but it still cannot reach the micro via (aperture φ 5 with laser drilling) provided by the present invention. 〇 ~ 〇1 50um).

Generally, the design of BGA carrier board takes into consideration the influence of heat dissipation efficiency on the chip. Generally, the ground layer (GND-Ground_large area metal layer) is designed as the bottom layer. It takes three layers as an example. Its three layers are not Layer!-Layer 2 is the signal layer, and _ " is the ground layer. When used in high-speed logic circuits, there will be crosstalk ("M " interference because of dense wiring" too close), so the present invention The structure has been provided with multiple pieces of excellent heat dissipation efficiency, so when designing, it can be provided by tlffener) and use Uyer 1 & Uyer ft to move to 2. The problem is solved. At first, it is the line signal layer, so the string can be added to the invention. Revealing the wiring instructions of You Youxiong and Xu Gujian ^ keyless wires _ 'can be structured with / c,.,,,? And using multiple pieces of metal reinforcement> (SUffener) reinforcement structure, etc. ^ The soil seven alpha accounted for 'so the manufacturing method of the design of the present invention can completely cover the disadvantages of the conventional method before the +, π + k η I 0.

523886

V. Description of the invention (3) [Objective of the invention] The heat dissipation function is limited and the manufacturing disadvantages are a complete solution. The purpose of the present invention is to combine the complicated procedures in the conventional technology with high cost and low wiring density (T ota 1 S). ο 1 uti 〇η) 〇 Therefore, in order to achieve the above purpose, the present invention of 山 1 × 44, η 山 X 4 is provided for laser drilling to strengthen the structure and manufacture of a hot-type solar panel inserted into a downward-shaped spherical array carrier board. The method includes: • providing a first substrate, the second metal layer and a third metal layer film image transfer mode, leaving the line 'and opening a laser mask in the opening of the first laser mask; A '' is formed on the surface in advance to form an inner layer circuit; a second metal layer is used to form a second metal layer; a third metal layer is formed on the third metal layer to form a plurality of third substrates; a second substrate is laminated on the surface of the second metal layer circuit; Lamination—a second substrate, and a first metal layer is formed on the second substrate to form an outer circuit; a laser drilled hole forms a third through hole, which is laser-drilled to the second metal Layer to the second metal A plurality of third through holes are formed between the layers, or a plurality of third through holes are formed between the third metal layer and the first metal layer; a metal material is plated in the third through holes, and then a dry film image is formed. The third metal layer is etched in a transfer manner to form a third metal layer circuit. • A second substrate is pressed and bonded to a surface of the third metal layer circuit.

523886 V. Description of the invention (4) The first substrate 'and the second substrate has a metal reinforcement structure; and a laser mask is opened on the first metal layer by a dry film image transfer method. Forming a plurality of first laser reticle openings; • laser drilling to form a first through hole, forming a plurality of first through holes between the first metal layer and the second metal layer by laser drilling, After plating a metal material in the first through hole, nickel-gold plating is performed on the first metal layer in a dry film image transfer manner, and then the first metal layer is line-etched to form a first metal layer. Circuitry; • A solder resist is printed on the surface of the first metal layer circuit, and the first, second, and third substrates are cut through to form a wafer embedding area, and a heat sink (Heat Sink) is pressed on the circuit. One side of the second substrate is ugly and underheated. [Detailed description of the embodiment of the present invention] The present invention provides a method for manufacturing a laser drilled hole-enhanced heat-dissipating chip embedded downward spherical array carrier board, such as the first ( A) Picture ~ shown in the first (up) picture: Including the following steps ... 'Provide a first substrate step, the first substrate 101 gets on and off the vehicle, and a second metal layer 102 and a third metal layer 103 are formed on the surface in advance, as shown in the first (A) diagram, In order to form an inner layer circuit, the material of the first substrate 101 may be a Bissaleimide Triazine (BT) dielectric material or other organic materials or even an inorganic ceramic material, and the thickness is about 60%. m,

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In addition, the first metal layer 102 and the third golden sound 103 (Cu) have a thickness of about 12.饨: 枓 can be -thinning the copper m-Fi 1 layer 2 and the third metal layer 103, as shown in Figure-(B), the thick and thin place of thinning is like a square move, "弟A π, again 9 Am, and then using a dry film 104 image to turn a ') picture, the second metal layer is etched to form a two metal layer circuit 102a' 丨 and the second metal layer circuit i〇2a U is formed. A black oxidation step is further added to 'emulsify the second metal layer circuit 102 & surface black (Black Oxide) to form a second black oxide layer. The laser mask 105 is opened on the third metal layer 103, and a plurality of third laser masks are formed as shown in the first (D) diagram. A step of pressing a second substrate 106, combining a second substrate 106 and a metal layer 107 with a thermal compression bonding method on the surface of the second metal layer circuit 102 and the first (E) diagram The second substrate 106 may be a resin layer having a thickness of about 50 ~ 100 0 // m. A metal layer is used to form an outer layer line S /. The material of the first metal layer 107 on 106 may be copper (Cu), and the thickness is about 9 // m. The step of forming a third through hole by laser drilling is performed by laser drilling. As shown in the first (F) diagram, a step is formed between the third metal layer 103 and the second metal layer 102. A plurality of third through holes 108a, or a plurality of third through holes 108a formed between the third metal layer 107 and the first metal layer 107; and the third through holes 108a, After the metal plating material 108b in 108b is shown in the first (G) diagram, the metal plating material in the third through hole may be copper (Cu), and the thickness is about

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1 5 // in, then, shown; then tr u〇 image transfer method, such as the first (H) Figure 10 3a, as the third metal layer 103 forms a third metal layer line ma, peel ; Shows' wherein the first metal layer circuit oxide layer 7, and, the surface of the black oxide (Black Oxide), forming a first black pressed one ^-«-1111. Brother II substrate 111 step, in the third metal Layer line I 0 3a two third substrates m, as shown in the first (J) diagram, wherein the third

2. The material is made of a Bisaleimide Triazine (BT) dielectric material or other organic thermocompression bonding material to combine the third substrate. Work 1: It has one or more metal stiffener structures. ^ /, The material of the metal reinforcement sheet in Zhongzhi can be a copper (Cu), I Lu (A1) or its dagger 6 gold to provide design support for the bending of the plate and increase the heat dissipation power; and then use a dry film 112 image In the transfer method, as shown in the first (κ) diagram, the laser mask 113 is opened to form a plurality of first laser mask openings on the first metal layer 107, as shown in the first (L) diagram;

The step of forming a first through hole by laser drilling is to form a plurality of first through holes 114 ′ between the first metal layer 107 and the second metal layer 丨 2 by laser drilling. (Μ), and after the first through hole 丨 4 is plated with a metal material 115, as shown in the first (N) diagram, the first plated through hole 114 may be copper ( Cu), with a thickness of about 1 5 // m; and then transfer the image of a dry film 116 as shown in the first (0) figure; and then the first metal

Page 10 523886 V. Description of the invention (7) Electroplated nickel-gold 117 on the layer, as shown in the first (p) diagram; then, the first metal layer 107 is line-etched, as shown in the first (q) diagram. As shown, a first metal layer circuit 107a is formed; a step of forming a solder resist is performed by printing and spraying (Spray

Coat ing) or roller coating (Roner coat ing) and other methods to form a solder resist 118 on the surface of the first metal layer circuit 107a, and open / pattern (Pattern) by the exposure and development process, as described in As shown in FIG. 1 (R), the first substrate 101, the second substrate 106, and the third substrate 1U are cut into holes, as shown in FIG. 1 (s), to form a wafer sinking area Η 9, and A heat sink UtKHeat Sink is pressed, as shown in the first (τ) diagram, on one side of the third substrate for heat dissipation. Moreover, the structure formed by the above manufacturing method according to the present invention is shown in FIG. 1 and includes: a first substrate 201, the upper and lower surfaces of the first substrate having a second metal layer 202 and a third metal layer Circuit 203 to form an inner-layer circuit; a second substrate 206, which forms the surface of the circuit m, and is formed on the second substrate 206: a road 207 to form an outer-layer circuit; $ t Layer line-a plurality of third through holes 2G8, which are formed by laser drilling of metal layer lines m to M, two metal layer wires 2, three metal layer lines m to the first metal layer line 2 shaped three through holes 20δ Metal-plated material 209 ·, ▶

Page 11 523886 V. Description of the invention (8)-A third substrate 211 is formed on the surface of the third metal layer circuit 203, and the third substrate 211 has one or more metals in it Stiffener structure; a plurality of first through holes 2 1 4 are formed by laser drilling between the first metal layer line 207 to the second metal layer line 202, and the first through hole 214 中 plated metal material 215, the first metal layer circuit is electrically recorded with gold 217; ,,,,,, '

A solder resist 218 is formed by printing methods such as spray coating or roller coating, and the solder resist is formed on the surface of the first metal layer line 207, and the first substrate 201, the second substrate 206 and the third substrate 211 are perforated to form a wafer embedding region 219, and a heat sink 220 (Heat Sink) is provided on one side of the third substrate 211. In order to reduce the temperature of the chip and enhance the heat dissipation effect in the conventional technology, the back of the chip on the PBGA carrier board and the fin-type heat sink are attached to increase the heat dissipation power and reduce the temperature of the chip. Resistance (Thermal Resistance) is about 2.4DC / Watts, the thermal resistance of the 4-layer board

The Thermal Resistance is about i · 8 t / WaUs. When the above embodiments of the present invention use one or more metal stiffeners as heat sinks, the chip is directly embedded downward. The structure of (Cavity Down) sticks to the heat sink, so its Thermal Resistance can be greatly reduced to about 13c / Watts. As shown in the third figure, it will enhance the heat dissipation power and provide power to 5 watts. The above IC is used.

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Another embodiment of the present invention (Bussless) design, so PrS * 1 purpose * 5Γ of electrical noise, 丨

It is a common practice for the circuit layout to use non-plated wires, so the signal at the end of the plated wires is traced back. The resulting dry ... — Reduces the wiring space of plated wires. Applications that require more I / O layout can be increased without changing the area of the carrier board. Wiring density to greatly reduce costs, including at least the following steps to provide a substrate, the substrate 3 01 is formed in advance a first metal layer 302 and a first metal layer 303; drilling and mineral metal in the hole steps, tied to the substrate 301. The first metal layer 302 and the second metal layer 303 are drilled through holes 304 in a laser manner, and a metal layer is plated in the through holes. The step of forming a nickel-gold layer is to first form a dry layer. Film 306, and a nickel-plated gold layer 3007 is formed on the surface of the metallized layer 305 on the first metal layer 302 and the second metal layer 3 by image transfer; a step of forming a metal circuit by money The first step is to form a dry film 308, the engraved edge ore metal layer 305, the first metal layer 302, and the second metal layer 303 to form a metal circuit; and print a solder resist step 309. Because the general BGA board design considers the heat dissipation efficiency, the ground screen (GND-Ground-large area metal layer) is usually placed at the bottom. The three-layer board is used as an example. The structure is Layer 1-Layer 2 is the signal layer. Uyer 3 is the ground plane. This design is used in high-speed logic circuits due to dense wiring and communication 523886.

The layer moved closer and there was crossTaik interference. Therefore, in the present invention, the structure i = f 4 ί or more metal stiffeners (St i f f ener) provides excellent dispersion ..., $ rate, so the design moves the ground layer to Uyer 2, j and

Layer 3 puts the line signal layer to solve the problem of crosstalk. In addition, the present invention further discloses a method using a metal stiffener as a basis, and a via hole made with a laser drill to make a via hole: $ Connect the circuit between the structure of the on-board board and the full-body gold plating process. Gold Process), a multi-layer on-board board structure for producing electroless nickel / gold surface-treated circuits without conductive wires, and a manufacturing method for forming the structure, wherein a circuit layout of the present invention is designed and manufactured with electroless wires (B = sless) The layout of the holes can be used in different ways, such as complete symmetry, stacking type, and two layer-by-layer additions. For example, the fifth (person) diagram ~ the fifth invention compares the "existing technology" with the advantages of the invention: Metal stiffeners are used as heat sinks, and the chip directly adheres to its thermal resistance (Thermal Resistane ^ The drop is about 1.3t: / WattS, which will provide power to 5 WaUs [C use. 2 · Bussless design of trace line production line back to the production bureau, the problem of interference noise at the end of the plated wire can be solved, reducing the layout of the plated wire °

523886 V. Description of the invention (11) The line can provide more space to increase other 1/0 layout requirements. It can increase the wiring density without changing the area of the carrier board and greatly reduce the cost. ’3: = The process of plated nickel / gold plating and the process of laser micro-hole vias are used to manufacture the structure carrier of the present invention. I know that the support is facing downwards: ^ "The invention of a laser drilled hole to strengthen the heat sinking chip technology = = column carrier board structure and manufacturing method", can indeed be carried by the pace disk] the purpose and efficacy, in line with The new borrowing of invention patents and the requirements of industrial utilization. Ji | Wang Wei, the examples are only the figures and descriptions of the disclosure, which are only the best examples of the present invention. They are not used to define each of the present invention. = Change = It is understood that the technical information is within the scope of the patent application of the following case ... Modifications should be 523886 Simple illustration [Schematic illustration] The first (A) ~ the first (τ) Schematic diagram of a method for manufacturing a laser drilling-enhanced heat-dissipating wafer embedded downward-shaped spherical array carrier board provided by the invention The second figure is a schematic diagram of a laser drilling-enhanced heat-dissipating wafer embedded downward-shaped spherical array carrier board The third figure is a schematic diagram of the comparison between the conventional double-sided panel 1 (Thermal Resistance) and the embodiment of the present invention. Η The electroless plated wire. The fourth figure is a manufacturing method of a bussless design provided by the present invention. The fifth (A) to fifth (D) pictures are one of the inventions. The lunar plate of the vias designed for the manufacture of the vias is made of non-electrical symmetry, stacked, layer-by-layer, and other changes. For complete [illustration of number] A substrate 101, a second metal layer 102, a second metal layer circuit 102a, and a third metal layer 103

Page 16 523886 Schematic illustration of dry film 104 laser reticle 105 second substrate 106 first metal layer 107 first metal layer circuit 107a second through hole 108a second through hole 108b metal plating material 109 dry film 110 second substrate 111 Dry film 112 Laser mask 113 First through hole 114 Metal plated material 115 Dry film 116 Electroplated nickel gold 117 Solder resist 118 Wafer entry area 119 Heat sink 120 First — substrate 201 Second metal layer circuit 202 Third metal layer Circuit 203 first substrate 206

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523886 The diagram briefly illustrates the first metal layer circuit 207 the second through hole 208 metal plated material 209 the second substrate 211 the first through hole 214 metal plated material 215 electroplated nickel gold 217 solder resist 218 chip desired area 219 heat sink 220 Substrate 301 First metal layer 302 Second metal layer 303 Laser drilling through holes 304 Metal plating 305 dry film 306 through hole nickel-plated gold layer 307 dry film 308 printing solder resist 309

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Claims (1)

523886 6. The scope of the patent application is to electroplat gold on the first metal layer, and then perform line # engraving on the first metal layer to form a first metal layer circuit. • Form a solder resist, which is printed by a Spray coating or roller coating, etc., forming the solder resist on the surface of the first metal layer circuit, and cutting the first, second and third substrates to form a wafer The heat sink is embedded in the area, and a heat sink is pressed on one side of the third substrate for heat dissipation. 2. The manufacturing method as described in item 1 of the scope of patent application, wherein the first substrate material may be a Bismaleimide Triazine (BT) dielectric material or other organic materials or even inorganic ceramic materials. The thickness is about 6 ◦ to 300 // m, and the material of the second metal layer and the third metal layer may be copper (Cu), and the thickness is about 12 // m. 3. The manufacturing method according to item 1 of the scope of patent application, wherein before the second metal layer is etched, the second metal layer and the third metal layer can be thinned, and the thinned thickness is about 9 // m. 4. The manufacturing method according to item 1 of the scope of patent application, wherein after forming the second metal layer circuit, a black oxidation step may be added to black oxidize the surface of the second metal layer circuit (B 1 ack 0 X ide ) To form a second black oxide layer. 5. The manufacturing method as described in item 1 of the scope of patent application, wherein the second base Page 20 523886 6. Scope of patent application The board can be a resin layer with a thickness of about 50 ~ 100 0 // m. 6. The manufacturing method according to item 1 of the scope of patent application, wherein the material of the first metal layer on the second substrate may be copper (Cu), and the thickness is about 9 // m. 7. The manufacturing method according to item 1 of the scope of patent application, wherein the third through hole and the first through hole can be plated with copper (Cu) and the thickness is about 15 // m ° 8. The manufacturing method described in the first item of the patent application, wherein after forming the first metal layer circuit, a black oxidation step may be further performed to black oxidize the surface of the first metal layer circuit (B 1 ack OX X ide), A first black oxide is formed. The manufacturing method as described in item 1 of the scope of patent application, wherein the third substrate material may be a Bisaleimide Triazine (BT) dielectric material or other organic thermocompression bonding material . 1 0. A laser drilling enhanced heat sinking chip embedded downward-shaped spherical array carrier board structure includes: a first substrate having a second metal layer circuit and a third metal layer circuit on the upper and lower surfaces of the first substrate; To form an inner layer circuit; a second substrate formed on the second metal layer circuit Page 21 523886 6. The surface of the patent application, and a first metal layer circuit is formed on the second substrate to form an outer layer circuit. • A plurality of third through holes are laser-drilled on the first substrate. Formed between a three metal layer circuit and the second metal layer circuit, or between the third metal layer circuit and the first metal layer circuit; and a metal material is plated in the third through hole, a third substrate, the A third substrate is formed on the surface of the third metal layer circuit, and the third substrate has one or more metal stiffener structures, wherein the metal stiffener material may be copper (Cu). , Aluminum (A1) or other alloys to provide design and application of supporting plate bending, plate warping and improving heat dissipation power; • A plurality of first through holes are laser-drilled in the first metal layer line to the The second metal layer is formed between the lines, and the first through hole is plated with a metal material, and the first metal layer line is plated with nickel gold; a solder resist, which is spray-printed (Spray Coating) ) Or roller coating (Roller Co In an ating method, the first metal layer circuit surface is formed, and the first, second and third substrate cut holes form a wafer embedding area, and a heat sink is provided on one side of the third substrate. . 11. The structure described in item 10 of the scope of patent application, wherein the first substrate material can be a Bisaleimide Triazine (BT) dielectric material or other organic materials or even an inorganic ceramic material, thickness About 60 ~ 300 "m, and the material of the second metal layer and the third metal layer may be copper Page 22 523886 6. Patent application scope (Cu), thickness is about 12 // m. 12. The structure according to item 11 of the scope of patent application, wherein the second metal layer and the third metal layer can be thinned to a thickness of about 9 β m. 13. The structure as described in item 10 of the scope of patent application, wherein a second black oxide layer can be formed on the circuit surfaces of the first metal layer and the second metal layer, and the second black oxide layer is formed by using a black oxidation step. The surface of the metal layer circuit is black oxidized (B 1 ack oxide) to form a second black oxide layer. 14. The structure as described in item 10 of the scope of patent application, wherein the second substrate may be a resin layer having a thickness of about 50 to 100 / m. 15. The structure described in item 10 of the scope of patent application, wherein the material of the first metal layer on the second substrate may be copper (Cu), and the thickness is about 9 // m. 16. The structure as described in item 10 of the scope of patent application, wherein the third through hole and the first through hole can be plated with copper (Cu) and the thickness is about 1 5 // 1 7. Application The structure described in item 10 of the patent scope, wherein the third substrate material may be a Bisaleimide Triazine (BT) dielectric material or other organic thermocompression bonding material. Page 23