JP2015185617A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2015185617A JP2015185617A JP2014059198A JP2014059198A JP2015185617A JP 2015185617 A JP2015185617 A JP 2015185617A JP 2014059198 A JP2014059198 A JP 2014059198A JP 2014059198 A JP2014059198 A JP 2014059198A JP 2015185617 A JP2015185617 A JP 2015185617A
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Abstract
【解決手段】実施形態の半導体装置は、n型のSiC層と、n型のSiC層に設けられ、H(水素)、或いはD(重水素)を1×1018cm−3以上1×1022cm−3以下含有するSiC領域と、SiC領域上に設けられる金属層と、を備える。
【選択図】図1
Description
本実施形態の半導体装置は、n型のSiC層と、n型のSiC層に設けられ、H(水素)、或いはD(重水素)を1×1018cm−3以上1×1022cm−3以下含有するSiC領域と、SiC領域上に設けられる金属層と、を備える。
本実施形態の半導体装置は、p型のSiC層と、p型のSiC層に設けられ、H(水素)、或いはD(重水素)を1×1018cm−3以上1×1022cm−3以下含有し、H(水素)、或いはD(重水素)がSiCのC(炭素)サイトに位置するSiC領域と、SiC領域上に設けられる金属層と、を備える。
本実施形態の半導体装置は、半導体基板と、半導体基板の一方の側に設けられるn型のSiC層と、n型のSiC層に選択的に設けられ、H(水素)、或いはD(重水素)を1×1018cm−3以上1×1022cm−3以下含有するSiC領域と、n型のSiC層表面およびSiC領域表面に設けられるアノード電極と、半導体基板のn型のSiC層と反対側に設けられるカソード電極と、を備える。
本実施形態の半導体装置は、メサ構造を有すること以外は、第3の実施形態と同様である。したがって、第3の実施形態と重複する内容については記述を省略する。
本実施形態の半導体装置は、SiC領域14の深さが深いこと以外は、第3の実施形態と同様である。したがって、第3の実施形態と重複する内容については記述を省略する。
図18は、本実施形態の半導体装置の模式断面図である。このMOSFET(Metal Oxide Semiconductor Field Effect Transistor)400は、例えば、pウェルとソース領域をイオン注入で形成する、Double Implantation MOSFET(DIMOSFET)である。図18においては、第1の面とは図の上側の面であり、第2の面とは図の下側の面である。
図20は、本実施形態の変形例の半導体装置の模式断面図である。本変形例のMOSFET500は、DSBDが、いわゆる、transparent型であること以外は第6の実施形態と同様である。
図21は、本実施形態の半導体装置の模式断面図である。このMOSFET600は、トレンチゲート構造であること以外は、第6の実施形態と同様である。したがって、第6の実施形態と重複する内容については記述を省略する。
本実施形態の半導体装置は、p型のSiC層と、p型のSiC層に設けられ、H(水素)を1×1018cm−3以上1×1022cm−3以下含有し、H(水素)がSiCのC(炭素)サイトに位置するSiC領域と、SiC領域上に設けられる金属層と、を備える。
図23は、本実施形態の半導体装置の模式断面図である。このMOSFET800は、還流ダイオードがDSBDではなく、pウェル領域36より深いpウェルコンタクト領域41をアノード電極とすること以外は、第6の実施形態と同様である。
14 SiC領域
16 金属層
22 p型のSiC層
24 SiC領域
26 金属層
Claims (17)
- n型のSiC層と、
前記n型のSiC層に設けられ、H(水素)、或いはD(重水素)を1×1018cm−3以上1×1022cm−3以下含有するSiC領域と、
前記SiC領域上に設けられる金属層と、
を備えることを特徴とする半導体装置。 - 前記SiC領域が金属であることを特徴とする請求項1記載の半導体装置。
- 前記H(水素)、或いはD(重水素)がSiCのSi(シリコン)サイトに位置することを特徴とする請求項1または請求項2記載の半導体装置。
- 前記SiC領域の仕事関数が6.0eV以上であることを特徴とする請求項1ないし請求項3いずれか一項記載の半導体装置。
- 前記SiC領域の膜厚が1nm以上であることを特徴とする請求項1ないし請求項4いずれか一項記載の半導体装置。
- p型のSiC層と、
前記p型のSiC層に設けられ、H(水素)、或いはD(重水素)を1×1018cm−3以上1×1022cm−3以下含有し、前記H(水素)、或いはD(重水素)がSiCのC(炭素)サイトに位置するSiC領域と、
前記SiC領域上に設けられる金属層と、
を備えることを特徴とする半導体装置。 - 前記SiC領域が金属であることを特徴とする請求項6記載の半導体装置。
- 前記SiC領域の仕事関数が4.0eV以下であることを特徴とする請求項6または請求項7記載の半導体装置。
- 前記SiC領域の膜厚が1nm以上であることを特徴とする請求項6ないし請求項8いずれか一項記載の半導体装置。
- SiC層に第1の熱処理を行い、前記SiC層表面近傍の少なくとも一部のSi(シリコン)を蒸発させ、
前記SiC層に、H(水素)、或いはD(重水素)含有雰囲気で前記第1の熱処理よりも低温の第2の熱処理を行い、
前記第2の熱処理後に前記SiC層上に金属層を形成することを特徴とする半導体装置の製造方法。 - 前記金属層の形成後に、前記第2の熱処理後よりも低温の第3の熱処理を行うことを特徴とする半導体装置の請求項10記載の製造方法。
- 前記SiC層がn型であることを特徴とする請求項10または請求項11記載の半導体装置の製造方法。
- 前記第2の熱処理により、前記SiC層表面に金属のSiC領域を形成することを特徴とする請求項10ないし請求項12いずれか一項記載の半導体装置の製造方法。
- 前記第1の熱処理が1000℃以上1600℃以下であることを特徴とする請求項10ないし請求項13いずれか一項記載の半導体装置の製造方法。
- 前記第2の熱処理が400℃以上1200℃以下であることを特徴とする請求項10ないし請求項14いずれか一項記載の半導体装置の製造方法。
- 前記第2の熱処理の前記H(水素)、或いはD(重水素)含有雰囲気がプラズマH、或いはプラズマDであり、熱処理温度が0℃以上1000℃以下であることを特徴とする請求項10ないし請求項15いずれか一項記載の半導体装置の製造方法。
- 前記第3の熱処理が400℃以上1000℃以下であることを特徴とする請求項11記載の半導体装置の製造方法。
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US9601581B2 (en) | 2014-03-20 | 2017-03-21 | Kabushiki Kaisha Toshiba | Semiconductor device and method for producing the same |
JP2018137389A (ja) * | 2017-02-23 | 2018-08-30 | サンケン電気株式会社 | 半導体装置 |
WO2021161436A1 (ja) * | 2020-02-13 | 2021-08-19 | 三菱電機株式会社 | 炭化珪素半導体装置および電力変換装置の製造方法 |
JP2022508395A (ja) * | 2018-12-21 | 2022-01-19 | ヒタチ・エナジー・スウィツァーランド・アクチェンゲゼルシャフト | Mos構造およびストレッサを有する炭化珪素パワーデバイス |
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