JP2015122398A5 - - Google Patents

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Publication number
JP2015122398A5
JP2015122398A5 JP2013265007A JP2013265007A JP2015122398A5 JP 2015122398 A5 JP2015122398 A5 JP 2015122398A5 JP 2013265007 A JP2013265007 A JP 2013265007A JP 2013265007 A JP2013265007 A JP 2013265007A JP 2015122398 A5 JP2015122398 A5 JP 2015122398A5
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JP
Japan
Prior art keywords
cell
diode
basic
region
width
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JP2013265007A
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English (en)
Japanese (ja)
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JP2015122398A (ja
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Priority to JP2013265007A priority Critical patent/JP2015122398A/ja
Priority claimed from JP2013265007A external-priority patent/JP2015122398A/ja
Priority to US14/575,278 priority patent/US9430602B2/en
Priority to CN201410806910.9A priority patent/CN104733386A/zh
Publication of JP2015122398A publication Critical patent/JP2015122398A/ja
Publication of JP2015122398A5 publication Critical patent/JP2015122398A5/ja
Withdrawn legal-status Critical Current

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JP2013265007A 2013-12-24 2013-12-24 半導体集積回路装置及びそのレイアウト設計方法 Withdrawn JP2015122398A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2013265007A JP2015122398A (ja) 2013-12-24 2013-12-24 半導体集積回路装置及びそのレイアウト設計方法
US14/575,278 US9430602B2 (en) 2013-12-24 2014-12-18 Semiconductor integrated circuit device and method for designing layout of the same having standard cells, basic cells and a protective diode cell
CN201410806910.9A CN104733386A (zh) 2013-12-24 2014-12-22 半导体集成电路装置及其布局设计方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013265007A JP2015122398A (ja) 2013-12-24 2013-12-24 半導体集積回路装置及びそのレイアウト設計方法

Publications (2)

Publication Number Publication Date
JP2015122398A JP2015122398A (ja) 2015-07-02
JP2015122398A5 true JP2015122398A5 (enExample) 2016-12-22

Family

ID=53400316

Family Applications (1)

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JP2013265007A Withdrawn JP2015122398A (ja) 2013-12-24 2013-12-24 半導体集積回路装置及びそのレイアウト設計方法

Country Status (3)

Country Link
US (1) US9430602B2 (enExample)
JP (1) JP2015122398A (enExample)
CN (1) CN104733386A (enExample)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9541386B2 (en) * 2012-03-21 2017-01-10 Semiconductor Energy Laboratory Co., Ltd. Distance measurement device and distance measurement system
CN106339532B (zh) * 2016-08-18 2019-05-24 杭州旗捷科技有限公司 基础单元、标准单元、标准单元库、后端全定制设计方法、芯片
CN110998585B (zh) * 2017-06-22 2024-07-16 株式会社半导体能源研究所 布局设计系统及布局设计方法
US11003829B2 (en) * 2018-08-10 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna protection cell
CN113196463B (zh) * 2018-12-26 2024-03-01 株式会社索思未来 半导体集成电路装置
JP7758586B2 (ja) * 2022-01-28 2025-10-22 ローム株式会社 半導体集積回路
CN115954355B (zh) * 2023-03-06 2023-06-09 合肥晶合集成电路股份有限公司 半导体器件

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3130918B2 (ja) * 1990-10-31 2001-01-31 富士通株式会社 設計変更用セル及びこれを用いたレイアウト方法
US5966517A (en) * 1996-11-01 1999-10-12 Motorola, Inc. Semiconductor device using diode place-holders and method of manufacture thereof
JP3461443B2 (ja) * 1998-04-07 2003-10-27 松下電器産業株式会社 半導体装置、半導体装置の設計方法、記録媒体および半導体装置の設計支援装置
JP2000106419A (ja) * 1998-09-29 2000-04-11 Oki Electric Ind Co Ltd Ｉｃ設計用ライブラリ及びレイアウトパターン設計方法
JP2000332206A (ja) 1999-05-21 2000-11-30 Sharp Corp 半導体集積回路装置
JP4250299B2 (ja) * 2000-03-29 2009-04-08 川崎マイクロエレクトロニクス株式会社 配置配線方法
JP4629189B2 (ja) * 2000-06-14 2011-02-09 富士通セミコンダクター株式会社 レイアウト方法、レイアウト装置及び記録媒体
JP2002016143A (ja) * 2000-06-29 2002-01-18 Hitachi Ltd 半導体集積回路およびその設計方法
US6594809B2 (en) * 2000-11-29 2003-07-15 Taiwan Semiconductor Manufacturing Co., Ltd. Low leakage antenna diode insertion for integrated circuits
US7073148B1 (en) * 2003-09-11 2006-07-04 Xilinx, Inc. Antenna violation correction in high-density integrated circuits
US7956421B2 (en) * 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7843673B2 (en) * 2007-09-25 2010-11-30 Chartered Semiconductor Manufacturing, Ltd. Antenna diodes with electrical overstress (EOS) protection
US7895548B2 (en) * 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system
JP2009170515A (ja) * 2008-01-11 2009-07-30 Seiko Epson Corp 集積回路装置のレイアウト方法、集積回路装置のレイアウトプログラム、集積回路装置のレイアウトシステム、集積回路装置及び電子機器
US10192859B2 (en) * 2011-05-11 2019-01-29 Texas Instruments Incorporated Integrated circuits and processes for protection of standard cell performance from context effects
FR2999746B1 (fr) * 2012-12-13 2018-04-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de generation d'une topographie d'un circuit integre fdsoi

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