CN104733386A - 半导体集成电路装置及其布局设计方法 - Google Patents

半导体集成电路装置及其布局设计方法 Download PDF

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Publication number
CN104733386A
CN104733386A CN201410806910.9A CN201410806910A CN104733386A CN 104733386 A CN104733386 A CN 104733386A CN 201410806910 A CN201410806910 A CN 201410806910A CN 104733386 A CN104733386 A CN 104733386A
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CN
China
Prior art keywords
diode
elementary cell
region
cell
basic
Prior art date
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Pending
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CN201410806910.9A
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English (en)
Chinese (zh)
Inventor
作田孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
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Seiko Epson Corp
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Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Publication of CN104733386A publication Critical patent/CN104733386A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10—Integrated device layouts

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
CN201410806910.9A 2013-12-24 2014-12-22 半导体集成电路装置及其布局设计方法 Pending CN104733386A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2013-265007 2013-12-24
JP2013265007A JP2015122398A (ja) 2013-12-24 2013-12-24 半導体集積回路装置及びそのレイアウト設計方法

Publications (1)

Publication Number Publication Date
CN104733386A true CN104733386A (zh) 2015-06-24

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Family Applications (1)

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CN201410806910.9A Pending CN104733386A (zh) 2013-12-24 2014-12-22 半导体集成电路装置及其布局设计方法

Country Status (3)

Country Link
US (1) US9430602B2 (enExample)
JP (1) JP2015122398A (enExample)
CN (1) CN104733386A (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106339532A (zh) * 2016-08-18 2017-01-18 杭州旗捷科技有限公司 基础单元、标准单元、标准单元库、后端全定制设计方法、芯片
CN110998585A (zh) * 2017-06-22 2020-04-10 株式会社半导体能源研究所 布局设计系统及布局设计方法
CN113196463A (zh) * 2018-12-26 2021-07-30 株式会社索思未来 半导体集成电路装置

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9541386B2 (en) * 2012-03-21 2017-01-10 Semiconductor Energy Laboratory Co., Ltd. Distance measurement device and distance measurement system
US11003829B2 (en) * 2018-08-10 2021-05-11 Taiwan Semiconductor Manufacturing Company, Ltd. Antenna protection cell
JP7758586B2 (ja) * 2022-01-28 2025-10-22 ローム株式会社 半導体集積回路
CN115954355B (zh) * 2023-03-06 2023-06-09 合肥晶合集成电路股份有限公司 半导体器件

Citations (5)

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JP2000106419A (ja) * 1998-09-29 2000-04-11 Oki Electric Ind Co Ltd Ｉｃ設計用ライブラリ及びレイアウトパターン設計方法
JP2002016143A (ja) * 2000-06-29 2002-01-18 Hitachi Ltd 半導体集積回路およびその設計方法
US20020066067A1 (en) * 2000-11-29 2002-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Low leakage antenna diode insertion for integrated circuits
US20030135835A1 (en) * 2000-06-14 2003-07-17 Fujitsu Limited Method of designing layout of semiconductor device
JP2009170515A (ja) * 2008-01-11 2009-07-30 Seiko Epson Corp 集積回路装置のレイアウト方法、集積回路装置のレイアウトプログラム、集積回路装置のレイアウトシステム、集積回路装置及び電子機器

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JP3130918B2 (ja) * 1990-10-31 2001-01-31 富士通株式会社 設計変更用セル及びこれを用いたレイアウト方法
US5966517A (en) * 1996-11-01 1999-10-12 Motorola, Inc. Semiconductor device using diode place-holders and method of manufacture thereof
JP3461443B2 (ja) * 1998-04-07 2003-10-27 松下電器産業株式会社 半導体装置、半導体装置の設計方法、記録媒体および半導体装置の設計支援装置
JP2000332206A (ja) 1999-05-21 2000-11-30 Sharp Corp 半導体集積回路装置
JP4250299B2 (ja) * 2000-03-29 2009-04-08 川崎マイクロエレクトロニクス株式会社 配置配線方法
US7073148B1 (en) * 2003-09-11 2006-07-04 Xilinx, Inc. Antenna violation correction in high-density integrated circuits
US7956421B2 (en) * 2008-03-13 2011-06-07 Tela Innovations, Inc. Cross-coupled transistor layouts in restricted gate level layout architecture
US7843673B2 (en) * 2007-09-25 2010-11-30 Chartered Semiconductor Manufacturing, Ltd. Antenna diodes with electrical overstress (EOS) protection
US7895548B2 (en) * 2007-10-26 2011-02-22 Synopsys, Inc. Filler cells for design optimization in a place-and-route system
US10192859B2 (en) * 2011-05-11 2019-01-29 Texas Instruments Incorporated Integrated circuits and processes for protection of standard cell performance from context effects
FR2999746B1 (fr) * 2012-12-13 2018-04-27 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de generation d'une topographie d'un circuit integre fdsoi

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000106419A (ja) * 1998-09-29 2000-04-11 Oki Electric Ind Co Ltd Ｉｃ設計用ライブラリ及びレイアウトパターン設計方法
US20030135835A1 (en) * 2000-06-14 2003-07-17 Fujitsu Limited Method of designing layout of semiconductor device
JP2002016143A (ja) * 2000-06-29 2002-01-18 Hitachi Ltd 半導体集積回路およびその設計方法
US20020066067A1 (en) * 2000-11-29 2002-05-30 Taiwan Semiconductor Manufacturing Co., Ltd. Low leakage antenna diode insertion for integrated circuits
JP2009170515A (ja) * 2008-01-11 2009-07-30 Seiko Epson Corp 集積回路装置のレイアウト方法、集積回路装置のレイアウトプログラム、集積回路装置のレイアウトシステム、集積回路装置及び電子機器

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106339532A (zh) * 2016-08-18 2017-01-18 杭州旗捷科技有限公司 基础单元、标准单元、标准单元库、后端全定制设计方法、芯片
CN106339532B (zh) * 2016-08-18 2019-05-24 杭州旗捷科技有限公司 基础单元、标准单元、标准单元库、后端全定制设计方法、芯片
CN110998585A (zh) * 2017-06-22 2020-04-10 株式会社半导体能源研究所 布局设计系统及布局设计方法
CN113196463A (zh) * 2018-12-26 2021-07-30 株式会社索思未来 半导体集成电路装置
CN113196463B (zh) * 2018-12-26 2024-03-01 株式会社索思未来 半导体集成电路装置

Also Published As

Publication number Publication date
US20150178433A1 (en) 2015-06-25
US9430602B2 (en) 2016-08-30
JP2015122398A (ja) 2015-07-02

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Application publication date: 20150624