JP2015115582A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2015115582A JP2015115582A JP2013259064A JP2013259064A JP2015115582A JP 2015115582 A JP2015115582 A JP 2015115582A JP 2013259064 A JP2013259064 A JP 2013259064A JP 2013259064 A JP2013259064 A JP 2013259064A JP 2015115582 A JP2015115582 A JP 2015115582A
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- layer
- nitride semiconductor
- semiconductor layer
- semiconductor device
- film
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Abstract
Description
以下、図面を参照しながら本実施の形態の半導体装置について詳細に説明する。
図1は、本実施の形態の半導体装置の構成を模式的に示す断面図である。図1等に示す本実施の形態の半導体装置(半導体素子)は、窒化物半導体を用いたMIS(Metal Insulator Semiconductor)型の電界効果トランジスタ(FET;Field Effect Transistor)である。この半導体装置は、高電子移動度トランジスタ(HEMT:High Electron Mobility Transistor)型のパワートランジスタとして用いることができる。本実施の形態の半導体装置は、いわゆるリセスゲート型の半導体装置である。
次いで、図5〜図22を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図5〜図22は、本実施の形態の半導体装置の製造工程を示す断面図または平面図である。
実施の形態1においては、素子分離領域ISOに接続部VIAを設けたが、活性領域ACに接続部VIAを設けてもよい。例えば、本実施の形態においては、ソース電極SEの下に接続部VIAを設ける。
図26は、本実施の形態の半導体装置の構成を模式的に示す断面図である。本実施の形態の半導体装置(半導体素子)は、窒化物半導体を用いたMIS型の電界効果トランジスタである。この半導体装置は、高電子移動度トランジスタ(HEMT)型のパワートランジスタとして用いることができる。本実施の形態の半導体装置は、いわゆるリセスゲート型の半導体装置である。
次いで、図29〜図34を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。図29〜図34は、本実施の形態の半導体装置の製造工程を示す断面図または平面図である。
実施の形態1および2においては、リセスゲート型の半導体装置を例示したが、他の構成の半導体装置としてもよい。例えば、本実施の形態のように、ゲート電極の下にゲート接合層を配置した接合型の半導体装置を用いてもよい。
図35は、本実施の形態の半導体装置の構成を模式的に示す断面図である。本実施の形態の半導体装置(半導体素子)は、窒化物半導体を用いたトランジスタである。この半導体装置は、高電子移動度トランジスタ(HEMT)型のパワートランジスタとして用いることができる。
次いで、図36〜図40を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。
実施の形態3においては、素子分離領域ISOに接続部VIAを設けたが、活性領域ACに接続部VIAを設けてもよい。例えば、本実施の形態においては、ソース電極SEの下に接続部VIAを設ける。
図41は、本実施の形態の半導体装置の構成を模式的に示す断面図である。本実施の形態の半導体装置(半導体素子)は、窒化物半導体を用いたトランジスタである。この半導体装置は、高電子移動度トランジスタ(HEMT)型のパワートランジスタとして用いることができる。
次いで、図42を参照しながら、本実施の形態の半導体装置の製造方法を説明するとともに、当該半導体装置の構成をより明確にする。
BA 障壁層
BU バッファ層
C1D コンタクトホール
C1S コンタクトホール
CH チャネル層
CP キャップ層
DE ドレイン電極
DP ドレインパッド
GE ゲート電極
GI ゲート絶縁膜
GL ゲート線
GLT 溝
IF1 絶縁膜
IL1 層間絶縁膜
ISO 素子分離領域
JL ゲート接合層
NUC 核生成層
PR1 フォトレジスト膜
PR2 フォトレジスト膜
PRO 保護膜
S 基板
SE ソース電極
SP ソースパッド
T 溝
TH 貫通孔
UC チャネル下地層
VC 電位固定層
VIA 接続部
Claims (20)
- 基板の上方に形成された第1窒化物半導体層と、
前記第1窒化物半導体層上に形成された第2窒化物半導体層と、
前記第2窒化物半導体層上に形成された第3窒化物半導体層と、
前記第3窒化物半導体層上に形成された第4窒化物半導体層と、
前記第4窒化物半導体層を貫通し、前記第3窒化物半導体層の途中まで到達する溝と、
前記溝内にゲート絶縁膜を介して配置されたゲート電極と、
前記ゲート電極の両側の前記第4窒化物半導体層の上方にそれぞれ形成された第1電極および第2電極と、
前記第1電極と第1窒化物半導体層との間を接続する接続部と、
を有し、
前記第3窒化物半導体層の電子親和力は、前記第2窒化物半導体層の電子親和力より大きく、
前記第4窒化物半導体層の電子親和力は、前記第2窒化物半導体層の電子親和力より小さく、
前記第1窒化物半導体層は、p型またはn型の不純物を含有する、半導体装置。 - 請求項1記載の半導体装置において、
前記基板は、第1領域と第2領域とを有し、
前記ゲート電極、前記第1電極および前記第2電極は、前記第1領域に形成され、
前記第2領域は、前記第4窒化物半導体層および第3窒化物半導体層中に形成された素子分離領域であり、
前記接続部は、前記素子分離領域および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層まで到達する貫通孔の内部に配置されている、半導体装置。 - 請求項2記載の半導体装置において、
前記接続部上には、前記第1電極と電気的に接続される第1端子部が、配置されている、半導体装置。 - 請求項2記載の半導体装置において、
前記貫通孔の底面が、前記第1窒化物半導体層の底面より下に位置する、半導体装置。 - 請求項2記載の半導体装置において、
前記貫通孔の底面が、前記第1窒化物半導体層の表面または前記第1窒化物半導体層の途中に位置する、半導体装置。 - 請求項2記載の半導体装置において、
前記第1窒化物半導体層は、p型の不純物を含有する、半導体装置。 - 請求項2記載の半導体装置において、
前記基板と前記第1窒化物半導体層との間に超格子層を有し、
前記超格子層は、第5窒化物半導体層と、前記第5窒化物半導体層と電子親和力の異なる第6窒化物半導体層との積層体が2以上繰り返し配置されている、半導体装置。 - 請求項1記載の半導体装置において、
前記接続部は、前記第4窒化物半導体層、前記第3窒化物半導体層および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層まで到達する貫通孔の内部に配置されている、半導体装置。 - 請求項8記載の半導体装置において、
前記接続部上には、前記第1電極が、配置されている、半導体装置。 - 請求項8記載の半導体装置において、
前記貫通孔の底面が、前記第1窒化物半導体層の底面より下に位置する、半導体装置。 - 請求項8記載の半導体装置において、
前記貫通孔の底面が、前記第1窒化物半導体層の表面または前記第1窒化物半導体層の途中に位置する、半導体装置。 - 請求項8記載の半導体装置において、
前記第1窒化物半導体層は、p型の不純物を含有する、半導体装置。 - 請求項8記載の半導体装置において、
前記基板と前記第1窒化物半導体層との間に超格子層を有し、
前記超格子層は、第5窒化物半導体層と、前記第5窒化物半導体層と電子親和力の異なる第6窒化物半導体層との積層体が2以上繰り返し配置されている、半導体装置。 - 基板の上方に形成された第1窒化物半導体層と、
前記第1窒化物半導体層上に形成された第2窒化物半導体層と、
前記第2窒化物半導体層上に形成された第3窒化物半導体層と、
前記第3窒化物半導体層上に形成された第4窒化物半導体層と、
前記第4窒化物半導体層の上方に、第5窒化物半導体層を介して配置されたゲート電極と、
前記ゲート電極の両側の前記第4窒化物半導体層の上方にそれぞれ形成された第1電極および第2電極と、
前記第1電極と第1窒化物半導体層との間を接続する接続部と、
を有し、
前記第3窒化物半導体層の電子親和力は、前記第2窒化物半導体層の電子親和力より大きく、
前記第4窒化物半導体層の電子親和力は、前記第2窒化物半導体層の電子親和力より小さく、
前記第5窒化物半導体層の電子親和力は、前記第4窒化物半導体層の電子親和力より大きく、
前記第1窒化物半導体層は、p型またはn型の不純物を含有する、半導体装置。 - 請求項14記載の半導体装置において、
前記基板は、第1領域と第2領域とを有し、
前記ゲート電極、前記第1電極および前記第2電極は、前記第1領域に形成され、
前記第2領域は、前記第4窒化物半導体層および第3窒化物半導体層中に形成された素子分離領域であり、
前記接続部は、前記素子分離領域および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層まで到達する貫通孔の内部に配置されている、半導体装置。 - 請求項15記載の半導体装置において、
前記接続部上には、前記第1電極と電気的に接続される第1端子部が、配置されている、半導体装置。 - 請求項15記載の半導体装置において、
前記貫通孔の底面が、前記第1窒化物半導体層の表面または前記第1窒化物半導体層の途中に位置する、半導体装置。 - 請求項14記載の半導体装置において、
前記接続部は、前記第4窒化物半導体層、前記第3窒化物半導体層および前記第2窒化物半導体層を貫通し、前記第1窒化物半導体層まで到達する貫通孔の内部に配置されている、半導体装置。 - 請求項18記載の半導体装置において、
前記接続部上には、前記第1電極が、配置されている、半導体装置。 - 請求項18記載の半導体装置において、
前記貫通孔の底面が、前記第1窒化物半導体層の表面または前記第1窒化物半導体層の途中に位置する、半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2013259064A JP6534791B2 (ja) | 2013-12-16 | 2013-12-16 | 半導体装置 |
KR1020140163391A KR20150070001A (ko) | 2013-12-16 | 2014-11-21 | 반도체 장치 |
TW103140804A TW201528503A (zh) | 2013-12-16 | 2014-11-25 | 半導體裝置 |
EP14197151.5A EP2884539A1 (en) | 2013-12-16 | 2014-12-10 | Semiconductor device |
US14/569,492 US9601609B2 (en) | 2013-12-16 | 2014-12-12 | Semiconductor device |
CN201410784150.6A CN104716176B (zh) | 2013-12-16 | 2014-12-16 | 半导体器件 |
US15/437,559 US10014403B2 (en) | 2013-12-16 | 2017-02-21 | Semiconductor device |
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JP6534791B2 (ja) | 2019-06-26 |
KR20150070001A (ko) | 2015-06-24 |
US20170162683A1 (en) | 2017-06-08 |
TW201528503A (zh) | 2015-07-16 |
US20150171204A1 (en) | 2015-06-18 |
CN104716176B (zh) | 2019-06-14 |
US10014403B2 (en) | 2018-07-03 |
US9601609B2 (en) | 2017-03-21 |
EP2884539A1 (en) | 2015-06-17 |
CN104716176A (zh) | 2015-06-17 |
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